atmel atf280e rad hard sram based fpga see test results application oriented seu sensitiveness...

ATMEL ATF280E Rad Hard SRAM Based FPGA

SEE test results Application oriented SEU Sensitiveness

Bernard BANCELIN

ATMEL Nantes SAS,

Aerospace Business Unit

Aug 13, 2009Bernard BANCELIN ATMEL 2

MAPLD 2009 / FPGAs for Space

Overview

Atmel FPGA Key Points and Architecture

ATF280E Radiation Test Results

Application oriented SEU sensitiveness



Overview






ATF280E Block-Diagram

FPGACore

120 x 120 core-cells30 x 30 FreeRAMs

Config.SRAM

Boundary Scan

Controller

LVDS Interface8 Rx / 8 Tx

UserI/O

Configuration

Self IntegrityChecker

Config.Control

POR

ConfigurationLoad

Checker

DifferentialClocks

8 Global / 4 Fast



FPGA Architecture Overview

CGK1-CGK8

FCK1-2

Sector Clock Mux

Column Clock Mux



Atmel Radiation Hardened FPGAs

Layout rules Improved to avoid multiple nodes charge collection during a

single heavy ion impact

SEU hardened Memory points Core cell Flip-Flops, embedded memory, configuration

memory based on radiation hardened Flip-Flops

Controller protected by classical TMR Including combinatorial logic and flip-flop of all states

machines

FreeRAM address decoders, clock and reset trees Protected by DMR (resistive isolation path based on N and P

isolated path carrying the same signal)

Your Design is radiation Hardened by construction No need for SEU/SET mitigation



Hardened Flip-flop and Isolation Path



Overview






ATC18RHA Radiation Performances

ATF280 and AT697F (100MHz Leon2FT) use the same ASIC technology

ATC18RHA, 0.18µm technology

TID tested up to 300 Krad without parameters drift

No SEL up to 70 MeV.cm²/mg@125°C

SEU: - ATC18RHA SEU hardened DFF: LET threshold of 30 MeV/mg/cm2)

- Genesys memory synthesizer: LET threshold of 25 MeV/mg/cm2),

- very good SEU hardening results obtained for the compiled memories when used with error correction code (very low saturated cross section), resulting into a bit error rate improved by a factor > 1000 in GEO orbit.

- sensitivity of the standard DFF to SEU (LET threshold of 2 MeV/mg/cm2).

- very low SEU sensitivity of the ATC18RHA PLL.

- for small memory blocks, the interest of using the SEU hardened synthesized memories rather than the compiled memories, even with Error Correction Code (error rate per bit improved by a factor > 100).



Test Principles

Functionality and Immunity Test configurations Reset : configuration memory reset to low level (‘0’). Multiplier: configuration memory set to high level (‘1’). Shift register: core cell flip-flops and clock tree to upset. Inverted shift register: core cell flip-flops and clock tree to upset as the combinatorial path

to transients. And chain: combinatorial path to transients. Free RAM: integrated FreeRAM block tested as 4K words of 16 Bits dual-port RAM. Free RAM with EDAC: integrated FreeRAM block tested as 4K words of 16 Bits dual-port

RAM with an “Error Detector and Correction” EDAC system.

Test conditions Configuration clock frequency 1MHz IOs supply in the range 3V to 3.6V, nominal 3.3V Core voltage in the range 1.65V to 1.95V, nominal 1.8V Package temperature control for Latch-Up sensitivity

Test operator and location Test is run by HIREX (France) Test locations:

- UCL Louvain, Belgium- BNL Berkeley, USA- RADEF Jyvaskyla, Finland



Test Results

Single Event Latch-up No SEL detected over all the runs performed and in particular with the runs

performed at 1.95V core voltage and 3.6V I/O buffer at LBNL with Xenon and 45 deg tilting angle that corresponds to a LET of 76 MeV/(mg/cm²) and a device under test (DUT) temperature of 125°C, up to fluence of 1.10+7 part/cm².

Cross section The configuration SEU error cross section per device versus effective LET is

derived from the tests performed in UCL, BNL and RADEF.- Configuration memory SEU saturated cross-section better than 5.10-3 per device

(3.10-9 cm² per bit) with a LET threshold around 30MeV at Vcc min. - No SET was recorded with a LET of 43 MeV/(mg/cm²). - SET error cross-section per device about 1.6 10-4 at 60MeV/(mg/cm²). - FreeRAM Asymptotic SEU error cross-section per bit about 6.5 10-8 cm².

Test operator and location Test is run by HIREX (France) Test locations:

- UCL Louvain, Belgium- BNL Berkeley, USA- RADEF Jyvaskyla, Finland



SEU sensitivity of ATF280E configuration bits C onfiguration S E U

1.00E -07

1.00E -06

1.00E -05

1.00E -04

1.00E -03

1.00E -02

0 10 20 30 40 50 60 70 80

L E T MeV /(mg/c m2)

X-S

ectio

n /

devi

ce

cm

2

L B NL 1.65V R es et L B NL 1.77V R es et L B NL 1.65V Inverter + R egis ter L B NL 1.95 R egis ter 125°C L B NL 1.65 R egis ter

L B NL 1.77 V Multiplier L B NL 1.65V Multiplier L B NL 1.65V A ND UC L 1.65V Multiplier UC L 1.65V R es et



SEU sensitivity of ATF280E configuration bits



Calculated error rate for different orbits

Orbit Inclination Perigee Apogee Error Rate MTBF

(Deg) kms kms device/day years

GEO 0 35786 35786 1.87E-03 1.4

LEO ISS 51.5 400 400 1.84E-04 14.8

MEO 63.4 1000 26768 2.24E-03 1.22



Overview






Principle

Applications in RHBD SRAM-based FPGAs uses only part of the available resources

Device reliability gives the worst case considering that all resources are used

Application oriented sensitiveness analysis tools identify sensitive configuration memory bits and user RAM bits

Estimated critical configuration bits will give an application cross-section giving a more realistic result



Methodology

Extract programmed configuration bits in the application

Design structure and device architecture generation

Configuration bits analysis: - Bits once upset change the

function of the used resources

- Bits once upset propagate an output connected to external resources

bitstream

ARDfile

Resource usage

analysis

Configuration bits analysis

Criticality conditions

Sensitive bits report

Architecture tree

generation

Step 1

Step 2



Methodology

Logic cells / Bus repeaters

Critical internal / Critical external

Architecture elements: - Set

- Out

- LUT

- Common path

- Root




SET

SET

LUT

OUT OUT

FFD

Q

Programmable switch



Preliminary Results

Logic cells / Bus repeaters

Critical internal / Critical external

Architecture elements: - Set

- Out

- LUT

- Common path

- Root




CircuitProgrammed

Bits [%]

Resource Usage

[%]

Weighted Sensitiveness

[%]

B01 0.01 0.07 0.05

B03 0.07 0.33 0.20

B04 0.20 1.16 0.80

B08 0.10 0.48 0.31

B11 0.17 0.77 0.60

B12 0.48 2.61 1.62

B14 2.03 12.77 7.78

B08_chain 2.40 11.58 7.46



Conclusion

Application Oriented SEU sensitiveness Future works:

- Fault injection platform for adding a dynamic analysis

Work done in collaboration with ESA and Politechnico di Torino (Italy)

RHBD FPGA ATF280

- samples already available and designs on going

- Improvement of power-on current (maximum in worst case conditions 1A during 10µs)

ATFS450 development on going, using 150nm SOI process

New architecture for 2.5Mgates RHBD SRAM based FPGA for 2012, 65nm process

atmel atf280e rad hard sram based fpga see test results application oriented seu sensitiveness...

Documents