attiny417/814/816/817 · 2020. 12. 17. · • 1.1v • 1.5v • 2.5v • 4.3v – event system...

ATtiny417/814/816/817 tinyAVR® 1-series

IntroductionThe ATtiny417/814/816/817 are members of the tinyAVR®1-series of microcontrollers, using the AVR® processor withhardware multiplier, running at up to 20 MHz, with 4/8 KB Flash, 256/512 bytes of SRAM, and 128 bytes of EEPROMin a 14-, 20- and 24-pin package. The tinyAVR®1-series uses the latest technologies with a flexible, low-powerarchitecture, including Event System, accurate analog features, and Core Independent Peripherals (CIPs).Capacitivetouch interfaces with Driven Shield+ and Boost Mode technologies are supported with the integrated PeripheralTouch Controller (PTC).

Attention: Automotive products are documented in separate data sheets.

Features• CPU

– AVR® CPU– Running at up to 20 MHz– Single-cycle I/O access– Two-level interrupt controller– Two-cycle hardware multiplier

• Memories– 4/8 KB In-system self-programmable Flash memory– 128 bytes EEPROM– 256/512 bytes SRAM– Write/erase endurance:

• Flash 10,000 cycles• EEPROM 100,000 cycles

– Data retention:• 40 years at 55°C

• System– Power-on Reset (POR)– Brown-out Detector (BOD)– Clock options:

• 16/20 MHz low-power internal RC oscillator• 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator• 32.768 kHz external crystal oscillator• External clock input

– Single-Pin Unified Program and Debug Interface (UPDI)– Three sleep modes:

© 2020 Microchip Technology Inc. Complete Datasheet DS40002288A-page 1

• Idle with all peripherals running for immediate wake-up• Standby

– Configurable operation of selected peripherals• Power-Down with full data retention

• Peripherals– One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three compare channels– One 16-bit Timer/Counter type B (TCB) with input capture– One 12-bit Timer/Counter type D (TCD) optimized for control applications– One 16-bit Real-Time Counter (RTC) running from an external crystal, external clock, or internal RC

oscillator– Watchdog Timer (WDT) with Window mode, with a separate on-chip oscillator– One USART with fractional baud rate generator, auto-baud, and start-of-frame detection– One host/client Serial Peripheral Interface (SPI)– One Two-Wire Interface (TWI) with dual address match

• Philips I2C compatible• Standard mode (Sm, 100 kHz)• Fast mode (Fm, 400 kHz)• Fast mode plus (Fm+, 1 MHz)

– Analog Comparator (AC) with a low propagation delay– 10-bit 115 ksps Analog-to-Digital Converter (ADC)– 8-bit Digital-to-Analog Converter (DAC) with one external channel– Multiple voltage references (VREF):

• 0.55V• 1.1V• 1.5V• 2.5V• 4.3V

– Event System (EVSYS) for CPU independent and predictable inter-peripheral signaling– Configurable Custom Logic (CCL) with two programmable look-up tables– Automated CRC memory scan– Peripheral Touch Controller (PTC)(1)

• Capacitive touch buttons, sliders, wheels and 2D surfaces• Wake-up on touch• Driven shield for improved moisture and noise handling performance• 6 self-capacitance channels• 9 mutual capacitance channels

– External interrupt on all general purpose pins• I/O and Packages:

– Up to 22 programmable I/O lines– 14-pin SOIC150– 20-pin SOIC300– 20-pin VQFN 3x3 mm– 24-pin VQFN 4x4 mm

• Temperature Ranges:– -40°C to 105°C– -40°C to 125°C

• Speed Grades:– 0-5 MHz @ 1.8V – 5.5V– 0-10 MHz @ 2.7V – 5.5V– 0-20 MHz @ 4.5V – 5.5V

ATtiny417/814/816/817


Note: 1. PTC is available on devices with 8 KB flash or more.

ATtiny417/814/816/817


Table of Contents

Introduction.....................................................................................................................................................1

Features......................................................................................................................................................... 1

1. Silicon Errata and Data Sheet Clarification Document..........................................................................11

2. tinyAVR® 1-series Overview..................................................................................................................12

2.1. Configuration Summary..............................................................................................................12

3. Block Diagram.......................................................................................................................................14

4. Pinout.................................................................................................................................................... 15

4.1. 14-Pin SOIC............................................................................................................................... 154.2. 20-Pin SOIC............................................................................................................................... 164.3. 20-Pin VQFN..............................................................................................................................174.4. 24-Pin VQFN..............................................................................................................................18

5. I/O Multiplexing and Considerations..................................................................................................... 19

5.1. Multiplexed Signals.................................................................................................................... 19

6. Memories.............................................................................................................................................. 20

6.1. Overview.................................................................................................................................... 206.2. Memory Map.............................................................................................................................. 216.3. In-System Reprogrammable Flash Program Memory................................................................216.4. SRAM Data Memory.................................................................................................................. 226.5. EEPROM Data Memory............................................................................................................. 226.6. User Row....................................................................................................................................226.7. Signature Bytes..........................................................................................................................226.8. I/O Memory.................................................................................................................................236.9. Memory Section Access from CPU and UPDI on Locked Device..............................................256.10. Configuration and User Fuses (FUSE).......................................................................................26

7. Peripherals and Architecture.................................................................................................................45

7.1. Peripheral Address Map.............................................................................................................457.2. Interrupt Vector Mapping............................................................................................................467.3. System Configuration (SYSCFG)...............................................................................................47

8. AVR® CPU............................................................................................................................................ 50

8.1. Features..................................................................................................................................... 508.2. Overview.................................................................................................................................... 508.3. Architecture................................................................................................................................ 508.4. Arithmetic Logic Unit (ALU)........................................................................................................528.5. Functional Description................................................................................................................528.6. Register Summary......................................................................................................................588.7. Register Description...................................................................................................................58

9. NVMCTRL - Nonvolatile Memory Controller......................................................................................... 62

9.1. Features..................................................................................................................................... 62

ATtiny417/814/816/817


9.2. Overview.................................................................................................................................... 629.3. Functional Description................................................................................................................639.4. Register Summary......................................................................................................................699.5. Register Description...................................................................................................................69

10. CLKCTRL - Clock Controller................................................................................................................. 77

10.1. Features..................................................................................................................................... 7710.2. Overview.................................................................................................................................... 7710.3. Functional Description................................................................................................................7910.4. Register Summary......................................................................................................................8310.5. Register Description...................................................................................................................83

11. SLPCTRL - Sleep Controller................................................................................................................. 93

11.1. Features..................................................................................................................................... 9311.2. Overview.................................................................................................................................... 9311.3. Functional Description................................................................................................................9311.4. Register Summary......................................................................................................................9711.5. Register Description...................................................................................................................97

12. RSTCTRL - Reset Controller................................................................................................................ 99

12.1. Features..................................................................................................................................... 9912.2. Overview.................................................................................................................................... 9912.3. Functional Description..............................................................................................................10012.4. Register Summary....................................................................................................................10412.5. Register Description.................................................................................................................104

13. CPUINT - CPU Interrupt Controller..................................................................................................... 107

13.1. Features................................................................................................................................... 10713.2. Overview.................................................................................................................................. 10713.3. Functional Description..............................................................................................................10813.4. Register Summary ...................................................................................................................11313.5. Register Description................................................................................................................. 113

14. EVSYS - Event System....................................................................................................................... 118

14.1. Features................................................................................................................................... 11814.2. Overview...................................................................................................................................11814.3. Functional Description..............................................................................................................12014.4. Register Summary....................................................................................................................12214.5. Register Description.................................................................................................................122

15. PORTMUX - Port Multiplexer.............................................................................................................. 129

15.1. Overview.................................................................................................................................. 12915.2. Register Summary....................................................................................................................13015.3. Register Description.................................................................................................................130

16. PORT - I/O Pin Configuration..............................................................................................................135

16.1. Features................................................................................................................................... 13516.2. Overview.................................................................................................................................. 13516.3. Functional Description..............................................................................................................137

ATtiny417/814/816/817


16.4. Register Summary - PORTx.....................................................................................................14016.5. Register Description - PORTx.................................................................................................. 14016.6. Register Summary - VPORTx.................................................................................................. 15216.7. Register Description - VPORTx................................................................................................152

17. BOD - Brown-out Detector.................................................................................................................. 157

17.1. Features................................................................................................................................... 15717.2. Overview.................................................................................................................................. 15717.3. Functional Description..............................................................................................................15817.4. Register Summary....................................................................................................................16017.5. Register Description.................................................................................................................160

18. VREF - Voltage Reference..................................................................................................................167

18.1. Features................................................................................................................................... 16718.2. Overview.................................................................................................................................. 16718.3. Functional Description..............................................................................................................16718.4. Register Summary ...................................................................................................................16818.5. Register Description.................................................................................................................168

19. WDT - Watchdog Timer.......................................................................................................................171

19.1. Features................................................................................................................................... 17119.2. Overview.................................................................................................................................. 17119.3. Functional Description..............................................................................................................17219.4. Register Summary - WDT........................................................................................................ 17519.5. Register Description.................................................................................................................175

20. TCA - 16-bit Timer/Counter Type A.....................................................................................................178

20.1. Features................................................................................................................................... 17820.2. Overview.................................................................................................................................. 17820.3. Functional Description..............................................................................................................18020.4. Register Summary - Normal Mode...........................................................................................19020.5. Register Description - Normal Mode........................................................................................ 19020.6. Register Summary - Split Mode............................................................................................... 20920.7. Register Description - Split Mode.............................................................................................209

21. TCB - 16-Bit Timer/Counter Type B.................................................................................................... 225


22. TCD - 12-Bit Timer/Counter Type D.................................................................................................... 246


23. RTC - Real-Time Counter................................................................................................................... 296

ATtiny417/814/816/817


23.1. Features................................................................................................................................... 29623.2. Overview.................................................................................................................................. 29623.3. Clocks.......................................................................................................................................29723.4. RTC Functional Description..................................................................................................... 29723.5. PIT Functional Description....................................................................................................... 29823.6. Events...................................................................................................................................... 29923.7. Interrupts.................................................................................................................................. 30023.8. Sleep Mode Operation............................................................................................................. 30123.9. Synchronization........................................................................................................................30123.10. Debug Operation......................................................................................................................30123.11. Register Summary....................................................................................................................30223.12. Register Description.................................................................................................................302

24. USART - Universal Synchronous and Asynchronous Receiver and Transmitter................................318


25. SPI - Serial Peripheral Interface..........................................................................................................351


26. TWI - Two-Wire Interface.................................................................................................................... 366


27. CRCSCAN - Cyclic Redundancy Check Memory Scan...................................................................... 395

27.1. Features................................................................................................................................... 39527.2. Overview.................................................................................................................................. 39527.3. Functional Description..............................................................................................................39627.4. Register Summary - CRCSCAN...............................................................................................39927.5. Register Description.................................................................................................................399

28. CCL - Configurable Custom Logic...................................................................................................... 403


29. AC - Analog Comparator.....................................................................................................................419

ATtiny417/814/816/817



30. ADC - Analog-to-Digital Converter...................................................................................................... 428

30.1. Features................................................................................................................................... 42830.2. Overview.................................................................................................................................. 42830.3. Functional Description..............................................................................................................42930.4. Register Summary - ADCn.......................................................................................................43730.5. Register Description.................................................................................................................437

31. DAC - Digital-to-Analog Converter...................................................................................................... 455


32. PTC - Peripheral Touch Controller...................................................................................................... 461

32.1. Overview.................................................................................................................................. 46132.2. Features................................................................................................................................... 46132.3. Block Diagram..........................................................................................................................46232.4. Signal Description.................................................................................................................... 46232.5. System Dependencies............................................................................................................. 46332.6. Functional Description..............................................................................................................464

33. UPDI - Unified Program and Debug Interface.....................................................................................465


34. Instruction Set Summary.....................................................................................................................498

35. Conventions........................................................................................................................................ 499

35.1. Numerical Notation...................................................................................................................49935.2. Memory Size and Type.............................................................................................................49935.3. Frequency and Time.................................................................................................................49935.4. Registers and Bits.................................................................................................................... 50035.5. ADC Parameter Definitions...................................................................................................... 501

36. Electrical Characteristics.....................................................................................................................504

36.1. Disclaimer.................................................................................................................................50436.2. Absolute Maximum Ratings .....................................................................................................50436.3. General Operating Ratings ......................................................................................................50536.4. Power Consumption.................................................................................................................50636.5. Wake-Up Time..........................................................................................................................508

ATtiny417/814/816/817


36.6. Peripherals Power Consumption..............................................................................................50836.7. BOD and POR Characteristics.................................................................................................50936.8. External Reset Characteristics.................................................................................................51036.9. Oscillators and Clocks..............................................................................................................51036.10. I/O Pin Characteristics............................................................................................................. 51236.11. TCD..........................................................................................................................................51336.12. USART.....................................................................................................................................51336.13. SPI........................................................................................................................................... 51436.14. TWI...........................................................................................................................................51536.15. VREF........................................................................................................................................51836.16. ADC..........................................................................................................................................51936.17. TEMPSENSE...........................................................................................................................52136.18. DAC..........................................................................................................................................52236.19. AC............................................................................................................................................ 52336.20. PTC..........................................................................................................................................52336.21. UPDI Timing.............................................................................................................................52436.22. Programming Time...................................................................................................................525

37. Typical Characteristics........................................................................................................................ 526

37.1. Power Consumption.................................................................................................................52637.2. GPIO........................................................................................................................................ 53437.3. VREF Characteristics...............................................................................................................54137.4. BOD Characteristics.................................................................................................................54337.5. ADC Characteristics.................................................................................................................54637.6. TEMPSENSE Characteristics.................................................................................................. 55137.7. AC Characteristics....................................................................................................................55237.8. OSC20M Characteristics..........................................................................................................55637.9. OSCULP32K Characteristics................................................................................................... 55837.10. TWI SDA Hold Timing ............................................................................................................. 559

38. Ordering Information........................................................................................................................... 560

38.1. Product Information..................................................................................................................56038.2. Product Identification System...................................................................................................560

39. Package Drawings.............................................................................................................................. 562

39.1. Online Package Drawings........................................................................................................56239.2. 14-Pin SOIC............................................................................................................................. 56339.3. 20-Pin SOIC............................................................................................................................. 56639.4. 20-Pin VQFN............................................................................................................................56939.5. 24-Pin VQFN............................................................................................................................57239.6. Thermal Considerations........................................................................................................... 575

40. Errata.................................................................................................................................................. 576

40.1. Errata - ATtiny417/814/816/817............................................................................................... 576

41. Data Sheet Revision History............................................................................................................... 577

41.1. Rev. A - 12/2020.......................................................................................................................57741.2. Appendix - Obsolete Revision History......................................................................................583

ATtiny417/814/816/817


The Microchip Website...............................................................................................................................593

Product Change Notification Service..........................................................................................................593

Customer Support...................................................................................................................................... 593

Product Identification System.....................................................................................................................594

Microchip Devices Code Protection Feature.............................................................................................. 594

Legal Notice............................................................................................................................................... 594

Trademarks................................................................................................................................................ 595

Quality Management System..................................................................................................................... 595

Worldwide Sales and Service.....................................................................................................................596

ATtiny417/814/816/817


1. Silicon Errata and Data Sheet Clarification DocumentMicrochip aims to provide its customers with the best documentation possible to ensure the successful use ofMicrochip products. Between data sheet updates, a Silicon errata and data sheet clarification document will containthe most recent information for the data sheet. The ATtiny417/814/816/817 Silicon Errata and Data SheetClarification (www.microchip.com/DS80000934) is available at the device product page on www.microchip.com.

ATtiny417/814/816/817Silicon Errata and Data Sheet Clarification ...


https://www.microchip.com/DS80000934https://www.microchip.com

2. tinyAVR® 1-series OverviewThe following figure shows the tinyAVR 1-series devices, laying out pin count variants and memory sizes:

• Vertical migration upwards is possible without code modification, as these devices are pin-compatible andprovide the same or more features. Downward migration may require code modification due to fewer availableinstances of some peripherals.

• Horizontal migration to the left reduces the pin count and, therefore, the available features

Figure 2-1. tinyAVR® 1-series Overview

8 Pins

20 24 14

8 KB

Flash

16 KB

32 KB

4 KB

2 KB

Devices described in this data sheet

Devices described in other data sheets

ATtiny3216 ATtiny3217

ATtiny1614 ATtiny1616 ATtiny1617

ATtiny412

ATtiny212


ATtiny214


Devices with different Flash memory sizes typically also have different SRAM and EEPROM.

2.1 Configuration Summary

2.1.1 Peripheral SummaryTable 2-1. Peripheral Summary

ATtin

y417

ATtin

y814

ATtin

y816

ATtin

y817

Pins 24 14 20 24

SRAM 256B 512B 512B 512B

Flash 4 KB 8 KB 8 KB 8 KB

EEPROM 128B 128B 128B 128B

Max. frequency (MHz) 20 20 20 20

16-bit Timer/Counter type A (TCA) 1 1 1 1

16-bit Timer/Counter type B (TCB) 1 1 1 1

12-bit Timer/Counter type D (TCD) 1 1 1 1

ATtiny417/814/816/817tinyAVR® 1-series Overview


...........continued

ATtin

y417

ATtin

y814

ATtin

y816

ATtin

y817

Real-Time Counter (RTC) 1 1 1 1

USART 1 1 1 1

SPI 1 1 1 1

TWI (I2C) 1 1 1 1

ADC 1 1 1 1

ADC channels 12 10 12 12

DAC 1 1 1 1

AC 1 1 1 1

AC inputs 2p/2n 1p/1n 2p/2n 2p/2n

Peripheral Touch Controller (PTC)(1) No 1 1 1

PTC number of self-capacitance channels - 6 6 6

PTC number of mutual capacitance channels - 9 9 9

Configurable Custom Logic 1 1 1 1

Window Watchdog 1 1 1 1

Event System channels 6 6 6 6

General purpose I/O 22 12 18 22

External interrupts 22 12 18 22

CRCSCAN 1 1 1 1

Note: 1. The PTC takes control over the ADC0 while the PTC is used.

ATtiny417/814/816/817tinyAVR® 1-series Overview


3. Block DiagramFigure 3-1. tinyAVR® 1-series Block Diagram

IN/OUT

DATABUS

Clock Generation

BUS Matrix

CPU

USART0

SPI0

CCL

AC[2:0]

ADC0 / PTC

TCA0

TCB[1:0]

AINP[3:0]AINN[1:0]

OUT

WO[5:0]

RXDTXDXCK

XDIR

MISOMOSISCK

SS

PORTS

System Management

SLPCTRL

RSTCTRL

CLKCTRL

EVENT

ROUTING

NETWORK

DATABUS

UPDICRC

SRAM

NVMCTRL

Flash

EEPROM

OSC20M

OSC32K

Detectors/References

POR

Bandgap

WDT

RTC

CPUINT

OCD

RST

EXTCLK

LUTn-IN[2:0]LUTn-OUT

WO CLKOUT

PA[7:0]PB[7:0]PC[5:0]

GPIOR

TWI0SDASCL

TCD0WO[A,B,C,D]

XOSC32K

TOSC2

TOSC1

To detectors

UPDI / RESET

EVSYS EVOUT[n:0]

DACOUT [2:0]

ADC1

VLMBOD

EXTCLK

AIN[11:0]X[13:0]Y[13:0]

VREFA

AIN[11:0]

analog peripherals

analog peripherals

Analog peripherals

Digital peripherals

analog peripheralsCore components

Clocks/generators

®

Note: The block diagram represents the largest device of the tinyAVR®1-series, both in terms of pin count and Flashsize. See sections 2.1 Configuration Summary and 5. I/O Multiplexing and Considerations for an overview of thefeatures of the specific devices in this data sheet.

ATtiny417/814/816/817Block Diagram


4. Pinout

4.1 14-Pin SOIC

1

2

3

4 11

12

13

14

PA3 (EXTCLK)

PA2

PA1

GND

Power

Power Supply

Ground

Functionality

Programming/Debug

Clock/Crystal

Analog Function

Digital Function OnlyPin on VDD Power Domain

5

6

7

10

9

8

VDD

PA4

PA5

PA6

PA7

(TOSC1) PB3

(TOSC2) PB2

PB0

PB1

PA0 (RESET/UPDI)

ATtiny417/814/816/817Pinout


4.2 20-Pin SOIC

1

2

3

4 17

18

19

20

PA3 (EXTCLK)

PA2

PA1

GND

Power

Power Supply

Ground

Functionality

Programming/Debug

Clock/Crystal

Analog Function


5

6

7

16

15

14

VDD

PA4

PA5

PA6

PA7

PB5

PB4

PC3

PC2

PA0 (RESET/UPDI)

8

9

10

(TOSC1) PB3

(TOSC2) PB2

PB1

13

12

11

PC0

PB0

PC1



4.3 20-Pin VQFN

1

2

3

4

56 7 8

20 19 18 17

9

13

14

1516

1011

12

Note: It is recommended tosolder the large center pad toground for mechanical stability

Power

Power Supply

Ground

Functionality

Programming/Debug

Clock/Crystal

Analog Function


PA1

PA0

(RES

ET/U

PDI)

PB0

PB1PB

4

PB5

PA7

PA6

PA5

PA4

VDD

GND

(EXTCLK) PA3

PA2

PB2 (TOSC2)

PB3 (TOSC1)

PC3

PC2

PC1

PC0



4.4 24-Pin VQFN

Note: It is recommended tosolder the large center pad toground for mechanical stability

Power

Power Supply

Ground

Functionality

Programming/Debug

Clock/Crystal

Analog Function


1

2

3

4

5PA4

VDD

GND

(EXTCLK) PA3

PA2

PA5 6

PB5

PB6

PB7

PA7

PA6

PB4

7 8 9 10 11 12

PB0

PB1

PB2 (TOSC2)

PB3 (TOSC1)

PC0

PC1

15

16

17

13

14

1824 23 22 21 20

PA1

PA0

(RES

ET/U

PDI)

PC5

PC4

PC3

19

PC2



5. I/O Multiplexing and Considerations

5.1 Multiplexed SignalsTable 5-1. PORT Function Multiplexing

VQFN

24-

Pin

VQFN

20-

Pin

SOIC

20-

Pin

SOIC

14-

Pin Pin Name (1,2) Other/Special ADC0 PTC(4) AC0 DAC0 USART0 SPI0 TWI0 TCA0 TCB0 TCD0 CCL

23 19 16 10 PA0 RESET/ UPDI AIN0 LUT0-IN0

24 20 17 11 PA1 AIN1 TxD(3) MOSI SDA(3) LUT0-IN1

1 1 18 12 PA2 EVOUT0 AIN2 RxD(3) MISO SCL(3) LUT0-IN2

2 2 19 13 PA3 EXTCLK AIN3 XCK(3) SCK WO3

3 3 20 14 GND

4 4 1 1 VDD5 5 2 2 PA4 AIN4 X0/Y0 XDIR(3) SS WO4 WOA LUT0-OUT

6 6 3 3 PA5 AIN5 X1/Y1 OUT WO5 WO WOB

7 7 4 4 PA6 AIN6 X2/Y2 AINN0 OUT

8 8 5 5 PA7 AIN7 X3/Y3 AINP0 LUT1-OUT

9 PB7

10 PB6

11 9 6 PB5 CLKOUT AIN8 AINP1 WO2(3)

12 10 7 PB4 AIN9 AINN1 WO1(3) LUT0-OUT(3)

13 11 8 6 PB3 TOSC1 RxD WO0(3)

14 12 9 7 PB2 TOSC2, EVOUT1 TxD WO2

15 13 10 8 PB1 AIN10 X4/Y4 XCK SDA WO1

16 14 11 9 PB0 AIN11 X5/Y5 XDIR SCL WO0

17 15 12 PC0 SCK(3) WO(3) WOC

18 16 13 PC1 MISO(3) WOD LUT1-OUT(3)

19 17 14 PC2 EVOUT2 MOSI(3)

20 18 15 PC3 SS(3) WO3(3) LUT1-IN0

21 PC4 WO4(3) LUT1-IN1

22 PC5 WO5(3) LUT1-IN2

Notes: 1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. The notation for

signals is PORTx_PINn. All pins can be used as event input.2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous

detection.3. Alternate pin positions. For selecting the alternate positions, refer to section 15. PORTMUX - Port Multiplexer.4. PTC is only available in devices with 8 KB Flash or more. Every PTC line can be configured as X- or Y-line.

ATtiny417/814/816/817I/O Multiplexing and Considerations


6. Memories

6.1 OverviewThe main memories are SRAM data memory, EEPROM data memory, and Flash program memory. Also, theperipheral registers are located in the I/O memory space.

Table 6-1. Physical Properties of Flash Memory

Property ATtiny417 ATtiny814 ATtiny816 ATtiny817

Size 4 KB 8 KB 8 KB 8 KB

Page size 64B 64B 64B 64B

Number of pages 64 128 128 128

Start address 0x8000 0x8000 0x8000 0x8000

Table 6-2. Physical Properties of SRAM

Property ATtiny417 ATtiny814 ATtiny816 ATtiny817

Size 256B 512B 512B 512B

Start address 0x3F00 0x3E00 0x3E00 0x3E00

Table 6-3. Physical Properties of EEPROM

Property

Size 128B

Page size 32B

Number of pages 4

Start address 0x1400

ATtiny417/814/816/817Memories


6.2 Memory MapFigure 6-1. Memory Map

(Reserved)

(Reserved)

NVM I/O Registers and Data

64 I/O Registers

960 Ext. I/O Registers

0x0000 – 0x003F

0x0040 – 0x0FFF

0x1400 - 0x1480EEPROM128B

Flash Code

0x1000 – 0x13FF

Internal SRAM256/512B

0x3F00 (for SRAM 256B)/0x3E00 (for SRAM 512B)

4/8 KB

0x8FFF (for Flash 4K)/0x9FFF (for Flash 8K)

0x8000

0x3FFF

Flash Code4/8 KB

0x0000

CPU Code space UPDI/CPU Data space

6.3 In-System Reprogrammable Flash Program MemoryThe ATtiny417/814/816/817 contains 4/8 KB on-chip in-system reprogrammable Flash memory for program storage.Since all AVR instructions are 16 or 32-bit wide, the Flash is organized with 16-bit data width. For write protection, theFlash program memory space can be divided into three sections (see the illustration below): Bootloader section,Application code section, and Application data section, with restricted access rights among them.



The Program Counter (PC) is 11/12-bit wide to address the whole program memory. The procedure for writing Flashmemory is described in detail in the documentation of the Nonvolatile Memory Controller (NVMCTRL) peripheral.

The entire Flash memory is mapped in the memory space and is accessible with normal LD/ST instructions as well asthe LPM instruction. For LD/ST instructions, the Flash is mapped from address 0x8000. For the LPM instruction, theFlash start address is 0x0000.

The ATtiny417/814/816/817 also has a CRC peripheral that is a host on the bus.

Figure 6-2. Flash and the Three SectionsFLASHSTART: 0x8000

BOOTEND>0: 0x8000+BOOTEND*256

BO OT

APPEND>0: 0x8000+APPEND*256

AP PL ICA TIO NCO DE

AP PLICA TIO NDA TA

FLASH

FLASHEND

6.4 SRAM Data MemoryThe 256/512 bytes SRAM is used for data storage and stack.

6.5 EEPROM Data MemoryThe ATtiny417/814/816/817 has 128 bytes of EEPROM data memory. See also section 6.2 Memory Map. TheEEPROM memory supports single-byte read and write. The EEPROM is controlled by the Nonvolatile MemoryController (NVMCTRL).

6.6 User RowIn addition to the EEPROM, the ATtiny417/814/816/817 has one extra page of EEPROM memory that can be usedfor firmware settings; the User Row (USERROW). This memory supports single-byte read and write as the normalEEPROM. The CPU can write and read this memory as normal EEPROM, and the UPDI can write and read it as anormal EEPROM memory if the part is unlocked. The User Row can be written by the UPDI when the part is locked.USERROW is not affected by a chip erase.

6.7 Signature BytesAll tinyAVR® microcontrollers have a 3-byte signature code that identifies the device. The three bytes reside in aseparate address space. For the device, the signature bytes are given in the following table.

Note: When the device is locked, only the System Information Block (SIB) can be accessed.



Table 6-4. Device ID

Device Name Signature Bytes Address

0x00 0x01 0x02

ATtiny417 0x1E 0x92 0x20




6.8 I/O MemoryAll ATtiny417/814/816/817 I/Os and peripherals are located in the I/O memory space. The I/O address range from0x00 to 0x3F can be accessed in a single cycle using IN and OUT instructions. The extended I/O memory space from0x0040 to 0x0FFF can be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the32 general purpose working registers and the I/O memory space.

I/O registers within the address range 0x00-0x1F are directly bit-accessible using the SBI and CBI instructions. Inthese registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to theInstruction Set section for more details.

For compatibility with future devices, reserved bits must be written to ‘0’ if accessed. Reserved I/O memoryaddresses must never be written.

Some of the interrupt flags are cleared by writing a ‘1’ to them. On ATtiny417/814/816/817 devices, the CBI and SBIinstructions will only operate on the specified bit and can be used on registers containing such interrupt flags. TheCBI and SBI instructions work with registers 0x00-0x1F only.

General Purpose I/O RegistersThe ATtiny417/814/816/817 devices provide four general purpose I/O registers. These registers can be used forstoring any information, and they are particularly useful for storing global variables and interrupt flags. Generalpurpose I/O registers, which reside in the address range 0x1C-0x1F, are directly bit-accessible using the SBI, CBI,SBIS, and SBIC instructions.



6.8.1 Register Summary

Offset Name Bit Pos. 7 6 5 4 3 2 1 0

0x00 GPIOR0 7:0 GPIOR[7:0]0x01 GPIOR1 7:0 GPIOR[7:0]0x02 GPIOR2 7:0 GPIOR[7:0]0x03 GPIOR3 7:0 GPIOR[7:0]

6.8.2 Register Description



6.8.2.1 General Purpose I/O Register n

Name: GPIORnOffset: 0x00 + n*0x01 [n=0..3]Reset: 0x00Property: -

These are general purpose registers that can be used to store data, such as global variables and flags, in the bit-accessible I/O memory space.

Bit 7 6 5 4 3 2 1 0 GPIOR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bits 7:0 – GPIOR[7:0] General Purpose I/O Register Byte

6.9 Memory Section Access from CPU and UPDI on Locked DeviceThe device can be locked so that the memories cannot be read using the UPDI. The locking protects both the Flash(all Boot, Application Code, and Application Data sections), SRAM, and the EEPROM, including the FUSE data. Thisprevents successful reading of application data or code using the debugger interface. Regular memory access fromwithin the application is still enabled.

The device is locked by writing a non-valid key to the LOCKBIT bit field in FUSE.LOCKBIT.

Table 6-5. Memory Access Unlocked (FUSE.LOCKBIT Valid Key)(1)

Memory Section CPU Access UPDI Access

Read Write Read Write

SRAM Yes Yes Yes Yes

Registers Yes Yes Yes Yes

Flash Yes Yes Yes Yes

EEPROM Yes Yes Yes Yes

USERROW Yes Yes Yes Yes

SIGROW Yes No Yes No

Other fuses Yes No Yes Yes

Table 6-6. Memory Access Locked (FUSE.LOCKBIT Invalid Key)(1)

Memory Section CPU Access UPDI Access

Read Write Read Write

SRAM Yes Yes No No

Registers Yes Yes No No

Flash Yes Yes No No

EEPROM Yes Yes No No

USERROW Yes Yes No Yes(2)

SIGROW Yes No No No

Other fuses Yes No No No



Notes: 1. Read operations marked No in the tables may appear to be successful, but the data are not valid. Hence, any

attempt of code validation through the UPDI will fail on these memory sections.2. In the Locked mode, the USERROW can be written using the Fuse Write command, but the current

USERROW values cannot be read out.

Important: The only way to unlock a device is through a CHIPERASE. No application data are retained.

6.10 Configuration and User Fuses (FUSE)Fuses are part of the nonvolatile memory and hold the device configuration. The fuses are available from the devicepower-up. The fuses can be read by the CPU or the UPDI but can only be programmed or cleared by the UPDI. Theconfiguration values stored in the fuses are written to their respective target registers at the end of the start-upsequence.

The fuses for peripheral configuration (FUSE) are pre-programmed but can be altered by the user. Altered values inthe configuration fuse will be effective only after a Reset.Note: When writing the fuses, all reserved bits must be written to ‘1’.



6.10.1 Signature Row Summary


0x00 DEVICEID0 7:0 DEVICEID[7:0]0x01 DEVICEID1 7:0 DEVICEID[7:0]0x02 DEVICEID2 7:0 DEVICEID[7:0]0x03 SERNUM0 7:0 SERNUM[7:0]0x04 SERNUM1 7:0 SERNUM[7:0]0x05 SERNUM2 7:0 SERNUM[7:0]0x06 SERNUM3 7:0 SERNUM[7:0]0x07 SERNUM4 7:0 SERNUM[7:0]0x08 SERNUM5 7:0 SERNUM[7:0]0x09 SERNUM6 7:0 SERNUM[7:0]0x0A SERNUM7 7:0 SERNUM[7:0]0x0B SERNUM8 7:0 SERNUM[7:0]0x0C SERNUM9 7:0 SERNUM[7:0]0x0D

...0x1F

Reserved

0x20 TEMPSENSE0 7:0 TEMPSENSE[7:0]0x21 TEMPSENSE1 7:0 TEMPSENSE[7:0]0x22 OSC16ERR3V 7:0 OSC16ERR3V[7:0]0x23 OSC16ERR5V 7:0 OSC16ERR5V[7:0]0x24 OSC20ERR3V 7:0 OSC20ERR3V[7:0]0x25 OSC20ERR5V 7:0 OSC20ERR5V[7:0]

6.10.2 Signature Row Description



6.10.2.1 Device ID n

Name: DEVICEIDnOffset: 0x00 + n*0x01 [n=0..2]Default: [Device ID]Property: -

Each device has a device ID identifying this device and its properties such as memory sizes, pin count, and dierevision. This ID can be used to identify a device and hence, the available features by software. The Device IDconsists of three bytes: SIGROW.DEVICEID[2:0].

Bit 7 6 5 4 3 2 1 0 DEVICEID[7:0]

Access R R R R R R R R Default x x x x x x x x

Bits 7:0 – DEVICEID[7:0] Byte n of the Device ID



6.10.2.2 Serial Number Byte n

Name: SERNUMnOffset: 0x03 + n*0x01 [n=0..9]Default: [device serial number]Property: -

Each device has an individual serial number, representing a unique ID. This ID can be used to identify a specificdevice in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].

Bit 7 6 5 4 3 2 1 0 SERNUM[7:0]


Bits 7:0 – SERNUM[7:0] Serial Number Byte n



6.10.2.3 Temperature Sensor Calibration n

Name: TEMPSENSEnOffset: 0x20 + n*0x01 [n=0..1]Default: [Temperature sensor calibration value]Property: -

The Temperature Sensor Calibration registers contain correction factors for temperature measurements from the on-chip sensor. The ADC.SIGROW.TEMPSENSE0 is a correction factor for the gain/slope (unsigned), andSIGROW.TEMPSENSE1 is a correction factor for the offset (signed).

Bit 7 6 5 4 3 2 1 0 TEMPSENSE[7:0]


Bits 7:0 – TEMPSENSE[7:0] Temperature Sensor Calibration Byte nRefer to the ADC section for a description of how to use this register.



6.10.2.4 OSC16 Error at 3V

Name: OSC16ERR3VOffset: 0x22Default: [Oscillator frequency error value]Property: -

Bit 7 6 5 4 3 2 1 0 OSC16ERR3V[7:0]


Bits 7:0 – OSC16ERR3V[7:0] OSC16 Error at 3VThese registers contain the signed oscillator frequency error value relative to the nominal oscillator frequency whenrunning at an internal 16 MHz at 3V, as measured during production.





Bit 7 6 5 4 3 2 1 0 OSC16ERR5V[7:0]







Bit 7 6 5 4 3 2 1 0 OSC20ERR3V[7:0]







Bit 7 6 5 4 3 2 1 0 OSC20ERR5V[7:0]





6.10.3 Fuse Summary - FUSE


0x00 WDTCFG 7:0 WINDOW[3:0] PERIOD[3:0]0x01 BODCFG 7:0 LVL[2:0] SAMPFREQ ACTIVE[1:0] SLEEP[1:0]0x02 OSCCFG 7:0 OSCLOCK FREQSEL[1:0]0x03 Reserved 0x04 TCD0CFG 7:0 CMPDEN CMPCEN CMPBEN CMPAEN CMPD CMPC CMPB CMPA0x05 SYSCFG0 7:0 CRCSRC[1:0] RSTPINCFG[1:0] EESAVE0x06 SYSCFG1 7:0 SUT[2:0]0x07 APPEND 7:0 APPEND[7:0]0x08 BOOTEND 7:0 BOOTEND[7:0]0x09 Reserved 0x0A LOCKBIT 7:0 LOCKBIT[7:0]

6.10.4 Fuse Description



6.10.4.1 Watchdog Configuration

Name: WDTCFGOffset: 0x00Default: 0x00Property: -

The default value given in this fuse description is the factory-programmed value and should not be mistaken for theReset value.

Bit 7 6 5 4 3 2 1 0 WINDOW[3:0] PERIOD[3:0]

Access R R R R R R R R Default 0 0 0 0 0 0 0 0

Bits 7:4 – WINDOW[3:0] Watchdog Window Time-Out PeriodThis value is loaded into the WINDOW bit field of the Watchdog Control A (WDT.CTRLA) register during Reset.

Bits 3:0 – PERIOD[3:0] Watchdog Time-Out PeriodThis value is loaded into the PERIOD bit field of the Watchdog Control A (WDT.CTRLA) register during Reset.



6.10.4.2 BOD Configuration

Name: BODCFGOffset: 0x01Default: 0x00Property: -


The bit values of this fuse register are written to the corresponding BOD configuration registers at the start-up.

Bit 7 6 5 4 3 2 1 0 LVL[2:0] SAMPFREQ ACTIVE[1:0] SLEEP[1:0]


Bits 7:5 – LVL[2:0] BOD LevelThis value is loaded into the LVL bit field of the BOD Control B (BOD.CTRLB) register during Reset.Value Name Description0x0 BODLEVEL0 1.8V0x2 BODLEVEL2 2.6V0x7 BODLEVEL7 4.2V

Notes: • The values in the description are typical• Refer to the BOD and POR Characteristics in Electrical Characteristics for maximum and minimum values

Bit 4 – SAMPFREQ BOD Sample FrequencyThis value is loaded into the SAMPFREQ bit of the BOD Control A (BOD.CTRLA) register during Reset.Value Description0x0 Sample frequency is 1 kHz0x1 Sample frequency is 125 Hz

Bits 3:2 – ACTIVE[1:0] BOD Operation Mode in Active and IdleThis value is loaded into the ACTIVE bit field of the BOD Control A (BOD.CTRLA) register during Reset.Value Description0x0 Disabled0x1 Enabled0x2 Sampled0x3 Enabled with wake-up halted until BOD is ready

Bits 1:0 – SLEEP[1:0] BOD Operation Mode in SleepThis value is loaded into the SLEEP bit field of the BOD Control A (BOD.CTRLA) register during Reset.Value Description0x0 Disabled0x1 Enabled0x2 Sampled0x3 Reserved



6.10.4.3 Oscillator Configuration

Name: OSCCFGOffset: 0x02Default: 0x02Property: -


Bit 7 6 5 4 3 2 1 0 OSCLOCK FREQSEL[1:0]

Access R R R Default 0 1 0

Bit 7 – OSCLOCK Oscillator LockThis Fuse bit is loaded to LOCK in CLKCTRL.OSC20MCALIBB during Reset.Value Description0 Calibration registers of the OSC20M oscillator are accessible1 Calibration registers of the OSC20M oscillator are locked

Bits 1:0 – FREQSEL[1:0] Frequency SelectThis bit field selects the operation frequency of the 16/20 MHz internal oscillator (OSC20M) and determines therespective factory calibration values to be written to CAL20M in CLKCTRL.OSC20MCALIBA and TEMPCAL20M inCLKCTRL.OSC20MCALIBB.Value Description0x1 Run at 16 MHz with corresponding factory calibration0x2 Run at 20 MHz with corresponding factory calibrationOther Reserved



6.10.4.4 Timer Counter Type D Configuration

Name: TCD0CFGOffset: 0x04Default: 0x00Property: -


The bit values of this fuse register are written to the corresponding bits in the TCD.FAULTCTRL register of TCD0 atstart-up.

Bit 7 6 5 4 3 2 1 0 CMPDEN CMPCEN CMPBEN CMPAEN CMPD CMPC CMPB CMPA


Bits 4, 5, 6, 7 – CMPEN Compare x EnableValue Description0 Compare x output on Pin is disabled1 Compare x output on Pin is enabled

Bits 0, 1, 2, 3 – CMP Compare xThis bit selects the default state of Compare x after Reset, or when entering debug if FAULTDET is '1'.Value Description0 Compare x default state is ‘0’1 Compare x default state is ‘1’



6.10.4.5 System Configuration 0

Name: SYSCFG0Offset: 0x05Default: 0xF6Property: -


Bit 7 6 5 4 3 2 1 0 CRCSRC[1:0] RSTPINCFG[1:0] EESAVE

Access R R R R R Default 1 1 0 1 0

Bits 7:6 – CRCSRC[1:0] CRC SourceThis bit field controls which section of the Flash will be checked by the CRCSCAN peripheral during Resetinitialization.Value Name Description0x0 FLASH CRC of full Flash (boot, application code and application data)0x1 BOOT CRC of the boot section0x2 BOOTAPP CRC of application code and boot sections0x3 NOCRC No CRC

Bits 3:2 – RSTPINCFG[1:0] Reset Pin ConfigurationThis bit field selects the Reset/UPDI pin configuration.Value Description0x0 GPIO0x1 UPDI0x2 RESETOther Reserved

Note: When configuring the RESET pin as GPIO, there is a potential conflict between the GPIO actively driving theoutput, and a high-voltage UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.

Bit 0 – EESAVE EEPROM Save During Chip EraseNote: If the device is locked, the EEPROM is always erased by a chip erase, regardless of this bit.

Value Description0 EEPROM erased during chip erase1 EEPROM not erased under chip erase



6.10.4.6 System Configuration 1

Name: SYSCFG1Offset: 0x06Default: 0x07Property: -


Bit 7 6 5 4 3 2 1 0 SUT[2:0]

Access R R R Default 1 1 1

Bits 2:0 – SUT[2:0] Start-Up Time SettingThis bit field selects the start-up time between power-on and code execution.Value Description0x0 0 ms0x1 1 ms0x2 2 ms0x3 4 ms0x4 8 ms0x5 16 ms0x6 32 ms0x7 64 ms



6.10.4.7 Application Code End

Name: APPENDOffset: 0x07Default: 0x00Property: -


Bit 7 6 5 4 3 2 1 0 APPEND[7:0]


Bits 7:0 – APPEND[7:0] Application Code Section EndThis bit field sets the end of the application code section in blocks of 256 bytes. The end of the application codesection will be set as (BOOT size) + (application code size). The remaining Flash will be application data. A value of0x00 defines the Flash from BOOTEND*256 to the end of Flash as the application code. When both FUSE.APPENDand FUSE.BOOTEND are 0x00, the entire Flash is the BOOT section.



6.10.4.8 Boot End

Name: BOOTENDOffset: 0x08Default: 0x00Property: -


Bit 7 6 5 4 3 2 1 0 BOOTEND[7:0]


Bits 7:0 – BOOTEND[7:0] Boot Section EndThis bit field sets the end of the boot section in blocks of 256 bytes. A value of 0x00 defines the whole Flash as theBOOT section. When both FUSE.APPEND and FUSE.BOOTEND are 0x00, the entire Flash is the BOOT section.



6.10.4.9 Lockbits

Name: LOCKBITOffset: 0x0ADefault: 0xC5Property: -


Bit 7 6 5 4 3 2 1 0 LOCKBIT[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 0 0 0 1 0 1

Bits 7:0 – LOCKBIT[7:0] LockbitsWhen the part is locked, UPDI cannot access the system bus, so it cannot read out anything but the SystemInformation Block (SIB).Value Description0xC5 Valid key - memory access is unlockedother Invalid key - memory access is locked



7. Peripherals and Architecture

7.1 Peripheral Address MapThe address map shows the base address for each peripheral. For a complete register description and summary foreach peripheral, refer to the respective sections.

Table 7-1. Peripheral Address Map

Base Address Name Description

0x0000 VPORTA Virtual Port A

0x0004 VPORTB Virtual Port B

0x0008 VPORTC Virtual Port C(1)

0x001C GPIO General Purpose I/O registers

0x0030 CPU CPU

0x0040 RSTCTRL Reset Controller

0x0050 SLPCTRL Sleep Controller

0x0060 CLKCTRL Clock Controller

0x0080 BOD Brown-out Detector

0x00A0 VREF Voltage Reference

0x0100 WDT Watchdog Timer

0x0110 CPUINT Interrupt Controller

0x0120 CRCSCAN Cyclic Redundancy Check Memory Scan

0x0140 RTC Real-Time Counter

0x0180 EVSYS Event System

0x01C0 CCL Configurable Custom Logic

0x0200 PORTMUX Port Multiplexer

0x0400 PORTA Port A Configuration

0x0420 PORTB Port B Configuration

0x0440 PORTC Port C Configuration(1)

0x0600 ADC0 Analog-to-Digital Converter 0/Peripheral Touch Controller

0x0670 AC0 Analog Comparator 0

0x0680 DAC0 Digital-to-Analog Converter 0

0x0800 USART0 Universal Synchronous Asynchronous Receiver Transmitter 0

0x0810 TWI0 Two-Wire Interface 0

0x0820 SPI0 Serial Peripheral Interface 0

0x0A00 TCA0 Timer/Counter Type A 0

0x0A40 TCB0 Timer/Counter Type B 0

0x0A80 TCD0 Timer/Counter Type D 0

ATtiny417/814/816/817Peripherals and Architecture


...........continuedBase Address Name Description

0x0F00 SYSCFG System Configuration

0x1000 NVMCTRL Nonvolatile Memory Controller

0x1100 SIGROW Signature Row

0x1280 FUSES Device-specific fuses

0x1300 USERROW User Row

Note: 1. The availability of this register depends on the device pin count. PORTC/VPORTC is available for devices with

20 pins or more.

7.2 Interrupt Vector MappingEach of the interrupt vectors is connected to one peripheral instance, as shown in the table below. A peripheral canhave one or more interrupt sources, see the Interrupt section in the Functional Description of the respectiveperipheral for more details on the available interrupt sources.

When the Interrupt condition occurs, an Interrupt flag (nameIF) is set in the Interrupt Flags register of the peripheral(peripheral.INTFLAGS).

An interrupt is enabled or disabled by writing to the corresponding Interrupt Enable (nameIE) bit in the peripheral'sInterrupt Control (peripheral.INTCTRL) register.

The naming of the registers may vary slightly in some peripherals.

An interrupt request is generated when the corresponding interrupt is enabled, and the interrupt flag is set. Theinterrupt request remains Active until the Interrupt flag is cleared. See the peripheral's INTFLAGS register for detailson how to clear interrupt flags.

Interrupts must be enabled globally for interrupt requests to be generated.Table 7-2. Interrupt Vector Mapping

VectorNumber

ProgramAddress(word)

PeripheralSource(name)

Description

0 0x00 RESET

1 0x01 CRCSCAN_NMI Non-Maskable Interrupt available for CRCSCAN

2 0x02 BOD_VLM Voltage Level Monitor interrupt

3 0x03 PORTA_PORT Port A interrupt

4 0x04 PORTB_PORT Port B interrupt

5 0x05 PORTC_PORT Port C interrupt(1)

6 0x06 RTC_CNT Real-Time Counter interrupt

7 0x07 RTC_PIT Periodic Interrupt Timer interrupt (in RTC peripheral)

8 0x08 TCA0_OVFTCA0_LUNF

Normal: Timer Counter Type A Overflow interrupt.Split: Timer Counter Type A Low Underflow interrupt.

9 0x09TCA0_HUNF

Normal: Unused.Split: Timer/Counter Type A High Underflow.

10 0x0A TCA0_CMP0TCA0_LCMP0

Normal: Timer/Counter Type A Compare Channel 0 interrupt.Split: Timer/Counter Type A Low byte Compare Channel 0 interrupt.



...........continuedVector

NumberProgramAddress(word)

PeripheralSource(name)

Description

11 0x0B TCA0_CMP1TCA0_LCMP1


12 0x0C TCA0_CMP2TCA0_LCMP2


13 0x0D TCB0_INT Timer Counter Type B Capture interrupt

14 0x0E TCD0_OVF Timer/Counter Type D Overflow interrupt

15 0x0F TCD0_TRIG Timer/Counter Type D Trigger interrupt

16 0x10 AC0_AC Analog Comparator interrupt

17 0x11 ADC0_RESRDY Analog-to-Digital Converter Result Ready interrupt

18 0x12 ADC0_WCOMP Analog-to-Digital Converter Window Compare interrupt

19 0x13 TWI0_TWIS Two-Wire Interface/I2C Client interrupt

20 0x14 TWI0_TWIM Two-Wire Interface/I2C Host interrupt

21 0x15 SPI0_INT Serial Peripheral Interface interrupt

22 0x16 USART0_RXC Universal Asynchronous Receiver-Transmitter Receive Complete interrupt

23 0x17 USART0_DRE Universal Asynchronous Receiver-Transmitter Data Ready interrupt

24 0x18 USART0_TXC Universal Asynchronous Receiver-Transmitter Transmit Complete interrupt

25 0x19 NVMCTRL_EE Nonvolatile Memory EEPROM Ready interrupt

Note: 1. The availability of the port pins depends on the device pin count. PORTC is available for devices with 20 pins

or more.

7.3 System Configuration (SYSCFG)The system configuration contains the revision ID of the part. The revision ID is readable from the CPU, making ituseful for implementing application changes between part revisions.



7.3.1 Register Summary


0x00 Reserved 0x01 REVID 7:0 REVID[7:0]

7.3.2 Register Description



7.3.2.1 Device Revision ID Register

Name: REVIDOffset: 0x01Reset: [revision ID]Property: -

This register is read-only and displays the device revision ID.

Bit 7 6 5 4 3 2 1 0 REVID[7:0]

Access R R R R R R R R Reset

Bits 7:0 – REVID[7:0] Revision IDThis bit field contains the device revision. 0x00 = A, 0x01 = B, and so on.



8. AVR® CPU

8.1 Features• 8-Bit, High-Performance AVR RISC CPU:

– 135 instructions– Hardware multiplier

• 32 8-Bit Registers Directly Connected to the ALU• Stack in RAM• Stack Pointer Accessible in I/O Memory Space• Direct Addressing of up to 64 KB of Unified Memory• Efficient Support for 8-, 16-, and 32-Bit Arithmetic• Configuration Change Protection for System-Critical Features• Native On-Chip Debugging (OCD) Support:

– Two hardware breakpoints– Change of flow, interrupt, and software breakpoints– Run-time read-out of Stack Pointer (SP) register, Program Counter (PC), and Status Register (SREG)– Register file read- and writable in Stopped mode

8.2 OverviewAll AVR devices use the AVR 8-bit CPU. The CPU is able to access memories, perform calculations, controlperipherals, and execute instructions in the program memory. Interrupt handling is described in a separate section.

8.3 ArchitectureTo maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses forprogram and data. The instructions in the program memory are executed with a single-level pipeline. While oneinstruction is being executed, the next instruction is prefetched from the program memory. This enables instructionsto be executed on every clock cycle.

Refer to the Instruction Set Summary section for a summary of all AVR instructions.

ATtiny417/814/816/817AVR® CPU


Figure 8-1. AVR® CPU Architecture

Register file

Flash Program Memory

Data Memory

ALU

R0R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25

R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)

Stack Pointer

Program Counter

Instruction Register

Instruction Decode

Status Register

ATtiny417/814/816/817AVR® CPU


8.4 Arithmetic Logic Unit (ALU)The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between working registers or between aconstant and a working register. Also, single-register operations can be executed.

The ALU operates in a direct connection with all the 32 general purpose working registers in the register file. Thearithmetic operations between working registers or between a working register and an immediate operand areexecuted in a single clock cycle, and the result is stored in the register file. After an arithmetic or logic operation, theStatus Register (CPU.SREG) is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bitarithmetic are supported, and the instruction set allows for an efficient implementation of the 32-bit arithmetic. Thehardware multiplier supports signed and unsigned multiplication and fractional formats.

8.4.1 Hardware MultiplierThe multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supportsdifferent variations of signed and unsigned integer and fractional numbers:

• Multiplication of signed/unsigned integers• Multiplication of signed/unsigned fractional numbers• Multiplication of a signed integer with an unsigned integer• Multiplication of a signed fractional number with an unsigned fractional number

A multiplication takes two CPU clock cycles.

8.5 Functional Description

8.5.1 Program FlowAfter being reset, the CPU will execute instructions from the lowest address in the Flash program memory, 0x0000.The Program Counter (PC) addresses the next instruction to be fetched.

The CPU supports instructions that can change the program flow conditionally or unconditionally and are capable ofaddressing the whole address space directly. Most AVR instructions use a 16-bit word format, and a limited numberuse a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack as a word pointer. The stack isallocated in the general data SRAM, and consequently, the stack size is only limited by the total SRAM size and theusage of the SRAM. After the Stack Pointer (SP) is reset, it points to the highest address in the internal SRAM. TheSP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas.The data SRAM can easily be accessed through the five different Addressing modes supported by the AVR CPU.

8.5.2 Instruction Execution TimingThe AVR CPU is clocked by the CPU clock, CLK_CPU. No internal clock division is applied. The figure below showsthe parallel instruction fetches and executions enabled by the Harvard architecture and the fast-access register fileconcept. This is the basic pipelining concept enabling up to 1 MIPS/MHz performance with high efficiency.

Figure 8-2. The Parallel Instruction Fetches and Executions

clk

1st Instruction Fetch1st Instruction Execute

2nd Instruction Fetch2nd

attiny417/814/816/817 · 2020. 12. 17. · • 1.1v • 1.5v • 2.5v • 4.3v – event system...

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