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1 Evgeny Bolotin – ICECS 2004 Automatic Hardware- Automatic Hardware- Efficient Efficient SoC Integration SoC Integration by QoS Network on Chip by QoS Network on Chip Electrical Engineering Department, Technion, Haifa, Israel Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny QNoC Research Group, Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel

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Electrical Engineering Department, Technion, Haifa, Israel. Automatic Hardware-Efficient SoC Integration by QoS Network on Chip. Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny. QNoC Research Group, Electrical Engineering Department - PowerPoint PPT Presentation

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Page 1: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

1 Evgeny Bolotin – ICECS 2004

Automatic Hardware-Efficient Automatic Hardware-Efficient SoC IntegrationSoC Integration

by QoS Network on Chipby QoS Network on Chip

Electrical Engineering Department, Technion, Haifa, Israel

Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny

QNoC Research Group, Electrical Engineering DepartmentTechnion – Israel Institute of Technology

Haifa, Israel

Page 2: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

2 Evgeny Bolotin – ICECS 2004

OutlineOutline

• Introduction: SoC Integration Challenge

• NoC Concept and QNoC Architecture

• SoC Automatic Integration by QNoC

• Summary

Page 3: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

3 Evgeny Bolotin – ICECS 2004

The Integration Challenge:The Integration Challenge: Growing Chip DensityGrowing Chip Density

1998Asic - 0.35 m

2004SoC – 90 nm

Memory, I/O

P

• Design complexity - High IP reuse

• Scalable and Efficient, High Performance Interconnect

• Integration Challenge

Page 4: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

4 Evgeny Bolotin – ICECS 2004

The Growing Gap: Computation vs. Communication

From ITRS, 2001

Page 5: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

5 Evgeny Bolotin – ICECS 2004

Traditional SoC Nightmare

Variety of dedicated interfaces Poor separation between computation and communication.

Design and Verification Complexity Unpredictable performance

Page 6: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

6 Evgeny Bolotin – ICECS 2004

Solution – Network on Chip (NoC)

• Scalability

• Concurrency, effective spatial reuse of resources

• Higher bandwidth

• Higher levels of abstraction

• Modularity – Productivity Improvement

Easier SoC Integration!

Page 7: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

7 Evgeny Bolotin – ICECS 2004

NoC vs. “Off-Chip” NetworksWhat is Different?

• Routers on Planar Grid Topology

• Short PTP Links between routers

• Unique VLSI Cost Sensitivity: Area-Routers and LinksPower

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Page 8: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

8 Evgeny Bolotin – ICECS 2004

NoC vs. “Off-Chip Networks”• No legacy protocols to be compliant with …

• No software simple and hardware efficient protocols

• Different operating env. (no dynamic changes and failures)

• Custom Network Design – You design what you need!

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Example1: Replace modules

Page 9: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

9 Evgeny Bolotin – ICECS 2004

NoC vs. “Off-Chip Networks”

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Example2: Adapt Links

Adapt Links

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Example3: Trim Unnecessary (ports, buffers, routers, links)

Page 10: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

10 Evgeny Bolotin – ICECS 2004

QNoC: QoS NoC

Define Service Levels (SLs):• Signaling

• Real-Time

• Read/Write (RD/WR)

• Block-Transfer

Different QoS for each SL

Page 11: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

11 Evgeny Bolotin – ICECS 2004

QNoC Architecture

• Mesh Topology

• Fixed shortest path routing (X-Y)Simple Router (no tables, simple logic)No deadlock scenarioPower efficient communication

• Wormhole RoutingFor reduced buffering

Page 12: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

12 Evgeny Bolotin – ICECS 2004

QNoC Wormhole Router

R outer

Module

Moduleor

another router Input Port Output Port

Page 13: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

13 Evgeny Bolotin – ICECS 2004

SoC development with QNoC

CharacterizeTraffic

SystemM odules

SystemSim ulations

System Architecture Definition System Integration and Verification

M ap traffic to gridQ NoC

Architecture

O ptim ize

Estim ate cost

Topology andP lacem ent

O ptim izedQ NoC

Hardware

SoCFabrication

Q NoCVerifia tion

M odel

SystemVerification

Page 14: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

14 Evgeny Bolotin – ICECS 2004

Integration Automation Tools

QNoC Placement and Topology Generation• Analyzes System Modules and Traffic

• Derives NoC Topology and Module Placement

• Minimizes Spatial Traffic Density

For Lower Area and Power

Page 15: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

15 Evgeny Bolotin – ICECS 2004

Integration Automation Tools

QNoC Customization• Maze-Router – for efficient packet routing

• Link Load Calculator – for capacity allocation

• QNoC Network Simulator – for QoS assuring

Placed Modules Relative Link Load Simulated QoS

Page 16: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

16 Evgeny Bolotin – ICECS 2004

Integration Automation Tools

Automatic Hardware Generation• Use calculated QNoC parameters and QNoC VHDL

templates library• Create Synthesizable VHDL description of QNoC• Including

• Module wrappers• Synchronization and SER/DES circuitry • Routing logic and tables

System Verification• QNoC verification models• For hardware and system simulations

Page 17: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

17 Evgeny Bolotin – ICECS 2004

Summary

• SoC Integration Challenge

• NoC Concept

• QNoC Architecture

• SoC Integration by QNoC

• Automatic Integration Tools

Page 18: Automatic Hardware-Efficient SoC Integration by QoS Network on Chip

18 Evgeny Bolotin – ICECS 2004

More Info:

www.ee.technion.ac.il/qnocwww.ee.technion.ac.il/qnoc


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