automation test initiative takeaways 04 mipi tech on tour taiwan... · user specified test patterns...

MIPI® Physical Layer Test SolutionsKeyur Diwan

Agenda

MIPI PHY Overview

Transmitter Test Overview

Probing Approaches

Receiver Test Overview

Intel MIPI Webinar MIPI Phy Solutions

Why MIPI?

Target applications– Mobile Applications– Camera– Display– Chip-to-chip Interconnect– Storage– Memory

Key features– Low Power– Low Pin Count– Minimize interference– Optional support for optical interconnects (M-PHY)

Key benefits– High Performance– High Scalability– High Bandwidth– Unprecedented Flexibility

Supported by industry– Shipping in millions of mobile products– JEDEC Universal Flash Storage– Mobile PCI Express– USB SSIC


Source: MIPI Alliance Specification Brief, Physical Layers: M-PHY, D-PHY, C-PHY

MIPI PHY Overview


Source: MIPI Alliance Specification Brief, Physical Layers: M-PHY, D-PHY, C-PHY

MIPI Measurement Challenges

Signal access

Complex signaling

Tests specified at RX or TX pin

Terminated and un-terminated modes

Differential and non-differential signaling

Low power (LP) and high-speed (HS) modes

Spec to CTS latency

Switchable termination networks

Receiver stress dependencies

New measurements required

Multi-lane testing

Different encoding schemes

Different clocking architecture

Built-in chip/SoC error detectors


TRANSMITTER TESTING


D-PHY Transmitter Measurements

Detection of LP-HS transition and timing measurements on that transition

Dynamic switching of terminations between LP and HS mode

Measurements on clock and data lanes verify voltage and timing parameters, separate LP from

HS bits

D-PHY v2.0 adds eye diagram and jitter measurements

Bus Turn Around test – user intervention to enable BTA mode and run tests


M-PHY Transmitter Measurements

Total Jitter, Jitter Separation and

Extrapolated Eye Analysis at 1E-10

Slew Rate Testing

Common Mode AC/DC

measurements

Lane to Lane Skew

Integration with Sig Test for Jitter

Analysis and Correlation (Future)

Power Spectral Density

(Informative Test)

PWM and SYS Mode tests

BER CONTOUR USING DPOJET


C-PHY Signaling

(1) lane consists of (3) separate VA, VB, and VC single-ended signals

Bit encoding by TX, 16-bits 7 symbols three-wire state levels

Differential RX sees three voltages as VAB, VBC, and VCA

Bits decoded by RX, three wire state levels 7 symbols 16-bits

Co-exist on same pins used for D-PHY

(high) ¾ V

(low) ¼ V

Strong 1

zerocrossing

Strong 0

(mid) ½ V

Weak 1

Weak 0

+x +z +y +z -z +x -zVA

VB

VC

VA - VB

VB - VC

VC - VA

UIINST UIINST UIINST UIINST UIINST


C-PHY Transmitter Measurements

1st triggered edge recovered from A, B, and C wires

Eye mask placement for optimal eye opening

Jitter and eye diagram rendering performed over entire record length

Rise/fall times specified for different transitions

Embed or de-embed insertion loss and crosstalk from s-parameter file

Acquire user specified # live waveforms, or process captured waveforms


Probing ApproachesD-PHY & C-PHY

Tektronix P7300A probes recommended for D-PHY and C-PHY

– New flex tips are in-expensive, easy to use, and robust

Termination fixtures provide switchable termination for LP and HS modes. Two versions available: 3-lane board from UNH/IOL, 4-lane board from Moving Pixel Company.


* – Actual loads show significant non-ideal effects at 1 GHz and above

‡- If Termination Voltage (Vterm )is set to the common-mode voltage, there will be no DC CM current.

Ideal 100Ω 2 SE Inputs 2 SE Inputs

w/DC block

Diff Input with

Cterm

Diff Input with

Vterm

Nominal Differential Input Impedance 100Ω 100Ω 100Ω 100Ω 100Ω

DC Differential Input Current (200mV

Vdiff)

2mA 2mA 0 2mA 2mA

DC Common-Mode Input Current

(100mV Vcm)

0 4mA 0 0 0‡

DC Common-Mode Input Impedance ∞ 25Ω ∞ ∞ 25Ω

AC Common-Mode Input Impedance Varies with

frequency*

Nominally

constant 25Ω

Nominally constant

25Ω at higher

frequencies

Nominally constant

25Ω at higher

frequencies

Nominally constant

25Ω

Probing ApproachesM-PHY


Embedding & De-embeddingS-parameter Application

MIPI parameters specified at the IC pin

– For TX measurements, de-embed to TX pin

– For RX measurements, embed for stress calibration to RX pin

S-parameter files used to represent insertion loss, cross-talk, and reflections

S-parameters converted to embed or de-embed filters

Measurements applied to filtered data


Before embed After embed

RECEIVER TESTING


D-PHY Receiver Measurements

Dynamic Skew, Rj, Sj, ISI

LP, HS, LP-HS modes

Control of protocol parameters, LP and HS amplitude

User specified test patterns to:

Isolate and stress physical layer interface

Encoded data following encoding rules

Long enough to yield statistically rich behavior

Generated and observe “in system”

Skew control

Rise/fall time for LP

LP voltage up to 1.3v

Common mode noise insertion


M-PHY Receiver Measurements

Stress calibration key to accurate RX measurements

Stressors include rise/fall time, ISI, Rj, Sj, CM voltage, and differential eye height.

Jitter tolerance and margin tests at multiple Sjvalues

Differential termination enable/disable timing tests

Test at nominal bit rates +/- 2000ppm

Stressed receiver testing– BERT

– AWG + external error detector

PWM & SYS Mode Testing with iBER


C-PHY Receiver Measurements

Generate tri-level monotonic test signals

Test patterns must match iBER requirements

16-bit words, 6-wire states, PRBS9/11/18

Stressors include rise/fall time, duty cycle distortion

(DCD), ISI, CM voltage, differential voltage /

differential eye height.

LP-HS sequence dependencies:

LP voltage

LP-HS transition time

# sync words

Pattern payload

Append HS waveforms for sequence-based looping

for compliance and margin testing


Electrical

D-PHY Test Solutions

Protocol Decode

DSI/CSI-2

Standalone

Decoder

Scope-based

Decoder

Tx

Rx

HS Gear

2.5G

D-PHY 1.2

D-PHY TX

Personality

Automated D-

PHY TX

software

Automated D-

PHY RX

software

D-PHY Siggen

D-PHY 2.0

4.5 G

DSI/CSI-2

Pattern

Generator


Tektronix Solution Roadmap Partner Solution

Electrical

M-PHY Test SolutionsProtocol Decode

LLI

HSI

DigiRFv4

SSIC

MPCIe

UniPro

DSI 2

CSI 3

UFS

Tx

Rx

HS G1

HS G2

HS G3

HS G4

M-PHY TX

personality

Automated M-

PHY TX

software

Automated M-

PHY RX

software

PWM

G0 – G7

SYS



C-PHY Test Solutions

Protocol Decode

DSI/CSI-2

Standalone

Decoder

Scope-based

Decoder

Tx

Rx

HS & HS-

LP

2.5 Gb/s

Automated C-

PHY RX

software

C-PHY SigGen

C-PHY 4-lane

Pattern

Generator

Electrical

C-PHY TX

Personality

Automated C-

PHY TX

software



MIPI Contributions

Contributor since 2008

Weekly participation at PHY work group meetings (D-PHY, M-PHY, C-PHY)

Contributions to CTS

Work closely with UNH-IOL (Andy Baldman) with Tektronix Equipment


automation test initiative takeaways 04 mipi tech on tour taiwan... · user specified test patterns...

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