av02-0813en_0
TRANSCRIPT
HSMP-389x Series, HSMP-489x Series Surface Mount RF PIN Switch Diodes
Data Sheet
Features• UniqueConfigurationsinSurfaceMountPackages
–AddFlexibility
–SaveBoardSpace
–ReduceCost
• Switching
–LowCapacitance
–LowResistanceatLowCurrent
• LowFailureinTime(FIT)Rate[1]
• MatchedDiodesforConsistentPerformance
• BetterThermalConductivityforHigherPowerDissipation
• Lead-freeNote:1. For more information see the Surface Mount PIN Reliability Data
Sheet.
Description/ApplicationsTheHSMP-389xseries isoptimizedforswitchingappli-cationswherelowresistanceatlowcurrentandlowca-pacitancearerequired.TheHSMP-489xseriesproductsfeature ultra low parasitic inductance. These productsare specifically designed for use at frequencies whicharemuchhigher than theupper limit forconventionalPINdiodes.
Pin Connections and Package Marking
Notes:1. Packagemarkingprovidesorientation,identification,anddate
code.2. See“ElectricalSpecifications”forappropriatepackagemarking.
GUx
1
2
3
6
5
4
2
Package Lead Code Identification, SOT-23/143 (Top View)
Package Lead Code Identification, SOT-323 (Top View)
Package Lead Code Identification, SOT-363 (Top View)
Absolute Maximum Ratings[1] TC = +25°C
Symbol Parameter Unit SOT-23/143 SOT-323/363
If ForwardCurrent(1µsPulse) Amp 1 1
PIV PeakInverseVoltage V 100 100
Tj JunctionTemperature °C 150 150
Tstg StorageTemperature °C -65to150 -65to150
θjc ThermalResistance[2] °C/W 500 150
ESD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge.
Notes:1. Operationinexcessofanyoneoftheseconditionsmayresultinpermanentdamagetothedevice.2. TC=+25°C,whereTCisdefinedtobethetemperatureatthepackagepinswherecontactismadetothecircuitboard.
SERIES–SHUNT PAIR
LOWINDUCTANCE
SINGLE
T
UNCONNECTEDTRIO
L1 2 3
6 5 4
1 2 3
6 5 4
1 2 3
6 5 4
UHIGH
FREQUENCYSERIES
V1 2 3
6 5 4
DUAL SWITCHMODEL
R1 2 3
6 5 4
COMMONCATHODE
F
COMMONANODE
E
SERIES
C
SINGLE
B
DUAL ANODE
489B
COMMONCATHODE
#4
COMMONANODE
#3
SERIES
#2
SINGLE
#0
UNCONNECTEDPAIR
#5
DUAL ANODE
4890
RINGQUAD
#71
3
2
4
UNDER DEVELOPMENT
3
Electrical Specifications, TC = 25°C, each diode
Package Minimum Maximum Maximum Part Number Marking Lead Breakdown Series Resistance Total Capacitance HSMP- Code Code Configuration Voltage VBR (V) RS (ý) CT (pF) 3890 G0[1] 0 Single 100 2.5 0.30 3892 G2[1] 2 Series 3893 G3[1] 3 CommonAnode 3894 G4[1] 4 CommonCathode 3895 G5[1] 5 UnconnectedPair 389B G0[2] B Single 389C G2[2] C Series 389E G3[2] E CommonAnode 389F G4[2] F CommonCathode 389L GL[2] L UnconnectedTrio 389R S[2] R DualSwitchMode 389T Z[2] T LowInductanceSingle 389U GU[2] U Series-ShuntPair 389V GV[2] V HighFrequencySeriesPair
TestConditions VR=VBR IF=5mA VR=5V Measure f=100MHz f=1MHz IR10µA
Notes:1. Packagemarkingcodeiswhite.2. Packageislasermarked.
High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes
Minimum Maximum Typical Maximum Typical Part Package Breakdown Series Total Total Total Number Marking Voltage Resistance Capacitance Capacitance Inductance HSMP- Code[1] Configuration VBR (V) R S (ý) C T (pF) CT (pF) LT (nH)
489x GA DualAnode 100 2.5 0.33 0.375 1.0
TestConditions VR=VBR IF=5mA f=1MHz VR=5V f=500MHz– Measure VR=5 V f=1MHz 3GHz IR10µA
Note:1. SOT-23packagemarkingcodeiswhite;SOT-323islasermarked.
Typical Parameters at TC = 25°C
Part Number Series Resistance Carrier Lifetime Total Capacitance HSMP- R S (ý) τ (ns) C T (pF)
389x 3.8 200 0.20@5V
TestConditions IF=1mA IF=10mA f=100MHz IR=6mA
4
HSMP-389x Series Typical Performance, TC = 25°C, each diode
Typical Applications for Multiple Diode Products
Figure 6. HSMP-389L used in a SP3T Switch.
Figure 7. HSMP-389L Unconnected Trio used in a Dual Voltage, High Isolation Switch.
1
123
40
5 6
b1 b2 b3
23
11 1
RF in RF out
2
2
3
4 5 6
100
2+V–V
“ON”“OFF”
Figure 1. Total RF Resistance at 25 C vs. Forward Bias Current.
100
10
1
0.1
RF
RE
SIS
TA
NC
E (
OH
MS
)
IF – FORWARD BIAS CURRENT (mA)
0.01 0.1 1 10 100
120
115
110
105
100
95
90
851 10 30
IF – FORWARD BIAS CURRENT (mA)
Figure 3. 2nd Harmonic Input Intercept Point vs. Forward Bias Current.
INP
UT
INT
ER
CE
PT
PO
INT
(d
Bm
)
Diode Mounted as a Series Attenuator in a50 Ohm Microstrip and Tested at 123 MHz
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.200 4 8 12 16 20
VR – REVERSE VOLTAGE (V)
TO
TA
L C
AP
AC
ITA
NC
E (
pF
)
1 MHz
1 GHz
Figure 2. Capacitance vs. Reverse Voltage.
200
160
120
80
40
010 2015 25 30T
rr –
RE
VE
RS
E R
EC
OV
ER
Y T
IME
(n
S)
FORWARD CURRENT (mA)
Figure 4. Typical Reverse Recovery Time vs. Reverse Voltage.
VR = –2V
VR = –5V
VR = –10V
100
10
1
0.1
0.010 0.2 0.4 0.6 0.8 1.0 1.2
I F –
FO
RW
AR
D C
UR
RE
NT
(m
A)
VF – FORWARD VOLTAGE (V)
Figure 5. Forward Current vs. Forward Voltage.
125 C 25 C –50 C
5
Typical Applications for Multiple Diode Products(continued)
Figure 11. HSMP-389V Series/Shunt Pair used in a 1.8 GHz Transmit/Receive Switch.
Figure 10. HSMP-389U Series/Shunt Pair used in a 900 MHz Transmit/Receive Switch.
Figure 8. HSMP-389L Unconnected Trio used in a Positive Voltage, High Isolation Switch.
Figure 9. HSMP-389T used in a Low Inductance Shunt Mounted Switch.
RF in RF out
1+V
0
20
+V“ON”“OFF”
456
1
1 1
2
2
3
RF in
RF out
456
1 2 3
λ4
RcvrXmtr
Bias Ant
PA
bias
HSMP-389ULNA
λ4
Rcvr
Bias
Xmtr
HSMP-389V
Antenna
λ4
λ4
RcvrXmtr
Bias Ant
C C
6
Typical Applications for Multiple Diode Products(continued)
RF COMMON
RF COMMON
RF 1
BIAS 1 BIAS BIAS
RF 2
BIAS 2
Figure 12. Simple SPDT Switch, Using Only Positive Current.
RF COMMON
RF 1 RF 2
BIAS
Figure 14. Switch Using Both Positive and Negative Bias Current. Figure 15. Very High Isolation SPDT Switch, Dual Bias.
Figure 13. High Isolation SPDT Switch, Dual Bias.
RF 2RF 1
RF COMMON
RF 2RF 1
BIAS
7
Equivalent Circuit Model
HSMP-389x Chip*
Typical Applications for HSMP-489x Low Inductance Series
Microstrip Series Connection for HSMP-489x Series
In order to take full advantage of the low inductanceoftheHSMP-489xserieswhenusingtheminseriesap-plications,bothlead1andlead2shouldbeconnectedtogether,asshowninFigure17.
Co-Planar Waveguide Shunt Connection for HSMP-489x Series
Co-Planar waveguide, with ground on the top side ofthe printed circuit board, is shown in Figure 20. Sinceit eliminates the need for via holes to ground, it offerslowershuntparasitic inductanceandhighermaximumattenuationwhencomparedtoamicrostripcircuit.
A SPICE model is not available for PIN diodes as SPICEdoesnotprovideforakeyPINdiodecharacteristic,car-rierlifetime.
1 2
3
Figure 16. Internal Connections.
HSMP-489x
Figure 17. Circuit Layout.
50 OHM MICROSTRIP LINES
PAD CONNECTED TOGROUND BY TWO
VIA HOLES
Figure 18. Circuit Layout.
0.3 nH
0.3 nH
0.3 pF
1.5 nH 1.5 nH
Figure 19. Equivalent Circuit.
Figure 20. Circuit Layout.
Co-Planar Waveguide Groundplane
Center Conductor
Groundplane
0.12 pF** Measured at -20 V
0.5 Ω
RjRs
Cj
Rj = 20 Ω
I0.9
RT = 0.5 + Rj
CT = CP + Cj
I = Forward Bias Current in mA
* See AN1124 for package models
Figure 21. Equivalent Circuit.
0.3 pF
0.75 nH
Figure 16. Internal Connections.
Figure 17. Circuit Layout.
Microstrip Shunt Connections for HSMP-489x Series
InFigure18,thecenterconductorofthemicrostriplineisinterruptedandleads1and2oftheHSMP-489xdiodeare placed across the resulting gap.This forces the 1.5nHleadinductanceofleads1and2toappearaspartofalowpassfilter,reducingtheshuntparasiticinductanceandincreasingthemaximumavailableattenuation.The0.3nHofshuntinductanceexternaltothediodeiscre-atedbytheviaholes,andisagoodestimatefor0.032"thickmaterial.
Figure 18. Circuit Layout.
Figure 19. Equivalent Circuit.
Figure 20. Circuit Layout.
Figure 21. Equivalent Circuit.
8
Assembly Information0.026
0.075
0.016
0.035
Figure 22. PCB Pad Layout, SOT-363. (dimensions in inches).
0.026
0.035
0.07
0.016
Figure 23. PCB Pad Layout, SOT-323. (dimensions in inches).
0.0370.95
0.0370.95
0.0792.0
0.0310.8
DIMENSIONS IN inches
mm
0.0350.9
SOT-23 FootprintFigure 24. PCB Pad Layout, SOT-23.
DIMENSIONS IN inches
mm
0.0751.9 0.071
1.8
0.1122.85
0.0792
0.0330.85
0.0411.05
0.1082.75
0.0330.85
0.0471.2
0.0310.8
0.0330.85
Figure 25. PCB Pad Layout, SOT-143.
9
Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C)
Reflow Parameter Lead-Free AssemblyAverageramp-uprate(LiquidusTemperature(TS(max)toPeak) 3°C/secondmax
Preheat TemperatureMin(TS(min)) 150°C
TemperatureMax(TS(max)) 200°C
Time(mintomax)(tS) 60-180seconds
Ts(max)toTLRamp-upRate 3°C/secondmax
Timemaintainedabove: Temperature(TL) 217°C
Time(tL) 60-150seconds
PeakTemperature(TP) 260+0/-5°C
Timewithin5°CofactualPeaktemperature(tP) 20-40seconds
Ramp-downRate 6°C/secondmax
Time25°CtoPeakTemperature 8minutesmax
Note1:Alltemperaturesrefertotopsideofthepackage,measuredonthepackagebodysurface
25
Time
Tem
pera
ture
Tp
T L
tp
tL
t 25° C to Peak
Ramp-up
ts
Ts min
Ramp-downPreheat
Critical ZoneT L to Tp
Ts max
Figure 26. Surface Mount Assembly Profile.
SMT Assembly
Reliable assembly of surface mount components is acomplex process that involves many material, process,and equipment factors, including: method of heating(e.g., IRorvaporphasereflow,wavesoldering,etc.)cir-cuit board material, conductor thickness and pattern,type of solder alloy, and the thermal conductivity andthermal mass of components. Components with a lowmass,suchastheSOTpackage,willreachsolderreflowtemperaturesfasterthanthosewithagreatermass.
AvagoTechnologies’diodeshavebeenqualifiedtothetime-temperatureprofileshowninFigure26.Thisprofileis representativeofan IR reflowtypeofsurfacemountassemblyprocess.
After ramping up from room temperature, the circuitboard with components attached to it (held in placewithsolderpaste)passesthroughoneormorepreheat
zones. The preheat zones increase the temperature ofthe board and components to prevent thermal shockand begin evaporating solvents from the solder paste.The reflow zone briefly elevates the temperature suffi-cientlytoproduceareflowofthesolder.
Theratesofchangeoftemperaturefortheramp-upandcool-down zones are chosen to be low enough to notcausedeformationof theboardordamagetocompo-nentsduetothermalshock.Themaximumtemperatureinthereflowzone(TMAX)shouldnotexceed260°C.
Theseparametersaretypicalforasurfacemountassem-blyprocessforAvagoTechnologiesdiodes.Asageneralguideline,thecircuitboardandcomponentsshouldbeexposedonlytotheminimumtemperaturesandtimesnecessarytoachieveauniformreflowofsolder.
10
e
B
e2
e1
E1
C
E XXX
L
D
A
A1
Notes:XXX-package markingDrawings are not to scale
DIMENSIONS (mm)
MIN.0.79
0.0000.300.082.731.150.891.780.452.100.45
MAX.1.20
0.1000.540.203.131.501.022.040.602.700.69
SYMBOLA
A1BCD
E1e
e1e2EL
e B
e2
B1
e1
E1
C
E XXX
L
D
A
A1
Notes:XXX-package markingDrawings are not to scale
DIMENSIONS (mm)
MIN.0.79
0.0130.360.76
0.0862.801.200.891.780.452.100.45
MAX.1.0970.100.540.92
0.1523.061.401.022.040.602.650.69
SYMBOLA
A1B
B1CD
E1e
e1e2EL
e
B
e1
E1
C
E XXX
L
D
A
A1
Notes:XXX-package markingDrawings are not to scale
DIMENSIONS (mm)
MIN.0.800.000.150.081.801.10
1.800.26
MAX.1.000.100.400.252.251.40
2.400.46
SYMBOLA
A1BCD
E1e
e1EL
1.30 typical0.65 typical
EHE
D
e
A1
b
AA2
DIMENSIONS (mm)
MIN.1.151.801.800.800.800.00
0.150.080.10
MAX.1.352.252.401.101.000.10
0.300.250.46
SYMBOLED
HEA
A2A1ebcL
0.650 BCS
L
c
Package Dimensions
Outline 23 (SOT-23)
Outline 143 (SOT-143) Outline SOT-363 (SC-70 6 Lead)
Outline SOT-323 (SC-70 3 Lead)
11
USERFEED DIRECTION
COVER TAPE
CARRIERTAPE
REEL
Note: "AB" represents package marking code. "C" represents date code.
END VIEW
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
Note: "AB" represents package marking code. "C" represents date code.
END VIEW
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
END VIEW
8 mm
4 mm
TOP VIEW
Note: "AB" represents package marking code. "C" represents date code.
ABC ABC ABC ABC
Option Descriptions-BLKG=Bulk,100pcs.perantistaticbag-TR1G=TapeandReel,3000devicesper7"reel-TR2G=TapeandReel,10,000devicesper13"reel
TapeandReelingconformstoElectronicIndustriesRS-481,“TapingofSurfaceMountedComponentsforAutomatedPlacement.”
Device Orientation
For Outline SOT-143
For Outlines SOT-23, -323
For Outline SOT-363
Ordering InformationSpecifypartnumberfollowedbyoption.Forexample: HSMP-389x-xxx
BulkorTapeandReelOption PartNumber;x=LeadCode SurfaceMountPIN
Package CharacteristicsLeadMaterial Copper(SOT-323/363);Alloy42(SOT-23/143)LeadFinish Tin100%MaximumSolderingTemperature 260°Cfor5secondsMinimumLeadStrength 2poundspullTypicalPackageInductance 2nHTypicalPackageCapacitance 0.08pF(oppositeleads)
12
Tape Dimensions and Product Orientation
For Outline SOT-143
For Outline SOT-23
9 MAX
A0
P
P0
D P2
E
F
W
D1
Ko 8 MAX
B0
13.5 MAX
t1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTHWIDTHDEPTHPITCHBOTTOM HOLE DIAMETER
A0B0K0PD1
3.15 ± 0.102.77 ± 0.101.22 ± 0.104.00 ± 0.101.00 + 0.05
0.124 ± 0.0040.109 ± 0.0040.048 ± 0.0040.157 ± 0.0040.039 ± 0.002
CAVITY
DIAMETERPITCHPOSITION
DP0E
1.50 + 0.104.00 ± 0.101.75 ± 0.10
0.059 + 0.0040.157 ± 0.0040.069 ± 0.004
PERFORATION
WIDTHTHICKNESS
Wt1
8.00 + 0.30 – 0.100.229 ± 0.013
0.315 + 0.012 – 0.0040.009 0.0005
CARRIER TAPE
CAVITY TO PERFORATION(WIDTH DIRECTION)
CAVITY TO PERFORATION(LENGTH DIRECTION)
F
P2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCEBETWEENCENTERLINE
WF
E
P2P0
DP
D1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTHWIDTHDEPTHPITCHBOTTOM HOLE DIAMETER
A0B0K0PD1
3.19 ± 0.102.80 ± 0.101.31 ± 0.104.00 ± 0.101.00 + 0.25
0.126 ± 0.0040.110 ± 0.0040.052 ± 0.0040.157 ± 0.0040.039 + 0.010
CAVITY
DIAMETERPITCHPOSITION
DP0E
1.50 + 0.104.00 ± 0.101.75 ± 0.10
0.059 + 0.0040.157 ± 0.0040.069 ± 0.004
PERFORATION
WIDTHTHICKNESS
Wt1
8.00 + 0.30 – 0.100.254 ± 0.013
0.315+ 0.012 – 0.0040.0100 0.0005
CARRIER TAPE
CAVITY TO PERFORATION(WIDTH DIRECTION)
CAVITY TO PERFORATION(LENGTH DIRECTION)
F
P2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
A0
9° MAX 9° MAX
t1
B0
K0
Tape Dimensions and Product Orientation
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-0486ENAV02-0813EN - June 2, 2009
For Outlines SOT-323, -363P
P0
P2
FW
C
D1
D
E
A0
An
t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS)
An
B0
K0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTHWIDTHDEPTHPITCHBOTTOM HOLE DIAMETER
A0B0K0PD1
2.40 ± 0.102.40 ± 0.101.20 ± 0.104.00 ± 0.101.00 + 0.25
0.094 ± 0.0040.094 ± 0.0040.047 ± 0.0040.157 ± 0.0040.039 + 0.010
CAVITY
DIAMETERPITCHPOSITION
DP0E
1.55 ± 0.054.00 ± 0.101.75 ± 0.10
0.061 ± 0.0020.157 ± 0.0040.069 ± 0.004
PERFORATION
WIDTHTHICKNESS
Wt1
8.00 ± 0.300.254 ± 0.02
0.315 ± 0.0120.0100 ± 0.0008
CARRIER TAPE
CAVITY TO PERFORATION(WIDTH DIRECTION)
CAVITY TO PERFORATION(LENGTH DIRECTION)
F
P2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
FOR SOT-323 (SC70-3 LEAD) An 8°C MAX
FOR SOT-363 (SC70-6 LEAD) 10°C MAX
ANGLE
WIDTHTAPE THICKNESS
CTt
5.4 ± 0.100.062 ± 0.001
0.205 ± 0.0040.0025 ± 0.00004
COVER TAPE