Back-to-Back Connected Five-Level Diode-ClampedPWM Converters for Motor Drives

Hatti Natchpong, Yosuke Kondo, and Hirofumi Akagi, Fellow, IEEEDepartment of Electrical and Electronic Engineering

Tokyo Institute of Technology, JapanEmail: hatti.n.aa@m.titech.ac.jp, kondo.y.ac@m.titech.ac.jp, and akagi@ee.titech.ac.jp

Abstract—This paper addresses a medium-voltage adjustable-speed motor drive consisting of two five-level diode-clampedPWM converters connected back-to-back. It is followed bydesigning, constructing and testing a 200-V down-scaled modelto verify the validity and effectiveness of the medium-voltagemotor drive. This down-scaled model has four split dc capacitorsequipped with a voltage-balancing circuit using two bidirectionalbuck-boost choppers. The two five-level converters are based onsinusoidal PWM (SPWM) with a carrier frequency of 3 kHz. Themotor tested in this paper is a three-phase four-pole inductionmotor rated at 200 V, 5.5 kW and 60 Hz. Experimental waveformsshow that the four split dc-capacitor voltages are well balanced inany operating conditions, and that the total harmonic distortion(THD) values of the input line current and the output motorcurrent are 3.9% and 3.35%, respectively.

I. INTRODUCTION

Since the three-level neutral-point clamped (NPC), or diode-clamped, PWM inverter was invented in 1980 [1], it has beenpractically applied to steel mill drives, traction drives, STAT-COMs and UPFCs. Recently, attention has been paid to four-level and five-level diode-clamped PWM inverters intended forhigher-voltage and higher-power applications [2]. Significantdevelopments of power semiconductor technology has madethe so-called ”high-voltage IGBT” rated at 3.3/4.5/6.5 kV [3]available from the market.

The motivation of introducing the five-level inverter intoa medium-voltage motor drive is to eliminate heavy, costlytransformers from the motor drive, as well as to rely on lowercommon-mode voltage and lower dv/dt that lead to lowerstress on motor bearings and motor windings, and highervoltage capacity [4]-[6]. However, a five-level diode-clampedPWM inverter with a three-phase diode rectifier as the frontend suffers from voltage imbalance of four split dc capacitors.

This paper addresses a medium-voltage adjustable-speedmotor drive system based on two five-level diode-clampedPWM converters connected back-to-back, with focus onvoltage-balancing control of four split dc capacitors. A 200-V, 5.5-kW down-scaled motor drive system is designed, con-structed, and tested to verify the viability and effectiveness. Itconsists of a set of five-level diode-clamped PWM rectifier andinverter with the same carrier frequency as 3 kHz, a voltage-balancing circuit using two bidirectional buck-boost chopperswith the same carrier frequency as 3 kHz, and an inductionmotor rated at 200 V and 5.5 kW. Experimental waveformsobserved from the down-scaled system verify satisfactory sys-

tem performance including voltage-balancing performance inany operating conditions. Moreover, experimental results agreewell with theoretical results including dc currents flowing inthe bidirectional buck-boost choppers for achieving voltage-balancing control.

II. DESIGN CONCEPT OF THE 6.6-KV TRANSFORMERLESS

MOTOR DRIVE SYSTEM

A. Five-Level Diode-Clamped PWM Rectifier and Inverter

Fig. 1 shows the 6.6-kV 1-MW transformerless motor drivesystem, where the five-level rectifier is directly connected tothe 6.6-kV grid, and the five-level inverter to the 6.6-kV motorwithout transformer. Each switching device is either single4.5-kV IGBT or a string of three 1.7-kV IGBTs connectedin series. A single 4.5-kV diode can be used as a clampingdiode. When the rectifier and the inverter have the same carrierfrequency as 3 kHz, the actual switching frequency of eachIGBT ranges from 0 to 1.5 kHz. The weight of the 6.6-kV,1-MVA, 50-Hz transformer ranges from 3,000 to 4,000 kg,while that of the 6.6-kV, 1-MW rectifier or inverter rangesfrom 1,000 to 2,000 kg. Thus, it is reasonable to eliminate thetransformer from the 6.6-kV motor drives system in terms ofreducing cost, weight and physical size.

B. Review of Voltage-Balancing Control of The Four Split DCCapacitors

The four common dc capacitors connected in series betweenthe rectifier and the inverter has the following five node pointsin the dc link: the outer positive point P2, the inner positivepoint P1, the mid-point M, the inner negative point N1, andthe outer negative point N2, as shown in Fig. 1. Whenever themotor is operated either in powering mode or on regenerativemode, an amount of dc current would flows into, or out of, thetwo inner points P1 and N1. This causes voltage imbalance ofthe four capacitors unless special care were taken of voltagebalancing.

Existing solutions to voltage imbalance inherent in themotor drive system can be classified into the following twogroups; one is based on sophisticated switching control [7]-[9],and the other is based on additional hardware installation [10].The former is more preferable in cost than the second one.The authors of [7] have proposed a practical switching-anglecontrol method for staircase modulation or the so-call ”one-pulse PWM.” It appropriate adjusts all the switching angles of

1-4244-0844-X/07/$20.00 ©2007 IEEE. 1456

P2

P1

M

N1

N2

IM

6.6 kV

6 kV

-6 kV

6.6 kV

Voltage-balancingcircuitRectifier Inverter

Fig. 1. The 6.6-kV transformerless motor drive system based on the five-level diode-clamped PWM rectifier and inverter connected back-to-back.

both rectifier and inverter so as to balance the four capacitorvoltages, in addition to sinusoidal line current control, dc-linkvoltage regulation, and sinusoidal motor current control. Thelatter is superior to the first one in system performance andadaptability to existing triangle-carrier modulation and space-vector modulation without mutual interference between currentcontrol and voltage-balancing control.

From these considerations, the authors have decided to con-nect positive and negative bidirectional buck-boost choppersto the positive and negative points. Hence, each of the rectifierand the inverter devotes itself to concentrating on each high-priority task pursuing better system performance includinghigher reliability and robustness, while the positive bidirec-tional buck-boost chopper devotes itself to voltage balancingbetween vP2−P1 and vP1−M , and the negative buck-boostchopper plays its part between vM−N1 and vN1−N2.

III. SYSTEM CONFIGURATION

Fig. 2 shows the 200-V, 5.5-kW laboratory motor drivesystem that is designed, contructed, and tested in this paper.Fig. 3 shows the dc-link voltage and the individual split dccapacitor voltages. Table I sumarizes the circuit parameters ofthe experimental system.

The rectifier and the inverter with the same carrier frequencyas 3 kHz are operated independently, and the two buck-boost choppers with the same carrier frequency as 3 kHzare controlled independently. The rectifier is connected tothe 200 V laboratory ac mains through an ac inductance ofLAC = 5.2%. No switching ripple filter is installed upstreamof LAC . The inverter is directly connected to a 200-V, 5.5-kW induction motor without any inductor. The motor is

TABLE IRATINGS AND CIRCUIT PARAMETERS IN FIG. 1.

Power rating 5.5 kWRated ac voltage 200 VInductance of ac link inductor LAC 1.2 mH (5.2% )Resistance of ac link inductor RAC 2 mΩ (0.03 % )DC capacitor voltage Vdc 85 VSplit dc capacitor Cdc 10 mFDC link voltage 4Vdc 340 VUnit capacitance constant H 26 ms (340V)Chopper inductor LP =LN 4.2 mHCarrier frequency fC 3 kHz

on a three-phase, 50-Hz, 200-V, 5.5-kW, 16-A base

mechanically coupled with a permanent-magnet synchronousgenerator connected to a three-phase resistive load.

Fig. 4 shows the sinusoidal PWM technique used in theexperimental system, which is based on a single referencesignal e∗ and four 3-kHz carrier signals with different dc-bias voltages. The unit capacitance constant H [s] in Table Iis defined by the ratio of the energy [J] stored in the dc-linkcapacitor with respect to the power rating [W]. Since each ofthe four dc-link capacitors has the same capacitance as Cdc

= 10 mF, the unit capacitance constant H is 26 ms under 2.5mF, 340 V, and 5.5 kW.

IV. ANALYSIS OF DC MEAN CURRENT FLOWING INTO

TWO NODES P1AND M

When the dc mean currents flowing into, or out of, nodes P1,N1, and M are nonzero, voltage imbalance occures betweenthe corresponding dc capacitors. The dc mean currents flowing

1457

IM

200 V, 5.5 kW50 Hz200 V

LACiSvS

vS

iS

θ

e∗

eR eO

LP

LN

iLP

iLN

iRP1

iRM

iIP1

iIMiO

P1

M

N1

N2

P2

Voltage-balancingcircuitRectifier Inverter

f∗

V ∗dc

A/DPLL

A/D

(DSP)Calculation

(FPGA)PWM

4

424

24

DCCT

PT

TR1

TR2

TR3

TR4

TR5

TR6

TR7

TR8

TI1

TI2

TI3

TI4

TI5

TI6

TI7

TI8

Fig. 2. The 200-V 5.5-kW laboratory motor drives system.

vP2−N2

vP2−M

vM−N2

vP2−P1

vP1−M

vM−N1

vN1−N2

P2

P1

M

N1

N2

Fig. 3. The dc-link voltage and split dc-capacitor voltages.

into, or out of, nodes P1 and N1, come from the same principleof operation. This section conducts theoretical analysis of thedc mean curents of iRP1 and iRM in the rectifier.

A. Voltage Reference and Duty Factor

Fig. 5 shows the relations between a voltage reference e∗

and duty factors DP1 and DM . A duty factor represents aratio of a time interval, during which the line or motor currentflows into, or out of, a node, with respect to a period of theline frequency (50 Hz) or the inverter frequecy. Thus, theinstantaneous current flowing into, or out of, a node is givenas the product of the corresponding duty factor and the lineor motor current. Assuming that the PWM carrier frequencyis much higher than the maximal inverter frequency, the dutyfactors DP1 and DM are given by

DP1 =

⎧⎨⎩

0 (VN2−M ≤ e∗ < 0)e∗/VP1−M (0 ≤ e∗ < VP1−M )2 − e∗/VP1−M (VP1−M ≤ e∗ ≤ VP2−M ),

(1)

DM =

⎧⎪⎪⎨⎪⎪⎩

0 (VN2−M ≤ e∗ < VN1−M )1 + e∗/VP1−M (VN1−M ≤ e∗ < 0)1 − e∗/VP1−M (0 ≤ e∗ < VP1−M )0 (VP1−M ≤ e∗ ≤ VP2−M ).

(2)

B. The DC Mean Current Flowing into Node P1

It is assumed that the rectifier line-to-neutral voltage refer-ence e∗ and the source or line current iS are the followingsinusoidal waveforms.

e∗ =√

2E sin ωt (3)

iS =√

2I sin(ωt + φ)=

√2Id sin ωt −

√2Iq cos ωt (4)

Here, E is the rms value of the rectifier line-to-neutralvoltage reference. The dc mean current iRP1 in a steady statecan be defined as an average value of the instantaneous currentflowing into the node P1 over a period of the line cycle T (=20 ms). Therefore, iRP1 is given by

iRP1 =3T

∫ T

0

DP1iS dt =6T

∫ T4

0

DP1iS dt. (5)

Let the time, when√

2E is equal to VP1−M , be TVP1−M.

It is given by

TVP1−M =1ω

sin−1

(VP1−M√

2E

). (6)

When√

2E ≥ VP1−M , iRP1 is given by

iRP1 =6Id

ωT

[E

VP2−M

{4ωTVP1−M

− 2 sin(2ωTVP1−M)

−π} +2√

2 cos(ωTVP1−M)]. (7)

When√

2E ≤ VP1−M , iRP1 is given by

iP =6Id

ωT

(Eπ

VP2−M

). (8)

1458

VP2−M

VP1−M

0

VN1−M

VN2−M

e∗

Fig. 4. A converter voltage reference signal and four carrier signals for the5-level converter.

e∗

D

DP1

DM

0−2Vdc −Vdc Vdc 2Vdc

1

Fig. 5. Converter voltage e∗ and duty factors DP1 and DM .

It should be noted that the reactive current Iq is excludedfrom (7) and (8), and that the active current Id and the outputvoltage E determine iRP1. When attention is paid to thedirection of iIP1, the dc mean current flowing in the positivechopper inductor LP , iLP is given as the substraction of iIP1

from iRP1.

iLP = iRP1 − iIP1 (9)

Fig. 8 shows the theoretical results obtained from (9) whenthe inverter is operated with the rated constant-torque load,while Fig. 9 shows those when the inverter is operated with afan/blower-like load.

C. The DC Mean Current Flowing into Node M

The dc current flowing into node M, iM gets zero, irrespec-tive of the rectifier or the inverter.

iM =3T

∫ T

0

DM iS dt = 0. (10)

Equation (10) implies that as long as the voltage referencee∗ and the source current iS are sinusoidal waveforms, no dcmean current flows into node M. However, in an actual five-level converter, a small amount of dc mean current may flowinto node M, because component tolerances and tuning errorsexist in both power and control circuits. Therefore, the volt-ages vP2−M and vM−N2 might get imbalanced. Fortunately,applying the volt-per-hertz control to the five-level invertermakes vP2−M and vM−N2 automatically balanced because ofexistance of the following internal negative feedback loop thatan increased capacitor voltage is accompanied by an increasedloss, which in turn makes the capacitor voltage decrease.

V. CONTROL OF THE FIVE-LEVEL RECTIFIER AND

INVERTER

A. Overall Control

The control system is based on a fully-digital control circuitusing DSPs and FPGAs. Each data sampling of the sourcevoltages and currents, and the four dc capacitor voltages are

iSu

iSv

iSw

vSu

vSv

vSw

4V ∗dc

vP2−N2

vSd

vSq

iSd

iSq

i∗Sd

e∗Rd

e∗Rq

e∗Ru

e∗Rv

e∗Rw

+

–

d-q

d-q

trans.

trans.

PI

Decoupledcurrentcontrol

Inv.d-q

trans.

DC-link voltage control

Fig. 6. A control block diagram of the rectifier.

+–

+–

+–

vP2−P1

vP1−M

v∗LPi∗LP

iLP

PI P

Carrier signal (3 kHz)

Comparator

Gatesignals

Voltageregulator

Currentregulator

Fig. 7. The control block diagram of the positive chopper in the voltage-balancing circuit.

performed at every top and bottom of the four carrier signalswith different dc-bias voltages. Fig. 6 shows the control blockdiagram of the rectifier. It consists of decoupled current controlthat have been described in [11], and dc-link voltage control.The so-called ”volt-per-hertz” control with a base voltage andfrequency of 200 V and 60 Hz is applied to drive the 200-V,5.5-kW induction motor. The five-level rectifier and inverteruse four common carrier signals, as shown in Fig. 4.

B. DC-Link Voltage Control

The dc-link voltage between P2 and N2 is regulated by aPI controller that detects vP2−N2 and compares it with its dc-link voltage reference 4V ∗

dc. The PI controller is designed tohave a proportional gain of 0.25 A/V, and an integral gain of0.6 A/V·s.

C. Voltage-Balancing Control

As shown in Fig. 2, the voltage-balancing circuit consistsof two positive and negative buck-boost choppers operatedindependently. Fig. 7 shows the control block diagram ofthe positive chopper for achieving voltage balancing betweenvP1−M and vP2−P1. A proportional-plus-integral (PI) con-troller for voltage regulation is designed to have a proportionalgain of 5.0 A/V, and an integral gain of 0.02 A/V·s. Aproportional (P) controller for current regulation is designedto have a proportional gain of 0.1 V/A. A common 3-kHztriangle-carrier signal is used to produce the gate signals forthe two choppers.

VI. ACTUAL SWITCHING FREQUENCIES OF THE IGBTS IN

THE FIVE-LEVEL CONVERTER

The five-level diode-clamped converter consists of a stringof eight IGBTs per leg. As shown in Fig. 2, the eight IGBTs

1459

|iLP |

iRP1

iIP1

0

5

10

15

20

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

DC

mea

nch

oppe

rcur

rent

[A]

Inverter modulation index

Fig. 8. Theoretical dc mean chopper current in the rated constant-torqueload.

|iLP |iRP1

iIP1

0

5

10

15

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

DC

mea

nch

oppe

rcu

rren

t[A

]

Inverter modulation index

Fig. 9. Theoretical dc mean chopper current in a fan/blower-like load.

are referred to as T1, T2, · · · , and T8 from the top to thebottom. During the converter voltage reference e∗ is higherthan VP1−M , T1 and T5 are repetitively switched on and off,and the other IGBTs keep unswitched. Moreover, during 0 <e∗ < VP1−M , T2 and T6 are switched on and off. Symmetricaloperation makes T1, T4, T5, and T8 have the same switchingfrequency, and T2, T3, T6, and T7 have the same switchingfrequency, but the two frequencies are unequal. Therefore, itis reasonable to consider the switching frequencies of T1 andT2 as fS1 and fS2. Since e∗ is given by (3), the period, duringwhich T1 is switched on and off, is specified as

TVP1−M ≤ t ≤ T

2− TVP1−M . (11)

Thus, the switching frequencies, fS1 and fS2 are given by

fS1 =T/2 − 2TVP1−M

TfC , (12)

fS2 =fC

2− fS1. (13)

When√

2E = VP2−M , and fC = 3 kHz, fS1 gets amaximal value of 1 kHz, while fS2 gets a minimal value of

TABLE IICURRENT THD AND HARMONIC CURRENTS OF iSu AND iOu AT 60 HZ,

200 V, 5.5 KW, EXPRESSED AS %

THD 2nd 3rd 4th 5th 7th 11th 40thRec. Side 3.9 0.8 0.4 0.3 2.8 1.4 1.9 0.3Inv. Side 3.5 0.2 0.3 0.4 2.8 1.6 0.7 1.0

vP2−M

vP1−M

vN1−M

vN2−M

vSu

iSu

eRu−M

eRu−v

vP2−N2

iOu

eIu−M

eIu−v

iLP

iLN

-20

0

20-20

0

20-400

0

400-200

0

200-40

0

40-200

0

200320

340

360-400

0

400-200

0

200-30

0

30-200

0

200

10 ms

[V]

[A]

[V]

[V]

[V]

[V]

[A]

[V]

[V]

[A]

[A]

Fig. 10. Experimental waveforms at 5.5 kW and 60 Hz.

500 Hz. Moreover, when e∗ ≤ VP1−M , fS1 gets zero, and fS2

gets 1.5 kHz. The rectifier voltage reference is nearly equalto the source line-to-neutral voltage vS , fRS1 � 1 kHz, andfRS2 � 500 Hz. On the other hand, since the amplitude of theinverter voltage reference is proportional to the output inverterfrequency, fIS1 = 0 ∼ 1 kHz, and fIS2 = 0.5 ∼ 1.5 kHz.

1460

vSu

iSu

eRu−M

eRu−v

iOu

eIu−M

eIu−v

iLP

iLN

-20

0

20-20

0

20-400

0

400-200

0

200-40

0

40-400

0

400-200

0

200-30

0

30-200

0

200

2 ms

[V]

[A]

[V]

[V]

[A]

[V]

[V]

[A]

[A]

Fig. 11. Time-expanded waveforms in Fig. 10.

VII. EXPERIMENTAL RESULTS

A. Constant-Torque Load Operation

The inverter frequency was controlled in a range 5 to 60Hz. The resistive load was adjusted to have the motor producethe rated torque. That is, the output power is proportional torotating speed.

Figs. 10 and 11 show observed waveforms when the motorwas operated at 5.5 kW and 60 Hz. Table II summarizes themeasured current THD (Total Harmonic Distortion) values andharmonic currents of iSu and iOu, where each value is a ratiowith respect to the fundamental current. Note that harmoniccurrents being less than 0.1% were excluded from Table II.Both waveforms of iSu and iOu have THD values lower than5.0%. Moreover, the waveform of iSu meets the Japaneseharmonic guideline that the line-current THD value is lessthan 5% and each harmonic current is less than 3%.

It is clear from Fig. 10 that the rectifier and invertervoltages with respect to point M, eRu−M and eIu−M are five-level waveforms, and that the rectifier and inverter line-to-linevoltage eRu−v and eIu−v are nine-level waveforms. These arepeculair to the five-level converter.

vP2−M

vP1−M

vN1−M

vN2−M

vSu

iSu

eRu−M

eRu−v

vP2−N2

iOu

eIu−M

eIu−v

iLP

iLN

-20

0

20-20

0

20-400

0

400-200

0

200-40

0

40-200

0

200320

340

360-400

0

400-200

0

200-30

0

30-200

0

200

10 ms

[V]

[A]

[V]

[V]

[V]

[V]

[A]

[V]

[V]

[A]

[A]

Fig. 12. Experimental waveforms at 3.2 kW and 35 Hz.

The dc voltage ripple of vP2−N2 stayed within ±0.7% whilethe dc mean voltage of vP2−N2 was 340V. The four split dccapacitor voltages of vP2−P1, vP1−M , vM−N1, and vN1−N2

are well balanced as shown in Fig. 10. The voltage ripplesof vP2−M and vP1−M stayed within ±2.3.% and ±1.7%,respectively. The rectifier switching frequencies of TR1 andTR2, fRS1 and fRS2 were 950 Hz and 550 Hz, respectively.The inverter switching frequency of TI1, fIS1 was 960 Hz,while that of TI2, fIS2 was 540 Hz. The dc mean currentsflowing into the chopper inductors, iLP and iLN were 1.39A, and −1.55 A, respectively. Fig. 11 shows time-expandedwaveforms of Fig. 10. The 3-kHz switching ripples weresuperimposed on the dc current iLP and iLN .

Fig. 12 shows observed voltage and current waveformsat 3.2 kW and 35 Hz. The possitive and negative dc-mean

1461

vP2−M

vP1−M

vN1−M

vN2−M

vSu

iSu

eRu−M

eRu−v

vP2−N2

iOu

eIu−M

eIu−v

iLP

iLN

-20

0

20-20

0

20-400

0

400-200

0

200-40

0

40-200

0

200320340

420-400

0

400-200

0

200-30

0

30-200

0

200

20 ms0 20 105

Overvoltage detected

[V]

[A]

[V]

[V]

[V]

[V]

[A]

[V]

[V]

[A]

[A]

Fig. 13. Experimental waveforms before and after disabling the voltage-balancing circuit at 3.2 kW and 35 Hz.

chopper currents got maximal values of iLP = −13.5 A, andiLN = 12.7 A, while the four split dc capacitor voltages werewell balanced. Because the inverter output voltage was reducedby volt-per-herz control, the number of voltage levels of eIu−v

was decreased to five.Fig. 13 shows observed voltage and current waveforms be-

fore and after the voltage-balancing circuit were intentionallydisabled at t = 20 ms during the motor was operated at 3.2kW and 35 Hz. As soon as the voltage-balancing circuit wasdisabled, the capacitor voltages vP2−P1 and vN1−N2 startedincreasing, and then they reached a overvoltage protectionlevel. Finally, the system was shut down at t = 105 ms. Theseexperimental waveforms confirmed the effectiveness of thevoltage-balancing circuit for achieving stable operation.

iL

TheoryOutput power

P

5.5 kW

|iLP ||iLN |

0

5

10

15

0

3.0

6.0

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

DC

mea

nch

oppe

rcu

rren

t[A

]

Out

put

pow

er[k

W]

Inverter modulation index

Fig. 14. DC mean chopper current and inverter modulation index in therated constant-torque load.

iL

TheoryOutput power P

5.5 kW|iLP ||iLN |

0

5

10

15

0

3.0

6.0

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

DC

mea

nch

oppe

rcu

rren

t[A

]

Out

put

pow

er[k

W]

Inverter modulation index

Fig. 15. DC mean chopper chopper current and inverter modulation indexin a fan/blower-like load.

Fig. 14 shows theoretical and experimental dc mean currentsof iLP and iLN at each inverter modulation index, wherethe theoretical values were obtained from (5) to (9). Thetheoretical and experimental results agreed each other withacceptable errors. The maximal currents were about 80% ofthe rated current of 16 A.

B. Fan/Blower-like Load Operation

Fig. 15 shows experimental results when the resistive loadwas adjusted to act as a fan or a blower in which the outputpower is proportional to a cubic of rotating speed. When aninverter modulation index was 0.63, that is, the inverter outputfrequency was 40 Hz, the dc mean inductors currents iLP

and iLN reached their maximal currents of -5.5 A and 5.1 A,respectively. The maximal currents were one-third as low asthe rated current of 16 A.

VIII. CONCLUSION

This paper has discussed the 6.6-kV transformerless back-to-back system using two five-level diode clamped PWMconverters for motor drives. Attention has been paid to voltage-balancing control of the common four dc capacitors connectedin series. These voltages can be balanced by the voltage-balancing circuit consisting of two bi-directional buck-boostchoppers. Theoretical anlysis has been carried out on the dcmean currents flowing in the chopper inductors. Experimental

1462

results obtained from a 200-V 5.5-kW laboratory model haveverified the effectiveness of the voltage-balancing circuit andthe validity of the theoretical analysis.

REFERENCES

[1] A. Nabae, I. Takahashi and H. Akagi, “A new neutral-point-clampedPWM inverter,” IEEE Trans. on IAS, vol.17, No.5, pp.518-523, 1981

[2] J. S. Lai, and F. Z. Peng, “Multilevel converters-A new breed of powerconverters,” IEEE Trans. on Ind. Appl., vol.32, No.3, pp.506-517, 1996

[3] F. Auerbach, M. Glantschnig, A. Porst, J. G. Bauer, D. Reznik, H. J.Schulze, J. Gottert, M. Hierholzer, T. Schutze, and R. Spanke, “6.5 kVIGBT modules,” Conf. Rec. IEEE-IAS Annu.. Meeting, Phoenix, AZ, pp.1770-1774, 1999

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