Basic Computer

• The following discussions are based on a fictitious computer called “Basic Computer” by the author of the textbook

• It’s a much better way to learn computer architecture concepts than trying to understand the Intel Pentium architecture

Assembly Language

• Every computer architecture (or family of architectures) has its own unique assembly language

• Unlike Java, you should not learn assembly language syntax, data types, etc.

• You should learn to program/think at the assembly language level– It’s a way of thinking that requires intimate knowledge

of the underlying hardware architecture

Assembly Language Instructions

• Each instruction has two basic parts– Operation code (opcode)

• What the instruction wants the processor to do

– Operand(s) (registers, memory addresses)• Data location that the instruction wants the

processor to manipulated

• Some operands will be explicit while others will be implicit (implied by the opcode)

Assembly Language Instructions

• n-bit instruction format

• Example – 16 bit instruction

opcode operand/address0m+1 mn-1

opcode operand/address012 1115

2(n-1)-(m+1) opcodes

2(m+1) addresses

24 = 16 opcodes

212 =4096 addresses

Assembly Language Instructions

• Instructions within the same Assembly language may be of differing lengths– i.e. not all instructions utilize the same

number of bits as we saw with the Pentium

Internal Operation

• To execute an assembly language instruction the processor goes through 4 steps– Fetch an instruction from memory– Decode the instruction– Read the operands from memory/registers– Execute the instruction

• This is often referred to as the Fetch-Execute cycle or the Instruction cycle

• To execute a program the processor repeats this cycle until a halt instruction is reached

Internal Operation

• All this is under the control of the Control Unit• This is the component that decodes the

instruction and sends out microoperations to the rest of the hardware– The control unit can be hardwired

• Made up entirely of sequential circuits designed to do precisely the fetch-execute steps – fixed instruction set

– The control unit can be microprogrammed• A small programmable processor within the processor –

programmable instruction set

• More on this later

Addressing Modes

• In designing a computer architecture the designer must specify the instruction set– Opcode/operand pairs

• In specifying operands there are a number of alternatives– Immediate instructions– Direct address operands– Indirect address operands

Immediate Instruction

• The 2nd part of the instruction is the operand (rather than the address of the operand)

• An example might be an instruction that adds a constant to a register

add 3

– The “3” is the value we want to add, not an address in memory

Direct Address Instruction

• The 2nd part of the instruction is the memory address of operand

• An example might be an instruction that adds a value in memory to a register

add 0x30213

– The “0x30213” is the memory address of the value that we want to add

Indirect Address Instruction

• The 2nd part of the instruction is the memory address of the location that holds the memory address of the operand

• An example might be an instruction that adds a value in memory to a register

add 0x30213

– The “0x30213” is a memory address that holds the memory address of the value that we want to add

Addressing Modes

I opcode address

0 addc 3 0 add 0x33 1 add 0x33

0x420x33 0x420x33

0x880x42

Operand

Operand

Operand

Immediate Direct IndirectMode bit

Addressing Modes

• The term effective address refers to the actual address of the operand– For the previous example

• Immediate address mode– Effective address is the instruction itself

• Direct address mode– Effective address is the memory location 0x33

• Indirect addressing mode– Effective address is the memory location 0x42

Addressing Modes

• Something in the instruction word will specify which addressing mode is applicable– The operand itself (for immediate instructions)– A designated bit (for direct vs. indirect

address instructions)

Addressing Modes

• Indirect addressing is a convenient way to implement arrays (which are nothing more than pointers to blocks of contiguous memory)

• Some architectures define additional modes such as “read location then increment”– These are all derivations of the three defined

here

Registers

• In designing a computer architecture the designer must specify the register set

• There are essentially two categories– Special purpose registers– General purpose registers

Special Purpose Registers

• Program Counter (PC)– Holds the memory address of the next instruction of

our program

• Memory Address Register (AR)– Holds the address of a location in memory that we

want to access (read/write)

• The size of (number of bits in) these two registers is determined by the number of memory addresses in our architecture

Special Purpose Registers

• Instruction Register (IR)– Holds the instruction (opcode/operand) we are about

to execute

• Data Register (DR)– Holds the operand read from memory to be sent to

the ALU

• Accumulator (AC)– Holds an input to the ALU and the output from the

ALU

Special Purpose Registers

• Input Register (INPR)– Holds data received from a specified external

device

• Output Register (OUTR)– Holds data to be sent to a specified external

device

General Purpose Registers

• Temporary Register (TR)– For general usage either by our program or

the architecture

Registers• These registers (shown previously) are specified for the fictitious

architecture given in the textbook• All architectures will have these in some form• Most architectures will have more than just these

– More general purpose registers– Stack pointers– Interrupts– Program status bits– Multiple I/O ports– Timers– etc.

• To effectively program the architecture (in assembly language) you need to be aware of all the available registers and their usage

• High level language compilers possess this knowledge

Bus

• In designing a computer architecture the designer must specify the bus layout– The size of the bus (in bits)– What is connected to the bus– Access control to the bus

• Recall that a bus is an efficient alternative to lots of wires when it comes to transferring data between registers, control units, and memory locations

Bus Architecture

Memory unit4096x16

AR

PC

DR

AC

INPR

IR

TR

OUTR

ALUE

16-bit Bus

address

clock

S2S1S0

111

001

010

011

100

101

110

AccessSelect

Bus Architecture

• The three access select lines determine which register is allowed to write to the bus at a given time (recall that only one write at a time is allowed)

• Registers have load input signals (LD) that tell them to read from the bus

• If registers are smaller than the bus (less bits) than unused bits are set to 0

• Some registers have additional input signals– Increment (INR) and Clear (CLR)– See figure 5-4, page 130 of the textbook

Bus Architecture

• Memory has read/write input signals that tell it when to take data from the bus and send data to the bus

• Memory addresses (for both read and write operations) are always specified via the Address Register (AR)– An alternative (used in many architectures) is a two

bus system• One address bus• One data bus

Bus Architecture

• Results of all ALU (arithmetic, logic, and shift operations) are always sent to the Accumulator (AC) register– The ALU is the only way to set values into the accumulator

except for the clear (CLR) and increment (INR) control lines

• Inputs to the ALU come from– The Accumulator (AC)– The Data Register (DR)– The Input Register (INPR)

• The E output from the ALU is the carry-out (Extended AC) bit– Many architectures pack this into a register with other status bits

such as overflow

Bus Architecture

• Some pairs of microoperations can be performed in a single clock cycle– The key is to make sure they don’t both try to

put data on the bus– Consider the RTL statement

DR ← AC, AC ← DR

– This is allowed since the DR ← AC microoperation uses the bus while the AC ← DR microoperation does not

Instructions

• We said previously that there are two parts to an instruction– Opcode– Operand

• Realistically the two parts should be called– Opcode– Everything else

Instructions

• Three basic types– Those that reference memory operands– Those that reference register operands– Those that reference I/O devices

• Again, this is only for the fictitious architecture in the textbook but you will find similar categorizations in real architectures

Memory Instructions

I opcode address

011121415

I = 0 means direct memory addressI = 1 means indirect memory address

• There are 14 instructions in this class– 7 direct memory address forms– 7 indirect memory address forms

Memory Instructions

Hex Code

Symbol I = 0 I = 1 Description

AND 0xxx 8xxx Mem AND AC

ADD 1xxx 9xxx Mem + AC

LDA 2xxx Axxx Load AC from Mem

STA 3xxx Bxxx Store AC to Mem

BUN 4xxx Cxxx Unconditional Branch

BSA 5xxx Dxxx Branch to Subroutine

ISZ 6xxx Exxx Increment and Skip if Zero

Register Instructions

• There are 12 instructions in this class– They can use the “operand field” to specify

the register and type of operation since no memory address is required

0 1 1 1 Register operation

011121415

Register Instructions

Symbol Hex Code Description

CLA 7800 Clear AC

CLE 7400 Clear E bit

CMA 7200 Complement AC

CME 7100 Complement E bit

CIR 7080 Circulate right AC and E

CIL 7040 Circulate left AC and E

INC 7020 Increment AC

Register Instructions (cont.)

Symbol Hex Code Description

SPA 7010 Skip next instruction if AC is positive

SNA 7008 Skip next instruction if AC is negative

SZA 7004 Skip next instruction if AC is 0

SZE 7002 Skip next instruction if E is 0

HLT 7001 Halt

I/O Instructions

• There are 6 instructions in this class– They can use the “operand field” to specify

the exact operation since no memory address is required

1 1 1 1 I/O operation

011121415

I/O Instructions

Symbol Hex Code Description

INP F800 Input character to AC

OUT F400 Output character from AC

SKI F200 Skip on input flag

SKO F100 Skip on output flag

ION F080 Interrupt on

IOF F040 Interrupt off

Instruction Decoding

• The control unit evaluates bits 15 – 12 to determine the instruction format

• At first glance it appears that there can be only 8 unique instructions since the opcode resides in 4 bits

• But, additional instructions are created through the use of the I bit an unused bits in the operand field

Instruction Set Design

• To be useful, an architecture’s instruction set must contain enough instructions to allow all possible computations

• Four categories are necessary– Arithmetic, logical, shift operations– Moving data to/from memory from/to registers– Control such as branch and conditional

checks– Input/output

Instruction Set Design

• The set in the book is complete in that all the possible operations on binary numbers can be performed through combinations of instructions

• But, the set is very inefficient in that highly used operations require multiple instructions

• This is why the Pentium instruction set is so large and complicated – it makes for efficient programs