basic concepts and architectures - digital...

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11© IMSE-CNM ΣΔ Design Group

CMOS SigmaCMOS Sigma--Delta Converters Delta Converters ––From Basics to StateFrom Basics to State--ofof--thethe--ArtArt

RocRocííoo del Rdel Ríío, o, BelBeléénn PPéérezrez--VerdVerdúú and Josand Joséé M. de la RosaM. de la Rosa

{rocio,belen,jrosa}@imse.cnm.es

KTH, Stockholm, April 23-27

Basic Concepts and ArchitecturesBasic Concepts and Architectures


2. Fundamentals of 2. Fundamentals of ΣΔΣΔ ADCsADCs

3. Discrete3. Discrete--Time Time ΣΔΣΔ ModulatorsModulators

OversamplingOversampling

Quantization noise shapingQuantization noise shaping

Basic architectureBasic architecture

Classification of Classification of ΣΔΣΔ ADCsADCs

OUTLINEOUTLINE

SingleSingle--bit singlebit single--quantizer architecturesquantizer architectures

Dual quantizationDual quantization

MultiMulti--bit quantizationbit quantization

Bandpass Bandpass ΣΔΣΔ modulatorsmodulators

1. Introduction1. Introduction

4. Continuous4. Continuous--Time Time ΣΔΣΔ ModulatorsModulatorsBasic concepts and topologiesBasic concepts and topologies

Synthesis methodsSynthesis methods

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Introduction: Introduction: Basic ADC processBasic ADC processBasic ADC process


Introduction: Introduction: Basic ADC processBasic ADC processBasic ADC process

Sampling process

Limits the input signalfrequency

Speed of the ADC

Quantization process

Limits the input signalaccuracy

Resolution of the ADC

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Introduction: Introduction: Resolution vs. conversion rateResolution vs. conversion rateResolution vs. conversion rate

CMOS ADCsCMOS ADCs

ΣΔΣΔ ADCsADCs

Nyquist ADCsNyquist ADCs


Introduction: Introduction: QuantizationQuantizationQuantization

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Introduction: Introduction: QuantizationQuantizationQuantization

[Enge99]

Quantization input-output characteristic

Quantization error White noise model

- If x varies randomly from sample to sample

- If the # of quantizer levels is high


Introduction: Introduction: Quantization Quantization Quantization --- white noise modelwhite noise modelwhite noise model

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Oversampling

Classification of ADCs

Nyquist-rate ADCs (M~1)

Oversampling ADCs (M>>1)

Introduction: Introduction: SamplingSamplingSampling


PSD of oversampled quantization noise

Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: OversamplingOversamplingOversampling

In-Band Noise power (IBN or PQ)

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Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: Performance MetricsPerformance MetricsPerformance Metrics


Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: Performance MetricsPerformance MetricsPerformance Metrics

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Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: Quantization Noise ShapingQuantization Noise ShapingQuantization Noise ShapingProcessing of the quantization error

In-band noise power and effective resolution


Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: Basic Basic Basic ΣΔΣΔΣΔ ADC architectureADC architectureADC architecture

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SigmaSigma--DeltaDeltaADCADC

NyquistNyquistADCADC

HIGHHIGH--SELECTIVITY ANALOG FILTER SELECTIVITY ANALOG FILTER for antifor anti--aliasingaliasing

Overall resolution obtained using Overall resolution obtained using HIGHHIGH--ACCURACY ANALOG BLOCKSACCURACY ANALOG BLOCKS

LOWLOW--SELECTIVITY ANALOG FILTER SELECTIVITY ANALOG FILTER for antifor anti--aliasing (1st/2nd order)aliasing (1st/2nd order)

High overall resolution obtained using High overall resolution obtained using LOW/MODERATELOW/MODERATE--ACCURACY ANALOG BLOCKSACCURACY ANALOG BLOCKS

HIGHHIGH--SELECTIVITY DIGITAL FILTERSELECTIVITY DIGITAL FILTER

EASIER AND MORE ROBUST IN MODERN CMOSEASIER AND MORE ROBUST IN MODERN CMOS

Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: NyquistNyquistNyquist---rate vs. rate vs. rate vs. ΣΔΣΔΣΔ ADCsADCsADCs


H(z) with large gainwithin the signal band

1st1st--order order ΣΔΣΔMML L thth--order order ΣΔΣΔMM

Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: BasicBasic ΣΔΣΔΣΔM architectureM architectureM architecture

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DT ΣΔM CT ΣΔM

Low-Pass ΣΔM Band-Pass ΣΔM

Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: Classification of Classification of ΣΔΣΔΣΔMsMsMsNature of the signals being handled: Low-pass vs. Band-pass

Dynamics of the loop filter: Discrete-Time vs. Continuous-Time

Number of bits of the embedded quantizer: single-bit vs. multi-bit

Number of quantizers employed: single-loop, cascade, etc..

Type of primitives available in the fabrication technology…


H(z) with large gainwithin the signal band

L L thth--order order ΣΔΣΔMM

Oversampling, Oversampling, OSROSR

Order of the shaping, Order of the shaping, LL

Resolution of the Resolution of the internal quantizer, internal quantizer, BB

Speed of analog circuitry Speed of analog circuitry

Stability of the Stability of the ΣΔΣΔM M

Linearity of the DAC Linearity of the DAC

L B

Fundamentals of Fundamentals of ΣΔΣΔ ADCs: ADCs: Basic control parametersBasic control parameters

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DTDT--ΣΔΣΔMs: Ms: 1st1st--order LPorder LP ΣΔΣΔΣΔ ModulatorModulatorModulator

Using a linear model for the quantizer



Ramp input & 1-bit quantizer

Sinewave input & 3-bit quantizer

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Noise pattern



DTDT--ΣΔΣΔMs: Ms: 2nd2nd--order LPorder LP ΣΔΣΔΣΔ ModulatorModulatorModulator

1st-order ΣΔ Modulator

2nd-order ΣΔ Modulator

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DTDT--ΣΔΣΔMs: Ms: 2nd2nd--order LPorder LP ΣΔΣΔΣΔ ModulatorModulatorModulator

Linear analysis

Output spectrum and noise pattern


purepure--differentiator FIRdifferentiator FIR NTFNTFProne to instabilityProne to instability

2nd2nd--order order ΣΔΣΔMM

L L thth--order order ΣΔΣΔMM

Stable for inputs inif

[Candy85]

High-order ΣΔ loops areonly conditionally stable [OptE90]

IIRIIR NTFNTFss

Zeros at Zeros at zz = 1= 1

Gain adjusted to satisfy

[Lee87]

Butterworth/Chebyshev polesButterworth/Chebyshev poles

(1)(1)(1)(1)

DTDT--ΣΔΣΔMs: Ms: HighHigh--order Singleorder Single--loop loop ΣΔΣΔΣΔ ModulatorsModulatorsModulators

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OPTIMIZED IIROPTIMIZED IIR NTFNTFss

Complex zeros at |Complex zeros at |z z | = 1 with optimal | = 1 with optimal positions within the signal bandpositions within the signal band

[Schr93]


(2)(2)

(2)(2)(1)(1)

5th5th--order NTForder NTF((OSR OSR = 64)= 64)

IIRIIR NTFNTFss

Zeros at Zeros at zz = 1= 1

Gain adjusted to satisfy

[Lee87]


(1)(1)



(2)(2)

Distributed feedback andDistributed feedback anddistributed feedforward inputdistributed feedforward input

(1)(1)

(2)(2) Feedforward summationFeedforward summation+ local resonators+ local resonatorsComplexity (many feedback/feedforward coeffs)Complexity (many feedback/feedforward coeffs)

Large spread of coeffs (area, power)Large spread of coeffs (area, power)


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Systematic loss of resolution, but:

MASH MASH ΣΔΣΔMsMs

Each stage re-modulates a signal containing the quantization error in the previous one.

Digital processing is used to cancel out all quantization errors, but that in the last stage.

Error Cancellation Logic (ECL)Error Cancellation Logic (ECL)

d > 1, interstagecoupling

Smaller than for single loopsIndependent of OSR

HIGHHIGH--ORDER STABLE OPERATIONORDER STABLE OPERATION is ensured by cascading low-order stages (Li = 1, 2).

Relationships among ECL and ΣΔM to be fulfilled for perfect cancellation (NOISE LEAKAGENOISE LEAKAGE).

Performance close to idealPerformance close to ideal

Small spread of analog coeffsSmall spread of analog coeffsECL can be easily implementedECL can be easily implemented

Suited at low oversamplingSuited at low oversampling

DTDT--ΣΔΣΔMs: Ms: HighHigh--order Cascade order Cascade ΣΔΣΔΣΔ ModulatorsModulatorsModulators


11--11--1 1 ΣΔΣΔMM [Mats87]

4th4th--order 2order 2--stage cascadestage cascade22--2 2 ΣΔΣΔMM

4th4th--order 3order 3--stage cascadestage cascade22--11--1 1 ΣΔΣΔMM

[Kare90]

[Yin94]

22--1 1 ΣΔΣΔMM [Longo88]22--22--1 1 ΣΔΣΔMM [Vleu01]22--11--11--1 1 ΣΔΣΔMM [Rio00]22--22--2 2 ΣΔΣΔMM [Dedic94]

Noise leakage precludes the cascading ofa large number of stages to be practical

DTDT--ΣΔΣΔMs: Ms: HighHigh--order Cascade order Cascade ΣΔΣΔΣΔ ModulatorsModulatorsModulators

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Element TrimmingElement TrimmingAnalog CalibrationAnalog CalibrationDigital CorrectionDigital Correction

Increased dynamic rangeIncreased dynamic range

Better stability propertiesBetter stability properties

DAC nonDAC non--linearities are directly linearities are directly added to the inputadded to the input

B can trade for OSR (wideband)

More aggressive high-order NTFs

The linearity of the ΣΔM will beno better than that

Correcting DAC errorsCorrecting DAC errors

DEM techniquesDEM techniques

Decorrelating DAC errorsDecorrelating DAC errorsfrom the inputfrom the input

FULLFULL--PARALLEL ADC/DACPARALLEL ADC/DAC(Typically B < 6)

DAC linearity limited byDAC linearity limited bycomponent mismatchcomponent mismatch

Dual quantizationDual quantization

Introducing DAC errorsIntroducing DAC errorsat a nonat a non--critical positioncritical position

POSSIBLE APPROACHESPOSSIBLE APPROACHES

DTDT--ΣΔΣΔMs: Ms: MultiMulti--bitbit ΣΔΣΔΣΔ ModulatorsModulatorsModulators


Increased dynamic rangeIncreased dynamic range

Better stability propertiesBetter stability properties

DAC nonDAC non--linearities are directly linearities are directly added to the inputadded to the input

B can trade for OSR (wideband)

More aggressive high-order NTFs

The linearity of the ΣΔM will beno better than that

ELEMENT SELECTIONELEMENT SELECTIONLOGICLOGIC

FULLFULL--PARALLEL ADC/DACPARALLEL ADC/DAC(Typically B < 6)

DAC linearity limited byDAC linearity limited bycomponent mismatchcomponent mismatch

Elements selected to make DAC errors independent of the input signal

Dynamic Element Matching (DEM)Dynamic Element Matching (DEM)

Algorithms that try to average the error in each DAC level to zero (to push DAC errors to high freq.)

Randomization: Distortion transforms into white noiseRotation: Distortion moves out of band (CLA)Mismatch-shaping: 1st/2nd order (ILA, DWA, DDS)

DTDT--ΣΔΣΔMs: Ms: MultiMulti--bitbit ΣΔΣΔΣΔ ModulatorsModulatorsModulators

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Combines 1-bit and multi-bit quantizers (linearity/reduced error)

Dual QuantizationDual Quantization

LeslieLeslie--SinghSingharchitecturearchitecture

[Lesl90]Concept applied to singleConcept applied to single--loop loop ΣΔΣΔMsMs [Hair91]

Concept applied to cascade Concept applied to cascade ΣΔΣΔMsMs [Bran91]

L-0 cascade ΣΔMSuffers from noise leakageMulti-bit quantization does not improve stability

Improved stabilityNoise leakage

Multi-bit quantization usually applied only in the last stage

DAC errors shaped by L-LNRelaxes DAC requirements

Noise leakage (inherent to cascades)

DTDT--ΣΔΣΔMs: Ms: DualDual--quantizationquantization ΣΔΣΔΣΔ ModulatorsModulatorsModulators


DTDT--ΣΔΣΔMs: Ms: Bandpass Bandpass ΣΔΣΔΣΔ Modulators Modulators Modulators ––– IF DigitizationIF DigitizationIF Digitization

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DTDT--ΣΔΣΔMs: Ms: Bandpass Bandpass ΣΔΣΔΣΔ Modulators Modulators Modulators


DTDT--ΣΔΣΔMs: Ms: Bandpass Bandpass ΣΔΣΔΣΔ Modulators Modulators Modulators

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DTDT--ΣΔΣΔMs: Ms: Bandpass Bandpass ΣΔΣΔΣΔMs Ms Ms ––– Signal band location Signal band location Signal band location


DTDT--ΣΔΣΔMs: Ms: LPLPLP---tototo---BP Transformation Method BP Transformation Method BP Transformation Method

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DTDT--ΣΔΣΔMs: Ms: Bandpass Bandpass ΣΔΣΔΣΔ Modulators Modulators Modulators Other BP-ΣΔM architectures


DTDT--ΣΔΣΔMs: Ms: Bandpass Bandpass ΣΔΣΔΣΔ ADCs ADCs ADCs --- DecimationDecimationDecimation

Bandpass decimation

Efficient decimation

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Continuous-Time ΣΔMs

CT front (loop filter) partDT back (quantizer) partSampling inside the loop

CTCT--ΣΔΣΔMs: Ms: Basic ConceptsBasic ConceptsBasic Concepts

Discrete-Time ΣΔMs

DT loop filterAll internal signals are DTSampling at the input


AA Filter

Pros of CT-ΣΔMs

Implicit anti-aliasing filterLess impact of sampling errorsNo input switches – potentially better for low-voltage supplyNo “settling” error at the loop filter circuitryPotentially larger operation speed with less power consumptionNo sampling of the noise at the input capacitorsReduced digital noise coupling

Counters of CT-ΣΔMs

Very involved dynamic due to the combination of non-linearity, CT and DTlarger impact of circuit non-linearitiesTime constant tuning is needed for correct loop filteringLarge sensitive to time uncertainty (“jitter”)


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Linear analysis of CT-ΣΔMs, assuming [Bree01]:

Linear model for the quantizerDAC gain is unity in the signal bandwidth

Example: Lth-order, B-bit single-loop architecture



DT-to-CT synthesis method: pulse invariant transformation (freq. domain)

Find an equivalent DT ΣΔM that fulfils the required specificationsBased on a DT-to-CT equivalence [Cher00]

Open-loop configuration

CTCT--ΣΔΣΔMs: Ms: Synthesis MethodsSynthesis MethodsSynthesis Methods

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Application of DT-to-CT method to cascade CT ΣΔMs

Every state variable and DAC output must be connected to the integrator input of theulterior stages in the cascade [Ortm01]Increases the number of analog components (transconductors and amplifiers)

DT-to-CT



Direct synthesis method [Bree01]Uses the desired NTF as a starting point, (as for the DT case)An Inverse Chevychev distribution of the NTF zeros has advantages in terms of SNR and stability

Application to cascade architectures [Tort06]Optimum placement of poles/zeroes of the NTFSynthesis of both analog and digital part of the cascade CT ΣΔ ModulatorReduced number number of analog components

DT-to-CT

MethodDirect

Method


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1 1.5

2 2.5

0 0.20.40.60.81

8

10

12

14

16

18

σc(%)σgm(%)

SN

R L

oss

(dB

)

1

1.5

2

2.5

0 0.20.40.60.81

4

6

8

10

12

14

σc(%)σgm(%)

Direct synthesis of cascade architectures (I) [Tort06]

Sensitivity to mismatch (gm,C)A 2-1-1 example

DT-to-CT synthesis method Direct synthesis method



Direct synthesis of cascade architectures (II) [Tort06]


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A case study: A 12-bit@20MHz, 4-b, 2-1-1 CT ΣΔM for VDSL [Tort06]D

irect

synt

hesi

sm

etho

d



[Bree01] L. Breems and J.H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Kluwer Academic Publishers, 2001.

[Cherr00] J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Kluwer Academic Publishers, 2000.

[Enge99] J.V. Engelen and R. van de Plassche, BandPass Sigma-Delta Modulators: Stability Analysis, Performance and Design Aspects. Kluwer Academic Publishers, 1999.

[Geer02] Y. Geerts, M. Steyaert and W. Sansen: “Design of Multi-bit Delta-Sigma A/D Converters”. Kluwer, 2002.

[Mede99] F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators. Kluwer Academic Publishers, 1999.

[Nors97] S.R. Norsworthy, R. Schreier, and G.C. Temes (Editors), Delta-Sigma Data Converters: Theory, Design and Simulation. IEEE Press, New York 1997.

[Pelu99] V. Peluso, M. Steyaert, and W. Sansen, Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters. Kluwer Academic Publishers, 1999.

[Rabi99] S. Rabii and B.A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. KluwerAcademic Publishers, 1999.

[Rio06] R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez, CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design. Springer, 2006.

[Rodr03] A. Rodríguez-Vázquez, F. Medeiro and E. Janssens, CMOS Telecom Data Converters. KluwerAcademic Publishers, 2003.

[Rosa02] J.M. de la Rosa, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips. Kluwer Academic Publishers, 2002.

[Shoa95] O. Shoaei, Continuous-Time Delta-Sigma A/D Converters for High Speed Applications. Ph.D. Dissertation, Carleton University, 1995.

General ReferencesGeneral References

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