basicfabricationsteps andlayout - sharif

Basic Fabrication Stepsand Layoutand Layout

Somayyeh KoohiDepartment of Computer Engineering

Sharif University of TechnologyAdapted with modifications from lecture notes prepared by

author

Outline

� Fabrication steps� Transistor structures� Transistor behavior

Modern VLSI Design: Chap2 2 of 35Sharif University of Technology

� Transistor behavior�NMOS�PMOS

� Latch up

Foundry & Fab

� Foundry : fabrication line for hire�Foundries are major sources of fab capacity today

� Fab : Design and fabricate


� Fab : Design and fabricate

Silicon Lattice

� Semiconductor� Conductivity changed by adding

impurities� Impurities, called dopants, create

either n-type or p-type regions Si SiSi

Si SiSi


either n type or p type regions

� Transistors are built on asilicon substrate

� Silicon is a Group IV material� Forms crystal lattice with bonds

to four neighbors

Si SiSi

Si SiSi

Dopants

� Silicon is a semiconductor� Pure silicon has no free carriers and conducts poorly� Adding dopants increases the conductivity

� Gro p V (A i Ph h ): e tra electron (n t pe)


� Group V (Arsenic, Phosphorus): extra electron (n-type)� Group III (Boron): missing electron, called hole (p-type)

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

p-n Junctions

� A junction between p-type and n-typesemiconductor forms a diode

� Current flows only in one direction


� Current flows only in one direction

N-Diff P-Diff

anodecathode

Fabrication processes

� IC built on silicon substrate:� some structures diffused into substrate� other structures built on top of substrate


� Substrate regions are doped with n-type and p-typeimpurities� (n+ = heavily doped)

� Wires made of polycrystalline silicon (poly), multiplelayers of aluminum (metal)

� Silicon dioxide (SiO2) is insulator

Simple cross section

SiO2

metal2

metal3


substraten+ n+p+

substrate

metal1

poly

transistor via

Photolithography

Mask patterns are put on wafer using photo-sensitive material:


Process steps

First place tubs to provide properly-doped substrate forn-type, p-type transistors:

p-tub n-tub


Pattern polysilicon before diffusion regions:substrate

p-tub n-tub

poly polygate oxide

Process steps, cont’d

Add diffusions, performing self-masking:


p-tub n-tub

poly poly

n+n+ p+ p+

Process steps, cont’d

Start adding metal layers:

metal 1 metal 1


p-tub n-tub

poly poly

n+n+ p+ p+

vias

Outline




� Latch up

Transistor structure

n-type transistor:


0.25 micron transistor (Bell Labs)

silicide

gate oxide


poly

source/drain

Transistor layout

n-type (tubs may vary):

L


w

Basic transistor parasitics

� Gate to substrate, also gate to source/drain� Source/drain capacitance, resistance


Basic transistor parasitics (Cont’d)

� Gate capacitance Cg�Determined by active area

� Source/drain overlap capacitances C C d


� Source/drain overlap capacitances Cgs, Cgd�Determined by source/gate and drain/gate overlaps�Independent of transistor L�Cgs = Col W

� Drain/bulk & source/bulk capacitance

Outline




� Latch up

NMOS Transistor� Four terminals: gate, source, drain, body� Gate – oxide – body stack looks like a capacitor

� Gate and body are conductors� SiO2 (oxide) is a very good insulator


2 ( ) y g� Called metal – oxide – semiconductor (MOS) capacitor

� Even though gate isno longer made of metal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

NMOS Operation� Body is commonly tied to ground (0 V)� When the gate is at a low voltage

� P-type body is at low voltage� Source-body and drain-body diodes are OFF


y y� No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S

� When the gate is at a high voltage� Positive charge on gate of MOS capacitor� Negative charge attracted to body� Inverts a channel under gate to n-type� Now current can flow through n-type silicon from source through

NMOS Operation (Cont’d)


� Now current can flow through n type silicon from source throughchannel to drain, transistor is ON

� This induced channel forms a resistor (more carriers in the channel,lower the resistance)

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

� Poly-oxide-silicon sandwich under the gate is acapacitor�To increase voltage, need to add positive charge to

l d i h ili

NMOS Operation (Cont’d)


poly and negative charge to silicon� Initially, negative charge comes from pushing

away holes� After threshold voltage is reached, channel of

mobile electrons formed

PMOS Transistor� Channel carriers have positive charge� Similar, but doping and voltages reversed

� Body tied to high voltage (VDD)� Gate low: transistor ON

� Attracts holes to form a thin p-region allows holes to flow from p+ to p+� G t hi h t i t OFF


� Gate high: transistor OFF� When channel not formed, p+ regions are isolated by back-to-back diodes

� Bubble indicates inverted behavior

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

Drain current characteristics


Drain current

� Linear region (Vds < Vgs - Vt)�Id = k’ (W/L)[(Vgs - Vt)Vds - 0.5 Vds

2]� Saturation region (V ≥V - V )


� Saturation region (Vds ≥Vgs - Vt)�Id = 0.5k’ (W/L)(Vgs - Vt) 2

Power Supply Voltage

� GND = 0 V� In 1980’s, VDD = 5V� VDD has decreased in modern processes


� VDD has decreased in modern processes�High VDD would damage modern tiny transistors�Lower VDD saves power

� VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

0.5 µm transconductances

From a MOSIS process:� n-type:

�k ’ = 73 µA/V2


�kn = 73 µA/V�Vtn = 0.7 V

� p-type:�kp’ = 21 µA/V2

�Vtp = -0.8 V

Current through a transistor

� 0.5 µm parameters� W/L = 3/2� Measure at boundary between linear and saturation


yregions:

� Vgs = 2VId = 0.5k’(W/L)(Vgs-Vt)2= 93 µA

� Vgs = 5VId = 1 mA

Outline




� Latch up

Latch-up

� CMOS ICs have parastic silicon-controlled rectifiers(SCRs)

� When powered up


� SCRs can turn on� Creating low-resistance path from power to ground� Current can destroy chip

� Early CMOS problem� Can be solved with proper circuit/layout structures

Parasitic SCR structure� Parasitic bipolar transistors (pnp and npn) in a CMOS structure� The well and substrate have resistances RW and RS, respectively� Not completely isolated tubs

Twin tub


n+

p substrate

p+

A

YGND VDD

n+p+

substrate tap well tap

n+ p+

n wellRsub

Rwell

Vsub

VwellRsub

Rwell

Vsub

Vwell

n tub

Parasitic SCR� Two modes of operation:

� Both BJTs off� Both BJTs saturated � short circuit power supply


circuit I-V behavior

Solution to latch-up� Use tub ties with small resistance to connect tub to

power rail� n+ (heavily doped): low resistance

� Use enough to create low-voltage connection


� Use enough to create low voltage connection

Tub tie layout

p+


metal (VDD)

p-tub

basicfabricationsteps andlayout - sharif

Documents