BEE3 Update

Chuck ThackerJohn Davis

Microsoft ResearchChen Chang

BWRC/BEECube16 January 2008

Outline

• BEE3 board properties• BEE3 gateware• BEE3 schedule

Lab

John explains a tricky point to Chuck

BEE3

BEE3

Bandwidths (per-FPGA)• Memory

– 400 MT/s * 9B/T * 2 channels: 7.2 GB/s• Ring

– 500 MT/s * 9 B/T * 2 channels: 9.0 GB/s• QSH

– 400 MT/s * 10 B/T: 4 GB/s• Ethernet

– 125 MB/s• CX4

– 1.25 GB/s * 2 directions * 2 channels: 5GB/s• PCI Express

– Same as CX4

Initial Gateware• Mostly things required for production testing and

board characterization:• Signal connectivity checks

– Some are AC coupled, must test at speed– QSH tested with a crossover card

• Temperature and power supply monitoring• DDR-2 Controller

– Useful in other designs• CX4 and PCI Express for at-speed tests• Xilinx and others have lots of IP (alas, it either

doesn’t work very well, or is proprietary).

Project Participants and Roles• Microsoft Research (Silicon Valley)

– Funds, manages system engineering, does some gateware• Celestica (Ottawa and Shanghai)

– Did main board engineering, prototype fabrication– Microsoft has a very deep relationship with Celestica

• BEECube– Builds and delivers functioning systems

• Function Engineering (Palo Alto)– Did thermal and mechanical engineering

• Xilinx (San Jose)– Provides FPGAs for academic machines– Provides FPGA application expertise

• Ramp Group (BWRC)– Control board, basic software

• Ramp Community– Uses the systems for research– Expanding to industrial users (e.g., us)

Bring-up Status

• Most subsystems work:– Brought up a MicroBlaze on day 3 of bring-up– Ring wiring– 10 Gbit channels

• Works, but requires respin to relocate MGTs– GB Ethernet– PCI Express

Bring-up Status (2)• DDR2 controller doesn’t work (yet)

– Largest piece of “new” IP– Works flawlessly in post-route simulation– Timing complete at 200 MHz.

• Problems:– Design is complex

• Six Verilog modules, including a 36-bit RISC• Design turnaround is ½ hour (i.e., tools suck).• Simulator is slow

– Board testing uses ChipScope• Which doesn’t replace a ‘scope• Very difficult to probe

Schedule• Generate Specification – Done• Schematic Entry – Done• Board Layout – Done• Thermal modeling, heat sink design – Done• Chassis design -- Done• Signal Integrity – Done• Board Qualification – In progress• Board Respin -- TBD• Prototypes: Spring• Production: Start Summer ‘08