benchmarking current control methods using a single-phase ... · of the new current control method...

Benchmarking Current Control

Methods Using a Single-phase

Voltage Source Inverter Topology

Eric Lam

This thesis is presented for the degree of

Masters of Engineering Science (by Research)

at

The University of Western Australia

School of Electrical, Electronics and Computer Engineering

March 2010

Supervisors:

Dr. Lawrence J. Borle

Dr. Herbert H. C. Iu

Abstract

When faced with the task of developing a new current control method, it was soon realised

that there was not a consistent way to prove that a newly developed current control

method had made improvements over existing methods. Thus the focus of this thesis

turned towards investigating what aspects affect the fidelity (i.e. quality of control) of

current control methods for the given voltage source inverter (VSI ) topology. The main

purpose of such research would be to develop a set of criteria to justify any improvements

of the new current control method over existing current control methods and also identify

which particular aspects might show potential for improvement in control fidelity. Both

aspects require a way of measuring the capabilities of present methods and therefore

necessitates the establishment of desirable performance criteria. This effectively leads

to a “benchmark” approach to investigating the performance of existing current control

methods.

The highlights from carrying out this investigation are as follows:

• Phase-shift between the current output versus the reference current was observed to

be proportional to the target switching frequency of the considered current control

methods, which indicates an aspect of predictability that may have compensation

potential.

• The results also showed a proportional relationship between phase-shift and blanking

time, which would justify using appropriate compensation methods.

• Feedback delay was shown to contribute additional low-order harmonic content and

thus such delays should be minimised whenever possible.

• A control method that performs well independent of DC bus variation will make it

easier to design for, since it would be sufficient to just design the DC bus level to

meet a certain controllability margin (where this margin will ensure that the system

remains controllable even under transients and non-ideal assumptions).

• However, also take into consideration that there are diminishing returns from over

specification of this the DC bus margin.

iii

• Hysteretic or sliding mode controls using just the current as feedback is a very

useful quality, since the current controller tends to be more robust than those based

on modelling the system. For example, Hysteresis, Parabola and Ramptime did not

require significant redesign to change its operation from a pure inverter setup to a

shunt active power filter configuration.

Although not fully explored in this thesis, the next logical step would be to attempt to

implement ways to gain such improvements. To assist with incorporating these improve-

ments in future work, some implementation matters are discussed in light of developing

a new/improved current control method. Due to an expectation of increased controller

complexity, it is anticipated that a digital implementation would be preferred over an

analogue implementation. If such work was to be embarked upon by this author, then the

intention would be to:

• start with and build improvements upon the “best” current control algorithm inves-

tigated to have the most desired features/characteristics; and

• leverage the author’s existing experience in DSP development to implement the

control algorithm with a DSP.

.

iv

Contents

Abstract iii

Glossary xv

Acknowledgements xvii

Publications xix

Statement of contribution xxi

1 Introduction 1

1.1 Scope and Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Conventions and Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.1 Current error signal versus current difference signal . . . . . . . . . . 2

1.2.2 Per-unit representation of system quantities . . . . . . . . . . . . . . 2

1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Current Control Methods for Voltage Source Inverters 5

2.1 Voltage Source Inverter Topology . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 CC-VSI and Controllability . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.2 CC-VSI in Active Power Filter (APF) applications . . . . . . . . . . 8

2.2 Desirable Current Control Characteristics . . . . . . . . . . . . . . . . . . . 12

v

CONTENTS

2.2.1 Low harmonic distortion . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.2 Fast transient responses and fast control loop . . . . . . . . . . . . . 14

2.2.3 Tolerance to parameter change . . . . . . . . . . . . . . . . . . . . . 15

2.2.4 Zero-Average Current Error . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.5 Ideas exploited by control algorithms . . . . . . . . . . . . . . . . . . 17

2.3 Current Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.1 Proportional Integral Triangular Carrier Current Control . . . . . . 19

2.3.2 Standard Hysteresis Current Control . . . . . . . . . . . . . . . . . . 23

2.3.3 Parabola Current Control . . . . . . . . . . . . . . . . . . . . . . . . 25

2.3.4 Ramptime Current Control . . . . . . . . . . . . . . . . . . . . . . . 28

3 Analysing the Performance of Existing Current Controls for Voltage

Source Inverters 35

3.1 Benchmarking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.1.1 Current Reference Waveform . . . . . . . . . . . . . . . . . . . . . . 37

3.1.2 Developing Appropriate Measures of Control Fidelity . . . . . . . . . 39

3.2 Computer Assisted Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3 Simulation-based Analysis with Practical Considerations . . . . . . . . . . . 43

3.3.1 Base Case under Ideal Assumptions . . . . . . . . . . . . . . . . . . 43

3.3.2 Blanking Time Effects . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3.3 DC Level Requirements for Controllability . . . . . . . . . . . . . . . 45

3.3.4 Robustness to DC Bus Fluctuation . . . . . . . . . . . . . . . . . . . 45

3.3.5 Inductance Parameter Dependency . . . . . . . . . . . . . . . . . . . 46

3.3.6 Behaviour from Feedback Inaccuracies (Noise and Lag) . . . . . . . 46

3.3.7 All Conditions from 3.3.1 to 3.3.6 are Combined . . . . . . . . . . . 46

3.3.8 Lower Target Switching Frequency . . . . . . . . . . . . . . . . . . . 47

vi

CONTENTS

3.3.9 Adjusting the Control Methods for Analysis . . . . . . . . . . . . . . 47

3.4 Active Power Filter as a benchmark . . . . . . . . . . . . . . . . . . . . . . 48

4 Results and Discussion 51

4.1 Results from the Simulation-based Analysis . . . . . . . . . . . . . . . . . . 51

4.1.1 General Observations . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.1.2 Base Case for Ideal Performance . . . . . . . . . . . . . . . . . . . . 59

4.1.3 Blanking Time Effects . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.1.4 DC Voltage Requirements for Controllability . . . . . . . . . . . . . 62

4.1.5 Robustness to DC Bus Fluctuation . . . . . . . . . . . . . . . . . . . 63

4.1.6 Inductance Parameter Dependency . . . . . . . . . . . . . . . . . . . 64

4.1.7 Behaviour from Feedback Inaccuracies (Noise and Lag) . . . . . . . 64

4.1.8 All Conditions from 3.3.1 to 3.3.6 are Combined . . . . . . . . . . . 68

4.1.9 Lower Target Switching Frequency . . . . . . . . . . . . . . . . . . . 68

4.2 Initial results from hardware-based Active Power Filter experiment . . . . . 69

5 General Implementation Advice 73

5.1 Some Implementation Warnings and Issues . . . . . . . . . . . . . . . . . . 73

5.1.1 Dealing with some common issues . . . . . . . . . . . . . . . . . . . 74

5.2 Allowing For Control Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3 Suggested Future Development Platform . . . . . . . . . . . . . . . . . . . . 77

5.3.1 Analogue or Digital Implementation? . . . . . . . . . . . . . . . . . . 77

5.3.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . 78

6 Conclusion 83

6.1 What has the investigations revealed? . . . . . . . . . . . . . . . . . . . . . 83

6.2 Future Continuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

vii

CONTENTS

6.2.1 Possible avenues for control design/improvement . . . . . . . . . . . 84

6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

A Technical Data 87

A.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

A.2 Source code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

A.2.1 MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Bibliography 105

viii

List of Figures

2.1 1-ph FB CC-VSI Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Phasor diagrams that show the controllability relationship under the de-

scribed scenarios (top: in-phase; mid: inverter appears purely inductive;

bottom: inverter appears purely capacitive) . . . . . . . . . . . . . . . . . . 8

2.3 Basic shunt APF configuration . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Block diagram of the basic shunt APF topology used in this work . . . . . . 11

2.5 ZACE Current Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 Simplified (Linearized) Current Ripple . . . . . . . . . . . . . . . . . . . . . 18

2.7 PI Triangular Carrier Current Control . . . . . . . . . . . . . . . . . . . . . 21

2.8 PI Triangular Carrier Control Model . . . . . . . . . . . . . . . . . . . . . . 21

2.9 Potential for noise to cause earlier switching in Hysteresis current control . 24

2.10 1-ph HB CC-VSI topology assumed in Parabola current control derivations 25

2.11 Parabola current control behaviour with double parabolic bands . . . . . . 26

2.12 One of the suggested circuits for implementing Parabola current control . . 27

2.13 Error signal with relevant Ramptime timing variables labelled . . . . . . . . 29

2.14 Polarised Ramptime current control block diagram . . . . . . . . . . . . . . 31

3.1 Inductive load where uncontrollable region becomes apparent . . . . . . . . 38

3.2 Steady-state and the transient waveforms for current reference (per unit

based) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.3 DC bus fluctuation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

ix

LIST OF FIGURES

4.1 Distortion: Overview of analysis (Steady-state, 20 kHz) . . . . . . . . . . . . 52

4.2 Phase-shift: Overview of analysis (Steady-state, 20 kHz) . . . . . . . . . . . 54

4.3 Phase-shift: Overview of analysis (Steady-state, 5 kHz) . . . . . . . . . . . . 54

4.4 ESDi: Overview of analysis (Steady-state, 20 kHz) . . . . . . . . . . . . . . 55

4.5 ESDi: Overview of analysis (Steady-state, 5 kHz) . . . . . . . . . . . . . . . 55

4.6 Example of steady-state PI waveform in 5 kHz system with 90 out-of-phase

reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.7 ESDi: Overview of analysis (Transient, 20 kHz) . . . . . . . . . . . . . . . . 57

4.8 Distortion: Overview of analysis (Transient, 20 kHz) . . . . . . . . . . . . . 57

4.9 ESDi: Overview of analysis (Transient, 5 kHz) . . . . . . . . . . . . . . . . 58

4.10 Distortion: Overview of analysis (Transient, 5 kHz) . . . . . . . . . . . . . . 58

4.11 Distortion: Overview of analysis (Steady-state, 5 kHz) . . . . . . . . . . . . 59

4.12 Distortion: Blanking time (Steady Steady and Transient, 20 kHz and 5 kHz) 60

4.13 Phase-shift: Blanking time (Steady-state, 20 kHz and 5 kHz) . . . . . . . . 61

4.14 ESDi: Blanking time (Steady-state, 20 kHz) . . . . . . . . . . . . . . . . . 61

4.15 Distortion: DC margin (Steady-state and Transient, 20 kHz and 5 kHz) . . 62

4.16 ESDi: DC margin (Steady-state, 20 kHz and 5 kHz) . . . . . . . . . . . . . 63

4.17 Potential explanation for supposed improved performance in Hysteresis . . 64

4.18 Distortion: Inductance variation (Steady-State and Transient, 20 kHz and

5 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.19 Distortion: Feedback Inaccuracies (Steady-state and Transient, 20 kHz and

5 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.20 ESDi: Feedback Delay (Steady-state and Transient, 20 kHz and 5 kHz) . . 67

4.21 Phase-shift: Feedback Delay (Steady-state, 20 kHz and 5 kHz) . . . . . . . . 68

4.22 PI current control (pre-filtered current) . . . . . . . . . . . . . . . . . . . . 70

4.23 Hysteresis current control (pre-filtered current) . . . . . . . . . . . . . . . . 70

x

LIST OF FIGURES

4.24 Ramptime current control (pre-filtered current) . . . . . . . . . . . . . . . . 70

4.25 PI current control (post-filtered current) . . . . . . . . . . . . . . . . . . . . 71

4.26 Hysteresis curent control (post-filtered current) . . . . . . . . . . . . . . . . 71

4.27 Ramptime current control (post-filtered current) . . . . . . . . . . . . . . . 71

A.1 PSIM Shunt APF experiment schematic . . . . . . . . . . . . . . . . . . . . 88

A.2 PI triangular carrier current control implementation schematic . . . . . . . 89

A.3 Standard Hysteresis current control implementation schematic . . . . . . . 90

xi

List of Tables

3.1 Ideal System Parameters for 20 kHz . . . . . . . . . . . . . . . . . . . . . . 44

3.2 Blanking Delay For 20 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3 Combined Non-Ideal Parameters For 20 kHz System . . . . . . . . . . . . . 47

3.4 Adjusted Ideal System Paramters For 5 kHz . . . . . . . . . . . . . . . . . . 47

3.5 Initial APF System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.1 Legend for Charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 Phase-shift: Criteria specific results (Steady-state, 20 kHz) . . . . . . . . . . 53

4.3 Phase-shift: Criteria specific results (Steady-state, 5 kHz) . . . . . . . . . . 53

4.4 Measure values before the LC filter . . . . . . . . . . . . . . . . . . . . . . . 69

4.5 Measure values after the LC filter . . . . . . . . . . . . . . . . . . . . . . . . 69

5.1 DSP inside an FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

xiii

Glossary

1-ph single-phase

AC alternating current

ADC analogue-to-digital converter

APF active power filter

ASIC application specific integrated circuit

DC direct current

DSP digital signal processor

FB full-bridge

FPGA field-programmable gate array

HB half-bridge

IGBT insulated-gate bipolar transistor

GTO gate turn-off thyristor

IP intellectual property

MOSFET metal-oxide-semiconductor field-effect transistor

pu per-unit

PWM pulse-width modulation

RISC reduced instruction set computer

THD total harmonic distortion

VSI voltage source inverter

ZACE zero average current error

xv

Acknowledgements

Here I sincerely express my gratitude to the following peoples involved in supporting my

postgraduate research project.

• My family and friends - they have been very understanding and supportive through-

out the duration of my studies. A special mention goes to my parents.

• Mr. Hamdan Daniyal - a fellow research colleague and also great friend, whom I

have had the good fortune of being able to work and cooperate with. I will especially

remember his dedication and contributions to the joint development of a physical

hardware experiment.

• Mr. Silvio Ziegler - another wonderful friend and fellow research colleague, whom

also had a willingness to share both intellectually and socially. His focus and attitude

towards his work tended to flow on and motivate all those around him.

• Dr. Lawrence Borle - my original, but now external supervisor, whom is probably

one of the most considerate and selfless persons I have ever met — for despite leaving

his academic position to pursue a career back in industry, he generously continued

to offer supervision in a reduced-role. Without his technical knowledge and advice,

my ability to learn and conduct this research would have suffered significantly.

• Dr. Herbert Iu - my coordinating supervisor, whom kindly took me under his wing

after Dr. Borle left academia. Always willing and helpful whenever needed, his

academic insight and experiences were highly-valuable in the pursuit of publications.

• Past and present employers - for work arrangements that have permitted my con-

tinued studies.

• And others, whom I have shared social, intercultural and intellectual experiences as

part of my studies.

xvii

Publications

Conference papers:

• E. Lam (80 %), L. J. Borle, H. H. C. Iu, “Simulation-based analysis of current con-

trol methods for voltage source inverters with practical considerations” in 11th IEEE

Workshop on Control and Modeling for Power Electronics, Zurich, Switzerland, Pa-

per Number TS8.1, August 2008.

• H. Daniyal, E. Lam (40 %), L. J. Borle, H. H. C. Iu, “Comparing Current Con-

trol Methods Using an Active Power Filter Application as the Benchmark” in Aus-

tralasian Universities Power Engineering Conference, Sydney, Australia, Paper P-

112, December 2008.

Submitted for Journal publication:

• H. Daniyal, E. Lam (25 %), L. J. Borle, H. H. C. Iu, “Hysteresis, PI and Ramptime

Current Control Techniques for Active Power Filter Application: An Experimental

Comparison”, Submitted to: IEEE Transactions for Industrial Electronics, Date

submitted: 17 Jan 2010, Present status: Under review

xix

Statement of contribution

This thesis presents work that was either of my own or of various co-authors that included

myself during the candidature period. My main contributions are:

• arriving at the idea of “benchmarking” current control techniques, then carrying out

a corresponding simulation-based investigation (as per COMPEL 2008);

• also developing automation scripts (e.g. MATLAB M files) to assist in the pre-

processing and analysis of results from both simulation and experimental data;

• design and implementation of Hysteresis, Parabola and PI triangular carrier current

control boards for hardware experiments; and

• assisted in the analysis and write-up of collaborative papers (AUPEC 2008 and TIE

journal paper submitted in 2010 presently under review).

To further elaborate on joint collaborative work (see estimated proportion of contributions

indicated in the previous Publications section):

1. As indicated previously in the acknowledgements, Hamdan Daniyal put together

most of the APF experiment and I provided assistance in design decisions (in-

cluding safety considerations), construction/wiring and troubleshooting issues. In

terms of current controllers, Hamdan implemented Ramptime current control and

my contribution was Proportional-Integral and Hysteresis current control boards.

Subsequently, Hamdan performed most of the collection of experimental data and

I provided the MATLAB functions to analyse it. Together we have co-authored

an AUPEC 2008 conference paper presenting our findings from this data, where

each of us contributed approximately equal effort towards the preparation of this

publication. Hamdan did go on to attend and present the conference paper.

2. Hamdan and myself have taken the APF research further since the AUPEC paper

and have submitted it to a relevant journal for review. Due to noise issues at

higher power levels of our AUPEC setup, this research extension required a new

xxi

hardware setup. Since being preoccupied with writing up this thesis, my ability to

participate in this extended research were occasional and limited. Thus Hamdan has

contributed a significantly greater proportion of effort towards developing this new

hardware experiment platform, collecting and then processing results under it. That

said, I still managed to provide some support for automated processing of data via

MATLAB and had input into the write-up of the paper.

xxii

Chapter 1

Introduction

There are many current control methods in existence for the voltage source inverter topol-

ogy. Developing a new and improved current control method requires the understanding

of what existing current control methods are presently capable of. For this reason, bench-

marking is the strategy adopted to investigate current control performance. Benchmarking

is the practice of establishing a repeatable process for measuring performance against a

set of desirable criteria and then running each candidate of interest through this process.

Not only does benchmarking establish how well existing current control methods perform

based on the benchmark criteria, but also the same benchmark process will enable any

newly developed method to also be compared. Thus the creation of a suitable current con-

trol benchmark and applying it for a selection of existing methods was deemed a necessary

component in the preparatory groundwork for the development of an improved current

control technique.

1.1 Scope and Aim

The motivation behind this research topic was to be able to provide guidance for the

development of a new current control method. Although if time permitted, information

derived from this process could be used to design and implement a new current control

method. However, it was deemed that taking this to the next step would be a challenge

best left for a doctorate level degree (PhD) rather than the masters level degree targeted.

With this scope in mind, the thesis will discuss these specific research outcomes as follows:

• determine some suitable measures of control fidelity that allow unbiased comparisons

of different current controls;

• investigate what present current control methods are capable of;

1

1.2. CONVENTIONS AND NOTATIONS

• identify areas that might be improved; and

• suggest possible implementation issues and solutions.

Thus the primary contribution from this work is in measuring and comparing the

performance of existing current controls, where this would lead into further work on how

gains could be made in an improved current control method.

1.2 Conventions and Notations

1.2.1 Current error signal versus current difference signal

The current error signal (ie) in most literature follows standard control design convention,

where it is defined as the desired reference current minus the measured (actual) current

(Equation 1.1). However, some current control methods (particularly non-linear controls)

tend to adopt the current difference signal as the basis for controlling the current. This

current difference signal (idif ) is defined as the measured (actual) current minus the desired

reference current as in Equation 1.2. An obvious reason for choosing idif instead of ie is

because it is would be easy to recognise and interpret the ripple current in idif . Thus

expect to see idif in latter chapters, especially in Section 2.3.

ie = iref − imeas (1.1)

idif = imeas − iref = −ie (1.2)

, where:

• iref : reference current

• imeas: measured current

1.2.2 Per-unit representation of system quantities

The basic concept of the per-unit representation is to express quantities of the same type

(e.g. power, voltage, current) as a ratio of a selected base quantity of that same type. This

effectively turns the base quantity into a unit of measure. Per-units are generally used

in the field of electrical power systems, especially power transmission. Yet inexplicably,

it is not as commonly used for power electronics, even though it is still appropriate to

do so. The benefit of using per-units is to allow relevant system calculations to be done

efficiently. For example, a power system designed with per-units could be re-scaled for

2

INTRODUCTION

higher power ratings with relative ease. A minimum of two base quantities are required

to use the per-unit representation:

• Pbase (base power): nominal power rating of the system

• Vbase (base voltage): nominal voltage at that power rating

and a third is also defined for this work:

• f1 (base frequency): fundamental line frequency

The remaining base quantities automatically become defined as derivations of the

above, for example:

• Ibase (base current) =PbaseVbase

• Zbase (base impedance) =VbaseIbase

• Lbase (base inductance) =Zbase2πf1

• Tbase (base period) =1

f1

A quantity using the per-unit scale will typically be denoted by pu as its units. A

designer familiar with the per-unit system will then be able to recognise the relevant

base to use in their calculations. As an example, here are some quantities converted into

per-units, where the base power is 2400 W and the base voltage is 240 V:

• Ibase = 2400240 = 10A

• Zbase = 24010 = 24 Ω

• 1A = 1/10 = 0.1 pu

• 12 Ω = 12/24 = 0.5 pu

1.3 Thesis Outline

The basic structure of this thesis is as follows:

3

1.3. THESIS OUTLINE

• General introduction to the current control of a single-phase full-bridge voltage

source inverter topology and an overview of current control methods that are in-

vestigated in this work.

• Desirable qualities for current controls suitable for the VSI topology, which lead

to the development of a procedure (benchmark) to measure performance for these

qualities in existing current control methods. The same procedure can then be used

to justify any improvements when proposing new methods.

• Results from the benchmark procedure for some current control methods discussed

earlier.

• Some implementation suggestions based on the findings and control tuning experi-

ences. Also includes background information about DSP chips in anticipation that

the DSP will be the appropriate device for implementating an improved current

method.

• Future continuation and concluding remarks.

4

Chapter 2

Current Control Methods for

Voltage Source Inverters

For any given engineering problem, there are usually multiple ways to achieve a solution.

Thus it becomes necessary to have the scope defined, which restricts and targets our

investigation. The rest of this chapter will elaborate on the specific voltage source inverter

circuit topology and the relevant suitable current control methods to be covered in this

investigation.

2.1 Voltage Source Inverter Topology

The voltage source inverter (VSI) topology is a common topology used for DC-AC appli-

cations, including the following:

1. active power filters (APF);

2. uninterruptible power supplies (UPS);

3. solar inverters; and

4. motor drives

In this work we are specifically interested in the single-phase full-bridge configuration

that is depicted in Figure 2.1 below. The figure depicts MOSFET based switches, but

these can also be other switching devices such as IGBTs or GTOs depending on the

desired application ratings. Also, whilst this topology is capable of supporting voltage

control as well, our particular interest is in using it for current control applications. For

one, magnetic saturation issues can usually be avoided due to current control suppressing

5

2.1. VOLTAGE SOURCE INVERTER TOPOLOGY

the chance for build-up of the DC offset in the current, as opposed to pure voltage control

that would regulate the voltage in disregard of the current. Since we have particular

interest in current control of this topology, this control system is sometimes referred to as

“single-phase full-bridge current-controlled VSI” (or in shorthand: “1-ph FB CC-VSI”).

+−VDC

Sat

Sab

Sbt

Sbb

A

+

L

+ −VL

i L

Load

+

−

VLoad

−

BVI nv

Figure 2.1: 1-ph FB CC-VSI Topology

2.1.1 CC-VSI and Controllability

The CC-VSI control relies on the inductor to regulate the line current by switching the

voltage potential applied across the inductor between permitted switching configurations

for the given VSI topology. For proper current regulation, the control would impose a

positive voltage potential across the inductor to cause the current to “slope” upwards

and impose the opposite polarity across the inductor to cause the current to “slope”

downwards. However, since the potential is applied across the line inductor with a load,

then it is possible under certain load conditions for the line current to be uncontrollable (as

discussed later). Current feedback is acquired via imeas, which measures the line current

iL and typically performed by devices such as hall-effect current sensors. This measured

current would be compared against the desired reference current and depending on the

control strategy, the timing of switching and switching configuration are determined and

applied in a manner that would cause the line current to follow the reference current.

This research focuses on bipolar switching, which is one typical method of switching

operation for this topology and involves a full reversal of the DC bus voltage potential

applied between the mid-points (A and B). This corresponds to cross-alternating between

the two pairs of switches such that in one state the line voltage is imposed in one direction

and in the other state the line voltage in the opposite direction. Implementation of this

would simply involve sending the same control signals to Sat and Sbb and sending the

complementary control signals to Sab and Sbt. Although other switching schemes do

exist (e.g. unipolar switching), for this work it was decided that high-fidelity demanding

applications would be of interest — namely active power filters discussed later in this

chapter. Thus bipolar switching becomes the preferred choice for its greater controllability

despite some negatives (e.g. typically considered less efficient and has greater ripple than

6

CURRENT CONTROL METHODS FOR VOLTAGE SOURCE INVERTERS

unipolar switching). Readers should be able to find a more information about these

switching schemes in any good power electronics textbook.

An important issue to observe at this point is that the switching devices are non-ideal

in reality and always have finite turn “on” and “off” times that are often asymmetric or

at least, very difficult to make symmetric. If the control signals were to simply attempt

an immediate alternation of states as implied, then this sets up a situation for shorting

the DC bus. To avoid this issue, the control must introduce a suitable delay between the

instant we signal the turning “off” of one switch in a pair and the instant we signal the

turning “on” of the other switch in that pair. This delay is commonly known as blanking

time (also known as blanking delay or dead-time). However, this also presents a problem

that affects the resultant current output — the effective switching instant may become

delayed depending on the path of current flow. More specifically, when current transfers

from the free-wheeling diode to the switch, then blanking time imposes a delay to the

switching instant. But when current transfers from the switch to the free-wheeling diode,

then the switching instant is unaffected by blanking time.

Typically having the VDC greater than the peak expected voltages on inverter output

(i.e. load-side of inductor) will mean that the system is able to control the current, but this

does not always guarantee controllability (e.g. in the case of fundamental reactive power

flow). For full controllability of the given CC-VSI topology, the voltage output from the

inverter must be able to at least match the fundamental voltages applicable at the inductor

no matter what the currents required (e.g. even if the desired current is 90 out of phase

to the voltage). Whenever the control lacks full controllability there will be times when

it is unable to appropriately correct errors. This is because there is insufficient inverter

capability to source or sink current compared to that demanded, even if it went to the

duty-cycle extremes (i.e. fully-on or fully-off). Fixed switching frequency operation may

sometimes be sacrificed during these situations, since maintaining the extreme duty-cycles

will at least provide more optimal error correction.

Thus additional controllability requirements are needed so that the inverter is able to

compensate for any kind of load currents comprised of active and reactive components.

For example, such capability would reasonably be expected in APF applications to filter

out a certain level of line distortions. Equation 2.1 expresses the controllability margin as

a relationship between components involved in the expected fundamental line voltage and

DC bus voltage, which must be greater than zero for controllability.

VctrlMargin = VDC −Re~VLoad,fund + ~VL,fund

≥ 0 (2.1)

where VL,fund is the inductor voltage component and depends on the phase difference

between the line current and the line voltage. If the two are in-phase, then the minimum

requirement for controllability is when the VDC meets the requirements for the load. Oth-

7


erwise, if the inverter looks completely inductive (i.e. the output from the inverter has the

line current lagging the line voltage by 90 ), then VL,fund has the same magnitude of the

per-unit inductance multiplied by the fundamental load voltage VLoad,fund, but it is neg-

ative. Alternatively, if the inverter looks completely capacitive (i.e. the output from the

inverter has the line current lagging the line voltage by 90 ), then VL,fund is positive with

a magnitude equal to the per-unit inductance multiplied by the fundamental load voltage

VLoad,fund. From this we can see why reactive components will affect the controllability, in

that it may improve or worsen the prospects of controllability. To assist in understanding

the above situations, refer to the phase diagrams in Figure 2.2.

VLoad,fundIline

VL,fundVinv

= IL,fund

VLoad,fund

IlineVL,fund Vinv

= IL,fund

VLoad,fund

Iline

VL,fund

Vinv= IL,fund

VDC,min

VDC,min

VDC,min

~z = a+ bjj

j

j

Figure 2.2: Phasor diagrams that show the controllability relationship under the de-scribed scenarios (top: in-phase; mid: inverter appears purely inductive; bottom: inverterappears purely capacitive)

2.1.2 CC-VSI in Active Power Filter (APF) applications

As mentioned previously, CC-VSIs may be applied in Active Power Filter (APF) systems

with the goal of improving the quality of grid power and remains quite a popular research

subject over decades since the initial concepts of APFs were proposed in the 1970s [1–10].

The general aims of an APF are to:

8


• reduce distortions (such as harmonics) caused by non-linear loads;

• improve power factors for reactive loads; and

• in multi-phase systems, it may also perform load balancing.

Various topologies exist for APF applications [11], but specifically the basic shunt (some-

times called parallel) APF for a single-phase grid supply shall be considered in this work

as represented in Figure 2.3. This is because the primary focus of this work is to develop

a suitable test platform for determining the fidelity of various current controls and it was

identified that an APF application would perhaps prove to be a challenging yet realistic

way of determining the performance of current control methods. Notice that the grid

supply, APF (inverter) and load are tied to a common node, which has been labelled as

the Point of Common Coupling (PCC).

APF

Load

Gridigrid iload

iinv

PCC

imeasLPF

Figure 2.3: Basic shunt APF configuration

There are two main ways CC-VSIs can be used to perform active power filtering. One

strategy requires the calculation of compensation currents that would offset distortions

[7, 12]. This first approach usually requires measuring an additional current variable in

the system (typically iload). This is due to the inverter often being treated as standalone,

where the current control is merely concerned with the inverter output. Thus in this

situation, the current control is given the compensation current as its reference. But then

of course, additional information regarding the load must also be measured to be able to

compute this compensation current reference. The compensation current strategy provides

the designer with greater flexibility in determining what gets compensated and how, but

at the expense of computation time. Note that it is possible for compensation currents

be computed internally, but then included into a current reference suitable for the current

control of the grid current. This is the situation for the APF controller described in [10],

which appears to be more like a hybrid system combined with the second strategy to be

introduced shortly.

The other strategy is to avoid computing the compensation current altogether and

is often achieved by measuring and controlling the grid supply current (via the inverter)

directly rather than a computed current reference [13, 14]. Thus a “clean” sinusoidal

current reference that is in-phase with the grid voltage can be fed to the current controller,

which attempts to achieve this on the grid supply line. The complexity of implementation

9


can be immediately reduced using this approach, because it does not have to compute the

compensation current. Also there is no need to measure an additional variable, foregoing

any components associated with doing so. Hence it is deemed that under this approach,

the performance of the current control will never depend on how well the compensation

current is calculated. Finally, in line with our fidelity testing intentions, this strategy of

directly controlling the grid current would imply that more is demanded from the current

controller because it inherently factors in all errors for correction and thus supports a very

high control bandwidth (whereas compensation current calculations will tend to limit the

control bandwidth). As this is the more appropriate choice for the intentions of this work,

the explanations of how to control this system will be based on this particular approach

and will be the applicable APF system for all subsequent chapters.

To further explain this approach, Figure 2.4 expands upon the basic configuration

(previously shown in Figure 2.3) so that most internal components of the system are

visually represented — especially in the way of the required control blocks. Also notice

that this system can be considered the single-phase version of the three-phase APF system

described in [9, 14], as they share a very similar APF control scheme despite some variation

in the design (e.g. the low-pass filter). It is considered unnecessary to go to a three-phase

system, since a single-phase APF configuration should be sufficient in determining current

control fidelity. As from the diagram, the main signals that need to be measured for this

system are:

• the DC bus voltage (VDC);

• the voltage at PCC (VPCC); and

• the grid current to be controlled (imeas).

The measured VDC is passed through a low-pass filter, so that the result does not

contain all the ripples experienced from the switching. The resulting filtered VDC variable

is then compared against the desired bus voltage for it to be controlled by the outer loop

voltage regulator. In this work, the outer loop is a Proportional-Integral (PI) controller

and is tuned via empirical methods to arrive at acceptable stability and gains, which on

most occasions maintain VDC at the expected level. VPCC is measured for the phase-lock

loop (PLL) to be able synchronise the current reference to be in-phase with it. The inner

loop current control then uses the measured imeas to determine the required switching such

that the desired “clean” grid current is achieved, where presently the schematic shows a

PI triangular carrier current control.

In later discussions, the inner loop current control block will be substituted with other

suitable current control methods. However, since the grid line current is being measured

rather than the inverter current (iinv), the inner loop current control needs to take into

10


-+VDC

VDC,ref

PI OuterLoop

Voltage Control

Iref,mag

PhaseLockLoop(PLL)

CurrentReferenceGenerator

iref,unitysinwave

VPCC

iref

-+Inner LoopCurrentControl

Sgatesie

Non-linearLoad

iinv

imeas

PCC

VoltageSourceInverter

Sgates

Low-PassFilter(LPF)

iloadimeasGrid igrid

Figure 2.4: Block diagram of the basic shunt APF topology used in this work

consideration the direction of current flow from the inverter is opposite to that of the

measured grid current. The approach used in this work was to treat the input to the inner

loop control as it would be expected for a typical inverter, but adjust the output gating

signals so that they are appropriate for controlling igrid. This effectively means:

• if the inner loop current control was ie based, then continue using iref − imeas; or

• if the inner loop current control was idif based, then continue using imeas− iref ; and

• the current control gating signals are basically flipped, so that when the control

deems it necessary to switch igrid to move towards the positive direction, the control

actually demands the inverter to switch iinv in the negative direction (and vice-

versa).

Observe that there are two aspects to the controllability of this system corresponding

to the inner current control loop and outer voltage control loop requirements. The con-

trollability requirements for the inner current control loop will be pretty much the same as

for current control of a VSI, but becomes dependent on the outer voltage control loop due

to its regulation of the VDC bus voltage. The desired APF operation relies on there being

enough VDC bus voltage for the harmonic/reactive components to be partially, if not fully,

compensated for. Assuming the outer loop maintains a sufficient level of VDC voltage by

commanding an appropriately sized sinusoidal inner loop reference current that is in-phase

with the grid voltage, then the APF would automatically provide the currents to offset

the harmonics and reactive components drawn by the load. Or alternatively stated, this

should correspond to drawing a higher amplitude in-phase sinusoidal current from the grid

to:

11

2.2. DESIRABLE CURRENT CONTROL CHARACTERISTICS

• replenish and maintain the APF bus voltage, which is used for countering the har-

monics and reactive load current components (may also include inverter losses); and

• supply the active component of the load.

However, the controllability of the inner loop may be affected whenever there is a sud-

den significant increase in load current requirements (i.e. transients) — which is especially

the case for non-linear loads. If there is insufficient current being source from the grid, then

the load would attempt to source the rest from the inverter. As a result, the VDC bus will

temporarily sag assuming the voltage regulating outer loop is unable to respond quickly

enough in such situations. It may be tempting to make the outer loop respond faster,

but doing so will generally risk the stability of the outer loop voltage controller. Thus

it may not always be possible for full compensation to take place under such demanding

scenarios, and partial or even no compensation occurs whenever there is insufficient VDC

voltage to maintain full inner-loop controllability.

2.2 Desirable Current Control Characteristics

The purpose of the current control is to produce a current signal that is the same as

the desired reference current. Anything else present in the output signal is considered

distortion. In practice there will always be some level of distortion too costly to completely

remove, which is why various measures like total harmonic distortion (THD) exist to help

quantify it. Still, the aim is to avoid any imperfections found in the output current signal

and there are generally three aspects of distortion to consider:

1. DC offset: the offset from zero when comparing the generated current signal against

the current reference signal — equivalently described as when the average current

error signal is offset from zero. DC offsets drive magnetic components into saturation,

which is a problem given the presence of the line inductor in our topology. The risk

is that once the line inductor becomes saturated, then it no longer operates with the

desired behaviour, and consequently the controllability of the system is lost.

2. harmonics: considered to be the unwanted frequency components generated in the

output. Assuming that the current slopes are linear (current ripple looks triangular),

it is common for frequency components at odd-multiples of the switching frequency

to be generated in the output due to the switching action of these control strategies

(corresponding to the “triangular” current ripple form). Also, this means theoreti-

cally no even-frequency components of the switching frequency should be generated.

This is explained in further detail under “Low harmonic distortion”.

12


3. phase-shift: any phase-shift in the output current signal versus the current reference.

Typically control systems have slight phase lags due to the act of error correction

after the event. The reason that phase-shift is important is because power factor is

affected by the phase difference between the voltage and current. Any significant

phase-shifts of the generated current would imply a reduction in the power factor.

Fast transient responses become important here, because removing errors within the

shortest amount of time would reduce phase lag. Predictive methods or other meth-

ods of lag compensation may also be able to help reduce phase-shifts even further.

Similarly deadbeat controls, which attempt to reduce the error to zero within a given

number of time steps, are expected to incur phase-shifts that correspond to at least

that many number of time steps.

Keeping this in mind, you will find that most of the characteristics listed reflect the

desire to minimise all aspects of distortion and are generally important across the various

applications. However, I have also included some which are perhaps more application spe-

cific, with the hopes of finding out which current control methods may be more appropriate

for those specific applications.

2.2.1 Low harmonic distortion

Low harmonic current distortion is an important quality in quite a few applications be-

cause unwanted harmonics can shorten the lifetime for certain devices (e.g. transformers

and induction machines), since the harmonics can cause temperature rises beyond the

device ratings [15]. There also exist industry standards, such as the IEEE 519-1992 and

IEC 61000-3-6, which provide industry standard guidelines for measuring harmonics and

define acceptable limits on the level of harmonics to help guarantee power quality or min-

imise electromagnetic interference. Harmonics contribute to disturbances in more sensitive

equipment (e.g. telecommunications). Since typical systems will need to meet such re-

quirements for low harmonic content and this is generally achieved through using a filter

on the line output, which obviously adds to the cost and also represents a potential source

of instability if the cut-off frequency resonates with anything attached to the line (may

include the control loop itself).

Small low-order current harmonics distortion

Note that low-order harmonics is distinct from “low harmonics” discussed above and actu-

ally refers to harmonic distortions that are relatively close to the fundamental. Minimisa-

tion of these low-order harmonics are therefore addressed as a subset of the low harmonic

distortion quality. Due to the closeness of low-order harmonics to the fundamental, these

13


harmonic components would not be sufficiently attenuated even with a properly designed

output line filter. Ideally, minimal low-order harmonics will thus ensure that the shape

of the reference current is reproduced as closely as possible in the line output before the

filter and also allows the “low harmonic distortion” after filtering to be minimised as well.

The reason why this attribute was proposed was to measure and identify whether variable

switching frequency methods, such as Hysteresis, produce low-order harmonic components

of significance in comparison to the control methods that feature the switching character-

istics of being narrowband and relatively high frequency as discussed later.

Narrowband and relatively high switching frequency

The common switching action of the control strategy for this topology will contribute

harmonic distortion in the line current at the corresponding switching frequencies. A fil-

ter will need to be designed to remove such switching content. The purpose of having a

relatively high switching frequency is to move it significantly away from the fundamental

line current. This means that the filter designed would have minimal affect on the funda-

mental and also implies less cost for the filter itself. It also becomes desirable to have a

narrower switching frequency band in the frequency domain, as this reduces the filtering

requirements necessary to attenuate a narrower-band of switching harmonics. Thus many

control methods aim to target fixed-switching frequency operation for these reasons. An-

other benefit from fixed switching frequency operation is the opportunity to synchronize

switching action between multi-phase systems. With a switching synchronization across

the multiple phases, it is possible to offset the effects of one switching action against

another and thus reduce the requirements for magnetic components.

2.2.2 Fast transient responses and fast control loop

Fast transient response is important in applications such as APFs. APF applications re-

quire that the current control method be fast at reacting to sudden “pulse” currents drawn

by non-linear loads (e.g. diode bridge rectifier load). Thus apart from maintaining stabil-

ity, the current control used in an APF implementation must also be able to achieve good

performance in all three transient response parameters: fast start-up time, low overshoot

and fast settling time. Hysteresis Current Control is often recognised as the best current

control strategy under such criteria. A fast control loop should imply a fast transient

response, but this was included to address the minimisation of phase-shift.

14


2.2.3 Tolerance to parameter change

Tolerance to parameter changes is a very important characteristic to have. It is never

possible to get the ideal components in practice and so sources of variation include:

• slight difference between the true component value and the desired value (where

most components are manufactured with certain tolerance levels), which will result

in slight variation of system parameters;

• ideal models do not necessarily reflect true system behaviour, e.g. if inductors be-

come saturated or a purely resistive load is swapped for a diode rectifier loads, where

both cause very non-linear changes in system behaviour and parameters.

Variation of system parameters generally alter the initial assumptions during the design

and may therefore severely impact the behaviour and performance of the control method.

Subsequent to proper control design using the expected system parameters, there are two

ways of addressing parameter variation:

1. online parameter estimation which is an on-going self-adjusting process that usually

involves either many measurements and/or calculations;

2. higher-level abstraction which passively ignores the variation of system parameters

as long as the few parameters (may be single) being measured do capture the infor-

mation it needs for performing the control.

Online parameter estimation is often achieved in predictive control methods, but this may

be too expensive due to the calculations and/or additional measurement requirement. The

additional cost of the former may not be justifiable and this is where the latter shines.

We can consider Hysteresis and Ramptime current control methods as examples of the

latter, where both algorithms rely purely on information from the error signal to perform

control.

2.2.4 Zero-Average Current Error

Certain current control methods feature Zero-Average Current Error (ZACE), a control

characteristic initially coined in [16] and explained in detail by [17], but for convenience

the main points will be briefly covered here. Basically, it describes achieving an average

ripple current that will ideally approach zero within each switching instance and also a

balance in the areas enclosed by the excursions on either side of zero within one switching

period. ZACE by definition would guarantee that the output mostly comprises of the

desired current and on average the current should follow the reference in each switching

15


period. Note that when combined together with the first assumption, simply ensuring that

a zero-error crossing occurs at every half switching period implies a symmetrical balance

and achieves the desired average current within a switching period.

A1

−A1

A2

−A2

imeas

iref

Figure 2.5: ZACE Current Ripple

Although not immediately implied in Figure 2.5, an accurate ZACE control would

“slide” the window of consideration at each switching instance (i.e. half the switching

period) such that there is an overlap from the previous switching cycle, leading to −A1 ≈A2. Note that ZACE inherently caters for many desirable characteristic as follows.

Minimises low-order harmonics

As inherent from the symmetry, ZACE avoids introducing low-order harmonics from

switching as long as the given current reference is a clean sinusoidal. This is because

if the control was highly ZACE accurate, then it would achieve an average current that

matched the desired current reference for every switching period considered.

Approaches performance of dead-beat control

The very definition of ZACE implies that the error should be corrected within one switch-

ing period for the given current reference. This should mean that any control featuring

ZACE approaches the behaviour of dead-beat control or the ability to correct an error

within a guaranteed amount of time. This is basically governed by the control’s closed-

loop response, as the switching decisions must be able to be determined ahead of the next

switching period.

Avoids saturation of magnetics

Ideally ZACE would imply that DC offsets never exist, since there should be symmetry of

the areas bound by the error signal above and below the reference current. That is, the

16


actual current will have the DC content of the reference. Of course, in reality ZACE may

not always be achieved, but nevertheless it still helps.

2.2.5 Ideas exploited by control algorithms

Blanking delay compensation

A universal form of blanking time (i.e. applicable to any VSI control method) is to

alter the gate control signals by simply delaying the gate signal transition from “off” to

“on” by an appropriate time after the transition of the other gate signal from “on” to

“off”. However, in control methods that can pre-determine their switching instances for

a switching cycle (or half-cycle), it becomes possible to incorporate the blanking delay

into the timing of the switching instant so as to compensate for the delay and achieve

the effective switching instant at the time that was originally intended. Note because

blanking delay does not always affect the switching instant (as mentioned earlier in Section

2.1.1), it would be necessary for this compensation to take the direction of current into

consideration. Unfortunately this is not applicable to all control methods, so control

methods like Hysteresis will still need to use the standard approach. Balanced blanking

delay becomes particularly useful when the duty-cycle ratio approaches the extremes (0%

or 100%), since standard blanking delay effectively introduces an offset.

Linearity of current slopes within a switching period

Since the switching frequency is generally much faster than the rate at which the AC volt-

age changes and assuming full controllability, then it is possible to approximate the slopes

of inductor current in each direction as being temporarily “frozen” like constants. Put

in another way — when the switching frequency is significantly faster than the expected

voltage changes across the inductor, then the current ripple can often be imagined as linear

between switching instances. This switching ripple is depicted in the top part of Figure 2.6

and below it is an example switching signal of an ideal switch given the selected switching

period. It also leads to the use of “ramping up” and “ramping down” terminology, which

“ramping up” corresponds to when a positive voltage potential is applied across the line

inductor (L) and “ramping down” is when a negative voltage potential is applied across

the line inductor. As an example, this is a principle assumption used in the Ramptime

current control.

17

2.3. CURRENT CONTROL TECHNIQUES

imeas

iref

on

off

Figure 2.6: Simplified (Linearized) Current Ripple

Multi-phase inductor requirements reduction

Although not the focus of this work, multi-phase (e.g. three-phase grid connect) systems

can benefit from methods that have fixed switching frequency outputs as long as the

common node is floating (i.e. not connected to neutral). By having a fixed-switching

frequency, the outer loop control can then synchronise a pair of phases such that when

one line is pulled in one direction, the other line is pulled in the opposite direction. For

example, if we consider this in a three-phrase topology, one phase can be the standing

phase with the remaining two phases performing synchronised switching in this manner.

This effectively reduces the ripple on the lines and thus permits the designer to reduce the

inductor size, as demonstrated in [17].

2.3 Current Control Techniques

There are numerous current control techniques suitable for voltage source inverter topolo-

gies. The current control methods investigated in this work includes:

1. Proportional-Integral (PI) Triangular Carrier Current Control;

2. Hysteresis Current Control;

3. Ramptime Current Control; and

4. Parabola Current Control.

18


However, various applications involving CC-VSI have slightly different requirements that

make different aspects of current control performance more important than others. One

such example is the APF application already introduced and is further explored in later

chapters. Under APF applications, the transient performance of a current control method

tends to be of greater focus in an APF implementation.

This work purposely includes PI triangular carrier and Hysteresis current controls on

the basis that they are relatively easy to understand and well-known standard control

methods. They are also encountered in existing performance comparing work like [18] as

a standalone inverter current control and [3, 5, 7] under APF applications. The inclusion

of Ramptime and Parabola current control methods are due to their interesting charac-

teristics that should make them more favourable than the standard PI and Hysteresis for

certain application criteria. Each of these will we be discussed in further details in the

sections that follow. Predictive methods are not considered in this work because they tend

to rely heavily on accurate modelling of the system and are thus more application specific

and often very complicated in comparison to the methods considered here.

2.3.1 Proportional Integral Triangular Carrier Current Control

Proportional-Integral (PI) control is merely a special case (i.e. having zero differential

component) of the Proportional-Integral-Differential (PID) control. PID control is a well-

known and well-understood control technique and often considered the base standard for

performing linear control. As the name may already suggest, it simply comprises of each

component summed together:

1. the proportional component is the input multiplied by a certain scale KP and implies

that the output would be directly affected by the input as long as KP is non-zero.

2. the integral component is the integral of the input multiplied by a certain scale KI ,

which means that the output would be affected by all the past input values seen if

KI is non-zero.

3. the differential component is the differential of the input multiplied by a certain scale

KD and it determines how much the output should be affected by sudden changes

in input values, which is set to zero in PI control.

PID control is used in a variety of applications because it is simple and flexible, where the

coefficients KP , KI and KD required for achieving the desired control can be attained via:

1. an experimental tuning process (e.g. Ziegler-Nichols method); or

19


2. using equations derived from the system model to go through a theoretically optimal

design process and/or via a graphical design process (e.g. bode-plots and zeros-pole

placements).

Due to its simplicity, PID controllers do have limitations to the systems it can ade-

quately control. Therefore, some systems will be unsuitable for PID control. One potential

advantage from using PID control is the opportunity to use an empirical design approach,

such as Ziegler-Nichols method, to produce an appropriate control without much (if any)

knowledge of the underlying system model. In fact the system does not necessarily have to

be linear, as long as it can be approximated to a linear system with appropriate assump-

tions (i.e. based on the intended region of operation) [19]. The switching nature of the

CC-VSI topology is a clear sign of a non-linear system, but with certain linearization as-

sumptions a linear control method can be used to control it. This is demonstrated by many

existing research that have used PI-based current control in our topology of interest. Also

note that the derivative component is omitted to prevent the control from overreacting to

the inherent deviations away from zero error due to the nature of switching.

In the context of a CC-VSI, PI triangular carrier current control is applied in the

closed-loop sense by feeding in the current error (ie) as the input to a standard PI control.

Standard PI control is subsequently adapted for PWM output generation by comparing

the output value from the PI summation against a triangular carrier. Hence the full name

of PI triangular carrier current control, but for the sake of terseness this control will simply

be referred to as PI for the remainder of this thesis. The design approach used throughout

this work is mostly described as in [20], but it would be convenient to discuss it here. Also

be aware that the coefficients we use are only correct based on the signal polarities from

Figures 2.1 and 2.7.

For our purposes, only the analogue form of the standard PI control will be considered.

Although PI can be implemented digitally, discretization of the analogue PI control will

imply loss in performance compared to the pure analogue version. Hence the analogue

implementation will be used for comparison purposes as it should represent the best PI

can offer. The linear control model for this control method is as shown in Figure 2.8

directly from [20]. This contains approximations based on simplifying the VSI system to

exclude some difficult to model non-ideal and often non-linear behaviour (e.g. inductor

saturation). That said, this particular model includes a nominal inductor resistance (Rs)

that would be present in any realisable inductor.

Using this control model, it is now possible to convert the system into a transfer

function and then use it to design our PI controller. Note that any changes to the system

will generally need to be included in the system model for this method to arrive at a

suitable design and this is why empirical design methods are sometimes advantageous.

Without going into the details of the derivation, most of the same design assumptions and

20


KP

KI

+iref

−imeas

1s

+

+

+

−

Vtri

S

S

∑ ∑

Figure 2.7: PI Triangular Carrier Current Control

Figure 2.8: PI Triangular Carrier Control Model

recommendations are used from [20] to arrive at the exact design Equations 2.2 and 2.3

to solve for KP and KI . However, it is important to note that this model reflects only

the control of inverter current and would require remodelling for other control strategies

and/or topologies.

The shunt active power filter (APF) topology considered in this work is an example

where the above PI control model would fail. Under the shunt APF application discussed

earlier, a direct grid current control strategy is used and thus requires the reference current

waveform in the sinusoidal form that corresponds to the desired “clean” line current. This

is quite different to the indirect grid current control strategy commonly used by other

APF configurations, where a compensation current is calculated — in such scenarios, the

typical PI control model can still be used because the inverter current is being controlled

to produce the required offset current harmonics/distortions for the indirect cleaning of

the grid current. Works do exist for the study of PI current control in APF applications,

but more commonly via the generation of compensation currents.

Without opting for an alternative APF configuration to the shunt APF topology con-

sidered in this work, the PI controller was tuned via empirical methods for the given level

of load harmonics. It is important to note that under this shunt APF topology each time

the PI control is tuned, it will always be for a particular level of load harmonics. So any

changes to the expected load harmonic conditions will likely require the re-tuning of the

21


PI controller for it to continue operating effectively in the shunt APF application.

KI

KP=

ωCL

tan

(−90 + phm + 2tan−1

(ωCL

TS4

)+ tan−1

(ωCL

LSRS

)) (2.2)

KP =cPK

2VDC

RSGTI

√√√√√√√√

1 +

(ωCL

LSRS

)2

1 +

(1

ωCL

KI

KP

)2 (2.3)

where the following additional control design variables are required,

• cpk: triangular carrier peak amplitude;

• GTI : current transducer gain;

• ωCL: closed loop bandwidth; and

• phm: desired minimum phase margin

The first two variables are based on the circuit realisation of the triangular carrier and

the current sensing, which would be based on the desired ratings of the system and how

the signals are internally represented in the controller. Closed loop bandwidth specifies

the response speed for error correction, which for the purposes of this research assumes

the recommendation [20] of one sixth of the desired switching frequency is acceptable.

The phase margin is related to the transient response performance and the stability of the

linear control. However, an exception to recommendations [20] was a decision to alter the

minimum phase margin requirement to 45 instead of the recommended “rule of thumb”

of 60 , so as to improve the performance of the PI control. Given that phase margin

serves as a measure of control stability, it would be ill-advised to reduced phase margin

too much. 45 was chosen as it is generally recognised as the minimum phase margin for

stable control design, although there is some variation amongst texts [21].

An inherent issue with the integral component of the control method would be its

susceptibility to transient situations where it can potentially result in large overshoots and

longer settling times. Thus to enhance the performance of this control method apart from

adjusting the phase margin, it is standard practice to incorporate some form of antiwindup

mechanism that will help reduce this overshoot and generally improves settling time as

well. For the purposes of this work, a very simple antiwindup strategy was adopted and

simply involves clamping the magnitude of the integral component within certain bounds.

The bounds are chosen such that doing so restrains the accumulation of error to a certain

size, which results in a more limited overshoot than an unrestrained integral component.

22


2.3.2 Standard Hysteresis Current Control

Standard hysteresis is a simple non-linear control method where the current is “bounced”

between two fixed bands defined equidistant from the desired reference current (i.e. lower-

band = iref − h and upper-band = iref + h, where h is the equidistant hysteresis band

offset from iref ). A conceptually equivalent definition is to bounce the current difference

signal (idif ) between equidistant h bands about zero idif . Although the upper and lower

bands do not have to be symmetrical, there are at least two reasons behind the choice of

equidistant h-bands:

1. to guarantee that it will approach ZACE as it is a feature of the other non-linear

control methods considered here; and

2. as opposed to two bands of different magnitudes, equidistant bands can effectively

reduce the number of input parameters required for Hysteresis operation by one

(thus a potential cost saving for an analogue implementation)

Thus for the purposes of this work, only the version of Hysteresis using equidistant bands is

considered. An initial estimator for the size of these bands can be calculated by rearrang-

ing equations for determining the average switching frequency of the Hysteresis control.

Equations 2.4, 2.5 and 2.6 are the set of formulas from [22] that describe this relationship.

Due to inherent system losses, it is then possible to further fine-tune the bands such that

the average switching frequency is actually achieved.

fsw,ave = fsw,max

(1− k2

2

)(2.4)

fsw,max =VDC4hL

(2.5)

k =VAC,1VDC

(2.6)

Although there is an expected maximum switching frequency for hysteresis, it will

inherently not maintain a fixed switching frequency like the other methods. As a conse-

quence of the variable switching frequency nature, it can sometimes be difficult to design

an appropriate filter to remove all the switching harmonic content. For example, due

to the wider spectrum of frequencies generated, the filter would have to be larger to be

able to reject the lower switching frequencies and leads to an undesirable increase in the

component costs. Despite this fact, hysteresis is still a very popular control method due

to its simplistic nature, guaranteed stability and relaxed controllability region.

23


An advantage of the simplicity of the Hysteresis control is that the components required

to build it tends to be very minimalistic in comparison to most other methods — in terms

of analogue circuitry it often only requires the following: band generation, comparator

and latching logic. This is depicted in the Hysteresis circuit schematic, Figure A.3, found

in Appendix A.1. Since it does not rely on modelling the full system, it means the control

should be able to handle either the inverter or the APF scenario without much redesign

(if any). The only issue that will likely require adjustment between its use in the pure

inverter application compared to the APF application is the polarity of the switch output

logic, which most discrete latch IC devices should already cater for (i.e. it should have

both the inverted and non-inverted outputs).

One major reason why Hysteresis is often considered a very good control method for

APF applications is because of the high control bandwidth — allowing it to very quickly

handle transient situations commonly required for APF applications. However, this means

that it is entirely possible for noise on the current measurement signal to cause slightly

earlier switching than if the true current was presented to the comparator (see Figure 2.9).

This means that Hysteresis may have an even higher average switching frequency than

the intended design, but this is generally not much of an issue because often a low-pass

filter is used to remove the switching frequency content at the output anyway.

imeas

iref

−h

h

imeas

−h

h

iref

With noise

Without noise

Figure 2.9: Potential for noise to cause earlier switching in Hysteresis current control

24


2.3.3 Parabola Current Control

There are various methods proposed to combine the benefits of Hysteresis current control

and fixed switching frequency (or at least near fixed switching frequency). Parabola cur-

rent control [23] is one such method that attempts to gain the transient performance of

Hysteresis whilst approaching near fixed switching frequency. Originally, the derivation

of Parabola current control was based on a single-phase half-bridge inverter as shown in

Figure 2.10 directly from [23]. To start with, the basics behind Parabola current control

will be described under this 1-ph HB inverter topology until it is appropriate to show how

it is adapted for the single-phase full-bridge topology as used throughout this work.

Figure 2.10: 1-ph HB CC-VSI topology assumed in Parabola current control derivations

There are two versions of the Parabola current control method proposed in [23], but

only the improved version will be discussed here — i.e. the double parabolic bands version

as per Figure 2.11 directly from [23]. As can be seen, it targets near fixed switching

frequency by generating bands that vary through time. These bands are based on a

periodic parabola function, where the band resets and flips over to the opposite polarity

whenever the current error signal hits the band of appropriate polarity. Generating the

periodic parabola function relies on a very basic model of the system, where the relevant

system parameters for performing Parabola current control are as follows (and are reflected

by both Figures 2.10 and 2.11):

• Vp: upper voltage of the DC bus;

• Vn: lower voltage of the DC bus;

• L: line inductances;

• T : target switching period; and

• ∆i(t): equivalent to the current difference signal (idif )

25


Figure 2.11: Parabola current control behaviour with double parabolic bands

These parameters can be combined into a single input parameter for producing the

periodic parabola function as described in Equation 2.7 and in practice, the author of the

paper suggests it can be deemed constant (see [23] for detailed derivations where the other

variables shown in Figures 2.10 and 2.11 are necessarily defined). Since a single-phase full-

bridge VSI is the topology of interest in this work, the adaptation of the Parabola current

control for controlling this topology is pretty simple. The parabola function generator

just needs to be given an input as defined in Equation 2.8. And in this work it considered

constant as well (i.e. no online parameter updates).

ParabolaFnGeninput =(Vp − Vn) · T

L(2.7)

ParabolaFnGeninput =2 · VDC · T

L(2.8)

An important note realised through simulation is that we must include a restriction

that the parabola function generator never goes below some nominal value (e.g. 0 V) if

we are using ideal integrators and the latch based implementation given in [23]. Not in-

cluding this meant that the simulated system may become uncontrollable when transients

are encountered, since the parabola function could move quadratically away from the er-

ror signal (towards either positive infinity or negative infinity) and as such the parabola

band will never be hit again. This is inherently dealt with in typical real-world analogue

implementation — i.e. op-amp outputs are not able to go beyond the supply voltage rails.

Also, in the suggested implementations there is an edge detector circuit (ED), which may

be subject to further consideration because it represents an opportunity to filter out spuri-

ous noise that would cause undesirable switching. Using an analogue-based edge detector

circuit, the RC time constant can be set to help reduce the sensitivity of the control to

noise.

26


Figure 2.12 depicts one of the suggested implementation configurations in [23] and it

should be noted that the author seems to have intentionally suggested designs that produce

balanced upper and lower bands by sharing the same parabolic function generator. From

inspection, the double bands shown in Figure 2.11 are actually implemented using a single

parabola-function generator (PG) block that is always positive, but is also inverted for the

negative band and surrounded with the appropriate logic to make the appropriate reset

and comparison depending on the direction of error correction. However, the proposed

analogue circuits may have a slight issue due requirements for integrators to reset to zero.

Resetting to zero in analogue circuits can sometimes be difficult since the reset needs to

be held for sufficient time (dictated by the RC time constant) and there is the potential

for a residual value to remain/redevelop after the reset. This brings up the question of

whether there is another way to achieve the same control without such potential issues

and perhaps this is where a digital implementation may help (e.g. digital integrators that

can reset to zero accurately and quickly).

Figure 2.12: One of the suggested circuits for implementing Parabola current control

If we are to stick with analogue circuits, one possibility is to compromise the equivalence

between the upper and lower bands by separately generating these bands. The concept is

to have the appropriate band active, whilst resetting the inactive band and holding it to

zero and switching between them at each switching instance. Thus whenever the measured

current hits the active band it switches around the active band, activating the previously

inactive band by releasing it from zero and the previously active band is inactivated by

clamping it to zero. The reason for this configuration is to remove the edge detector

circuit that may have imposed bandwidth limitations in the suggested implementations,

whilst still utilising only a single comparator for switch output (i.e. an output latch is also

unnecessary). However, since this configuration would imply high bandwidth it might also

lose a certain amount of inherent noise filtering from the edge detector. Another option is

to investigate a digital implementation — something probably worth exploring in future

research.

Also as a result of the periodic parabola band timing, this control method will inher-

27


ently attempt to switch at the target switching frequency. Unlike Hysteresis it becomes

possible that Parabola current control may not maintain the fully “on” or fully “off” duty-

cycle for more than one switching period under some transient circumstances. Combined

with blanking time delay means that Parabola current control may not always achieve

the intended bounds and thus would contribute to slightly longer settling time before the

desired reference current is reached.

2.3.4 Ramptime Current Control

Ramptime current control is a non-linear near fixed switching frequency control method

and does not rely on either hysteresis or a clock. Although the concepts behind how

Ramptime works is not very difficult to understand, it is still probably the most complex

algorithm to implement out of the methods discussed previously. That said, Ramptime

does have a quite unique benefit in that it does not really need any system parameters

except the target switching frequency. Thus it will function correctly as long as the line

inductor is sized appropriately such that the current ripple is not too large or too small.

Simply put, this method relies only on the current difference signal (idif ) where the time

between the last switching instance and the zero current error crossing (polarity change

of idif ) is observed to determine the switching instance to use for the next half-cycle with

the aim of observing a zero error crossing where it expects to achieve zero average current

error as well as the target switching frequency. This obviously leads to Ramptime current

control featuring ZACE capabilities [17, 24, 25].

Several versions of the Ramptime control strategy do exist, so it would be important

to state that this work only considers the polarised version with these features:

• polarised algorithm where the next switching instant uses the previous same-side

excursion instead of the immediately previous opposite-side excursion;

• bipolar switching;

• switching noise filtering; and

• transient re-initialisation.

Other versions (including the original Ramptime) are not considered in this work, but

if interested the reader is referred to the full-literature [17]. To explain the Ramptime

concepts in general it is important to define some of the variables involved in the control

strategy — Figure 2.13 depicts the timing variables that all Ramptime control strategies

are based on. Also note the use following notations:

• asterisk (*): the variable is a desired/targeted value

28


• caret (∧): the variable is a measured value

• hash (#): the variable is a calculated value

imeas

iref

Tar1 Taf1

Tbf1 Tbr1

Tar2 Taf2

Tbf2 Tbr2

Figure 2.13: Error signal with relevant Ramptime timing variables labelled

where:

• Ta: amount of time the error signal spent above the zero within a switching period

• Tar: amount of time within Ta where the error signal is rising

• Taf : amount of time within Ta where the error signal is falling

• Tb: amount of time the error signal spent below the zero within a switching period

• Tbr: amount of time within Tb where the error signal is rising

• Tbf : amount of time within Tb where the error signal is falling

To maintain ZACE, Ramptime aims for the amount of time spent above the current

reference to be equal to the amount of time spent below the current reference. And for near

fixed switching frequency, both should be equal to half the desired switching period. Both

aspects are described in Equation 2.9. Since the polarised version of Ramptime is used in

this work, the same-sided information from previous switching period is used to determine

the next switching instance — as expressed in Equations 2.10 and 2.11. The important

reason why the polarised version is used is so that the excursion times will incorporate any

29


switching delays and therefore improves the error correction mechanism over the original

opposite-sided version. Also, notice that none of these relationships require anything to do

with the magnitude of the error signal. Thus as long as the error signal is measured and, if

necessary, scaled appropriately for the accurate discernability of the zero-error crossings,

then the Ramptime algorithm should work (i.e. the binary state of whether the error

signal is above or below zero are accurately reflected time-wise).

T ∗a = T ∗b =T ∗sw2

(2.9)

T#

ar,2 =

(T

∧ar,1

T∧a,1

)(T ∗sw2

)(2.10)

T#

bf,2 =

(T

∧bf,1

T∧b,1

)(T ∗sw2

)(2.11)

30


irip

Figure 2.14: Polarised Ramptime current control block diagram

31


The block diagram for polarised Ramptime shown in Figure 2.14 is one of the possible

ways to implement this algorithm. For the purposes of this work, only a general explana-

tion of its operation will be offered here, since it is not within the scope of this work to

re-explain the detailed derivations of the Ramptime control implementation. Please con-

sult [17] (particularly Chapters 5 and 6) should further explanation be required. Whilst the

original prototype of Ramptime was implemented with analogue circuitry, later develop-

ments would turn to a digital (FPGA) implementation of Ramptime. Of course, a digital

implementation would not look exactly the same, but it should still function the same

because it is based on the same principles. In later discussions regarding experimental

setups, the digital FPGA implementation is used.

Referring to Figure 2.14, the first comparator accepting the error signal input, ie, will

simply turn this into a logical “high” (value of 1) for positive polarity or “low” (value

of 0) for negative polarity. The adjacent logic and latch provides some additional noise

tolerance by helping to ignore any spurious zero-error crossings caused by noise in the error

signal. The resulting error polarity signal in combination with the switch output signal

(s) is used to initialise and update the timing integrators, with all integrators having time

constants of T ∗sw/2. Notice that the “above” excursion timing pathways are based on a

positive error polarity signal and the “below” excursion timing pathways are based on

a negative error polarity signal. Thus the “above” and “below” paths for the first-stage

integrators operate on the opposite edges of the error polarity signal.

The TAZ and TBZ sample-and-hold blocks are triggered before the reset of the first-

stage integrator takes place (when the error signal changes polarity) to allow the previous

current slope values to be available for the determination of the next same-sided switching

instance. Likewise the TAR and TBF sample-and-hold blocks are triggered to hold the

previous values corresponding to Tar and Tbf respectively. The limiters after sample-and-

hold blocks are set up to ensure correct operation of the algorithm in the case when none of

the integrators are initialised and also for handling transient situations. The second-stage

comparators thus produce the actual “above” and “below” ramps based on the previously

held ramp-rates, with logic to ensure that each operates at opposite intervals corresponding

to the positive and negative portions of the error polarity signal respectively.

The output ramps can be summed because only ever one path is non-zero whilst the

other path is zero and the result is presented to the negative input of the switch output

comparator. Similarly, there is logic to ensure that only one value of either Tar or Tbf

are ever presented to the summer for the excursion time going to the positive input of

the switch output comparator. Thus the comparator for the switch output is always

making an appropriate comparison between the active ramp and excursion timing value

for determining the next switching instance.

Since the algorithm relies heavily on timing, it is critical that the sensing of the current

32


is fast and accurate. It is recommended that the sensing delay not exceed 1% of the

switching period [17]. Also relevant are that there be minimal delays in computing the

next switching instance to be able to achieve high control bandwidth. For this purpose, the

implementation of the Ramptime algorithm converts the divisions into ramp comparisons

instead, which can be implemented in the form of integrators or counters. Finally the

tuning of Ramptime will depend on the expected VDC and the AC load magnitude, the size

of inductor and the target switching frequency together with the following considerations:

• Ramptime controllability will be impacted if the ripple envelope is too small for the

zero-error crossings to be accurately determined;

• Of course, the current ripple should not be excessively large either (i.e. it should

be relatively easy to see the underlying current reference from inspection), as that

would imply a large switching frequency component in the output.

Numerous works have shown the use of Ramptime current control method in the shunt

APF configuration [9, 14, 26].

33


34

Chapter 3

Analysing the Performance of

Existing Current Controls for

Voltage Source Inverters

The main contribution by this work consist of a reasonably comprehensive analysis and

comparison of existing current control methods suitable for the single-phase full-bridge

inverter topology of interest. The desirable characteristics previously discussed will form

the basis for assessing the performance of existing current control methods. Thus this

chapter aims to investigate the level of fidelity achieved by some existing current control

methods and allows us to recognise:

1. the strengths and weakness of each method; and

2. where improvements could be made.

Also another fundamental contribution from this work is in laying the foundations for

an objective way to determining how well a current control method meets the desirable

characteristics criteria under varying scenarios. The idea behind these scenarios would

be to stress the control method so that the strengths and weaknesses are easily identi-

fiable/measurable, then it should become easier to propose potential improvements and

demonstrate their effectiveness. Some similar work in comparing current control methods

has been done in the past [5, 18], but not exactly with the purpose of gaining insight into

where improvements might possibly be made.

35

3.1. BENCHMARKING PERFORMANCE

3.1 Benchmarking Performance

Assuming that we are interested in fair comparisons, the best performance achievable by

each method should be considered for analysis and comparison. A common issue with

many publications presenting new control methods is the narrowness of their comparisons

with existing methods, where most only attempt to compare their scheme against a single

established method. I believe this may correspond to a barrier to expertise and under-

standably so because it takes considerable effort to become knowledgeable enough to fully

optimise the various control methods in existence. Still, unfortunately this means it is

often difficult to be able to conclude how well it would compare against other methods

not covered in their work. Hence the aim of this section is to reduce this barrier.

Two approaches to reducing this barrier are taken — one is to offer some implementa-

tion guidance and the other is to discuss and promote the use of a standard benchmarking

platform. Although implementation guidance is offered only with respect to personal ex-

perience, it is deemed that passing on this knowledge is an appropriate and important

step for any future works to continue from where this work left off. And the reasons for

using a benchmark approach are due to the following benefits:

1. Permits others to re-validate results.

2. Allow unbiased comparisons between different current control methods suitable for

this particular topology.

3. Reduce effort in comparison analysis, since it would not be necessary to re-perform

the same experiment for already validated results.

4. Improve transferability of the results, where useful conclusions can be drawn from

comparing existing benchmark results with newly benchmarked results.

5. Incorporate measures universally desired across various applications and also mea-

sures that are more application specific to provide indicators of suitability under

these specific applications.

These matters will be explored through simulation, because this investigation approach

becomes quite cumbersome to pursue via physical experiments. This is mainly because

a physical experimental setup will involve both considerable costs and time to acquire

the required components and assemble the system and especially allowing for high con-

figurability to carry out various test conditions. It it is hoped that the results from these

simulations would help isolate particular areas of interest, such that in future it would be

possible to replicate the more interesting simulation results via hardware experiments (as

opposed to reproducing results that showed no significance in simulation).

36

ANALYSING THE PERFORMANCE OF EXISTING CURRENT CONTROLS FORVOLTAGE SOURCE INVERTERS

3.1.1 Current Reference Waveform

There are two scenarios which will be considered important for measuring the fidelity of

a control and these are the steady-state and transient response. Steady-state operation

is considered to be when the current reference is sinusoidal and in-phase with the AC

voltage with a magnitude of the typical current rating defined in Table 3.1. To consider

performance under transients, it is proposed that a special transient waveform be used.

This special transient waveform is constructed as a piecewise function of two sinusoids

with differing amplitudes, as defined in Equation 3.1.

f(t) =

sin(2π f t) if 0 < t ≤ π2

0.7 sin(2π f t) if π2 < t ≤ 3π

2

sin(2π f t) if 3π2 < t ≤ 2π

(3.1)

Notes regarding this special transient waveform:

1. one is full magnitude of the typical current and the other is 70 % of the typical

current;

2. each share 50 % of the line cycle;

3. transient occurs at 90 and 270 (i.e. the peaks and troughs);

4. is expected to have even harmonics of the fundamental and can be imagined to

correspond to a sudden increase in load every half-cycle.

Initially, this special transient current reference was intended to be in-phase with the

voltage as a way to test the transient responses at the most critical di/dt current slope,

i.e. given the reference is in-phase with the voltage then the slowest upwards di/dt rate

is at 90 and fastest at 270 . The work presented in the first set of simulations will be

based on this (as per [27]).

However, putting this transient current reference into the control system will bring

an additional consideration. If line voltage and current are in phase, then at the time

when the current transients occur, the line inductor voltage differentials are under opposite

conditions, which at first glance might seem alright. Yet due to the unbalanced slope rates,

this may give opportunity for saturation of magnetics (DC offsets) in a realistic system.

As it is intended that the benchmark setup also be applicable in practice, it would be

advisable to resolve this before going to physical experiments. So with the intention of

still using the transient reference, one solution is to phase-shift the line current by 90

relative to the line voltage, which results in the current slopes to balance in both upwards

and downwards direction around the transient regions. The next matter to consider is

37


in which direction such a shift should be made — should the output current lead the

voltage, where the inverter would appear like an inductor? Or should output current lag

the voltage, where the inverter would appear like a capacitor?

For hardware experimentation, it is proposed that the phase-shift is such that the

inverter looks capacitive to the load (i.e. current lags the voltage from the perspective

of the inverter). This corresponds to a worst-case scenario for controllability due to the

added inductor voltage component in the fundamental line voltage and thus reduced con-

trollability margin. Should no design changes be made the resulting system may become

uncontrollable in situations where the inverter can no longer drive the appropriate cur-

rents in the inductor, similar to what is shown in Figure 3.1. Although the control will be

designed such that the minimum control margin is fulfilled, my hypothesis is that such a

setup will stress each current control under investigation and thus potentially exacerbate

any performance issues related to each control method.

Figure 3.1: Inductive load where uncontrollable region becomes apparent

The respective current references are depicted in Figure 3.2.0 5 10 15 20

-2

-1

0

1

2

Time (ms)

Cur

rent

(A

)

Steady-stateTransient

Figure 3.2: Steady-state and the transient waveforms for current reference (per unitbased)

38


3.1.2 Developing Appropriate Measures of Control Fidelity

The primary motivation behind benchmarking is to determine the performance for each

current control. So how should each current control method be measured in an objective

manner such that it offers a fair comparison? A typical measure as used in power elec-

tronics and other fields is total harmonic distortion or THD of the line current i. One

form of its definition is presented in Equation 3.2, where both top and bottom consistently

use the RMS of each component (alternatively it is possible for the top and bottom to

consistently use the absolute magnitude of each component). To determine the harmonic

components of a measured signal in discrete time, an algorithm known as Fast Fourier

Transform (FFT) is often used since it was specifically designed and implemented for

computational efficiency on computers. Importantly, the application of FFT requires the

appropriate windowing of data such that it captures the waveform at the expected funda-

mental frequency. Since the FFT algorithm assumes that this windowed waveform repeats

itself infinitely on both sides of the window, then there are two issues:

1. the wrong window size will cause harmonic components to be computed for the

wrong fundamental frequency; and

2. the expected harmonic components (e.g. third harmonics in switching) will not be

as high as they should be

of which both are issues related to the “leakage” of the harmonic components to adjacent

frequencies.

THDi =

√√√√∞∑

n=2

I2n,rms

I1,rms(3.2)

where,

• THDi: percentage of distortion known as total harmonic distortion

• In,rms: rms value of the nth harmonic component in line current;

• I1,rms: rms value of the fundamental component in line current

By definition THD measures the amount of harmonic distortion as a proportion of the

fundamental magnitude and the aim would be for the system to be able to minimise THD

towards zero. It is relatively easy to see that THD would be reasonably tolerant to slight

FFT windowing inaccuracies since:

39


1. it is assumed the main fundamental component is not significantly distorted by

the combined effects of a “false” fundamental and “leakage” of the fundamental

component; and

2. the measure would take into consideration all harmonic components anyway, mean-

ing the non-fundamental components should still sum up to about the same value

even when there is “leakage”

However, what THD does not tell us is how well the fundamental component matches

that of the desired fundamental, such as how accurately the desired fundamental magni-

tude and fundamental frequency are outputted. To determine the absolute magnitude of

harmonic components it becomes necessary to ensure that the FFT is performed over the

correct window.

Here follows a list of measures to be considered in the analysis, which are designed

to fill-in the information gaps that THD alone can not provide. Note that I define ie =

(iline− iref ). Nomenclature-wise the Ien notation represents the magnitude component at

the nth harmonic from the FFT of the lower-case variable ie (so similarly for Irefn).

1. First consider a measure of distortion previously used in [18] for comparing current

control methods. This is restated as Equation 3.3 sake of convenience, but also

renamed to %Error due to it being the more obvious name by looking at the def-

inition. By definition it will capture any errors (distortions) of the generated line

current from the desired reference, which mean it takes into account issues such

as: offsets, scaling and phase shifts (issues that THD does not capture). Although

Equation 3.3 is all encompassing, this measure shall not used alone because it does

not distinguish between the various sources of error.

%Error =100

Iref,rms

√√√√ 1

T

∫

T

(iline − iref )2 dt (3.3)

2. Phase-shift between the actual current and the reference current is always of interest.

Using MATLAB we attempt a fit of the data for the generated current to a sinusoidal

function as stated in Equation 3.4, but means that this measure is only applicable for

a steady-state reference current and not the transient reference current waveform.

Observe that a positive φ would represent a phase lag in the generated current to

the reference.

Find φ via a curve fit of iline to:

A sin (2πf1t− φ) (3.4)

40


3. An error signal deviation (ESD) measure is proposed Equation 3.5 to indicate the

low-frequency deviations in the error signal ie from zero via FFT. Unlike Equation

3.3, ESD should not incorporate distortions from the switching frequency since it

only includes the fundamental up to the 21st harmonic. Thus ESD should be more

independent of whether the control method is of fixed or variable switching frequency.

Also when the fundamental component of the line current is in-phase and of the same

magnitude as the steady-state current reference, then ESD becomes equivalent to

a constrained (low-order) line current THD. This is because Iref1,rms will have the

same value as Iline1,rms and so Ie1,rms is zero.

ESDi =

√√√√21∑

n=1

I2en,rms

Iref1,rms(3.5)

4. In attempt to combine Distortion and ESD, reference-based low-order harmonics

(RLH ) is another proposed measure as defined in Equation 3.6 that ignores switch-

ing content and should indicate how precise the current control technique shapes the

controlled current to mimic the reference signal. Similar to ESD, this relies on the de-

sired reference fundamental component (Iref1,rms) rather than the line fundamental

component.

RLHi =

√√√√21∑

n=2

I2linen,rms

Iref1,rms(3.6)

5. Lower-order harmonic distortion (LHD) is defined in Equation 3.7 is basically the

bounded version of THDi that only includes up to the 21st harmonic. The purpose

of this harmonic measure is to be like THDi in showing harmonic content as a

proportion of the measure fundamental current, but ignore the higher frequencies

(i.e. where switching occurs).

LHDi =

√√√√21∑

n=2

I2linen,rms

Iline1,rms(3.7)

6. Reference-based total harmonic distortion (RTH ) defined in Equation 3.8 is basically

the same as THDi, but the denominator is replaced with the fundamental reference

magnitude (normally it would be the measured fundamental line magnitude). Notice

that THDi measures the amount of harmonics relative to the measured fundamen-

tal, which means it is entirely possible for there to be errors in the fundamental

that allows the true harmonic content to be distorted by this error in fundamental.

However, using the reference fundamental as the denominator ensures any error in

41

3.2. COMPUTER ASSISTED ANALYSIS

the fundamental (between the measured and the reference) are acknowledged. Thus

the measure should remain a uniform measure of harmonic content no matter which

control method or scenario.

RTHi =

√√√√∞∑

n=2

I2linen,rms

Iref1,rms(3.8)

7. ∆I1 defined in Equation 3.9 is a measure that captures an error in the fundamental

magnitude of the line by comparing it against the fundamental magnitude of the

reference and then turning it into a proportion of the reference magnitude.

∆I1 =|Iline1 − Iref1|Iref1,rms

(3.9)

3.2 Computer Assisted Analysis

There are many software packages today that allow us to design and explore control

methods. Also, it can be used to compute metrics of interest to help us assess control

systems and more specifically power electronic systems.

For design insight and power electronic systems simulation, PSIM by PowerSim was

used. Alternative packages such as PSPICE or Simulink (part of MATLAB) would prob-

ably be just as capable, but PSIM was preferred for its sheer simplicity — which means

less time to setup and simulate new systems from scratch. The primary software package

used for post-experimental or post-simulation analysis and visualisation is MATLAB by

Mathworks. For example, writing MATLAB scripts to assist in streamlining this analysis

process was a significant stage in this work and the reasons for choosing to build scripts

are:

• to reduce manual efforts especially when the same process is applied to multiple data

sets;

• to improve consistency of analysis and reduce chance of introducing human error/bias

(e.g. data windowing via consistently computed thresholds versus judgement by

human-eye); and

• scripts could be re-used with minor changes for different directory structures (or no

changes if the same directory structures are maintained).

The code listings for major components of the MATLAB scripts implementing the

calculation described in Section 3.1.2 can be found in Appendix A.2.1. The complete

42


package will be stored onto the lab’s server to be available for future use.

3.3 Simulation-based Analysis with Practical Considerations

Many practical considerations may alter the ideal performance of a particular current con-

trol method applied to voltage source inverters. Such real-world conditions may include:

blanking time (also known as dead-time), variation of system parameters (e.g. DC bus

fluctuations) and noise (e.g. current measurement for feedback). By simulating particular

levels of such non-ideal characteristics as a benchmark, each control technique can be as-

sessed to provide a designer some guidance as to the susceptibility of a particular control

method under non-ideal conditions.

Thus to pursue this benchmarking concept, the proposed analysis approach would be to

investigate each of the scenarios for each current control methods. Their purpose would to

be identify which non-ideal conditions would probably require additional design attention

to achieve the desired level of performance. These scenarios will be described in the

sections that follow and from the results it may turn out that only specific current control

methods are affected. Extending from previous analysis into current control VSI topology

(e.g. [3, 18]), I shall re-examine standard PI triangular carrier and standard hysteresis as

a basis for comparing with near fixed-switching frequency hysteresis via Parabola Current

Control [23] and Ramptime [17, 24].

3.3.1 Base Case under Ideal Assumptions

To establish a basis of comparison, I will start by explaining the base case simulation

configuration by applying ideal assumptions. Although not physically realisable, an ideal

system permits the very limits of the system to be pushed. For example, in an ideal system

the controllability margin could be pushed to approach zero (i.e. minimum required to

maintain controllability), which is one of the DC level scenarios. However, in anticipation

of the non-ideal systems, it is typical to design for greater tolerances and additional safety

margins. For this reason, a DC bus of 106 % of the AC fundamental is chosen (under unity

power factor). Choices such as switching frequency and inductance for a current ripple

size are made to reasonably reflect what might be expected in practice.

For a realisable inductor, the desired ratings (inductance, voltages, currents, etc) were

put into a magnetics manufacture’s inductor design software, which returned an AL toler-

ance of ±5 % inductance core material and DC resistance of about 104mΩ (i.e. excludes

skin effect and proximity effect). Note that AL is an industry standard unit of measure for

manufacture of inductors and is equal to nanohenries per turn squared (nH/N2) [28]. The

43

3.3. SIMULATION-BASED ANALYSIS WITH PRACTICAL CONSIDERATIONS

inductor tolerance range leads to the inductance parameter dependency test case and the

DC resistance is incorporated as an inductance resistance (RL) in the system model. Also

note that although this system was initially designed in nominal terms, simulations will

be conducted in the per-unit scale (i.e. 1 V RMS amd 1 A RMS output, 0.125 mH filter,

etc). Thus subsequent discussions use per-unit scaled parameters, especially in regards to

test setups and control design.

Parameter Nominal Per-unit

Output AC Voltage (Vo) * 240 V RMS 1 pu

Typical Output Current * 10 A RMS 1 pu

Line Frequency (f1) * 50 Hz 1 pu

Target Switching Frequency (fsw)(if applicable)

20 kHz 400 pu

DC Bus Voltage (VDC) 360 V 1.5 pu

Filter Inductance (L) 3 mH 39.27 mpu

Inductance ESR (RL) 0.104 Ω 4.333 mpu

Current Reference Phase Lag (phaselag of iref to Vo)

90 0 pu

Blanking Time (ideal switches) 0 s 0 pu

Table 3.1: Ideal System Parameters for 20 kHz

*Base units from which derived base units are Zbase = Vbase/Ibase and Lbase = Zbase/(2πf1)

3.3.2 Blanking Time Effects

Blanking time (also known as dead-time) is simply the “on”-delay required for avoiding

shoot-through in complementary switching and by introducing this delay it alters the

realised PWM signal, which may have detrimental effects on particular control strategies.

In simulation I shall consider the standard and simplest implementation that modifies the

original switching control signals, such that at each switch transition the signal for the

“on” switch is delayed by this time. A range of delays are considered (see Table 3.2)

as switching devices with larger ratings tend to be slower to switch and thus may imply

certain methods are less suitable for high-power applications.

Delay Nominal

1 % of switching period 0.5µs



Table 3.2: Blanking Delay For 20 kHz

Although strategies such as [29–31] exist for compensating blanking time effects, they

are not necessarily compatible with the control method used (e.g. hysteretic methods with-

44


out pre-determined switching instances will be unlikely to benefit from such compensation

strategies) and their implementation obviously adds to control complexity.

3.3.3 DC Level Requirements for Controllability

This test recognises that the DC source is not necessarily an ideal source, so if VDC

drops then there may be concerns regarding controllability. From the ideal case notice

that the specified DC bus voltage provides an additional margin of 6 % above the peak

AC amplitude (i.e. VDC is 106 % of the peak amplitude of Vo) to ensure controllability,

but the margin is not excessively large either because it is a trade-off against reducing

switching loss. In order to evaluate the effects of a DC voltage level drop, each control

method is designed for the ideal case and its performance assessed for a shrinking margin

that approaches the very bounds of controllability - first down to 3 % margin, then even

to 0 % margin.

3.3.4 Robustness to DC Bus Fluctuation

An ideal DC bus would provide a constant voltage, but in reality this may not be so true,

as even with a regulating capacitor the DC bus voltage may be fluctuating with time. Thus

I shall simulate this fluctuation on top of the ideal DC bus voltage, which is represented by

Vrip (as depicted in Figure 3.3). To refrain from pushing beyond the controllable region,

the constraint of VDC > |VAC | must be met. Thus Vrip shall be defined as a sinusoid with

amplitude of about 5% pu (i.e. 17 V) at twice the fundamental line frequency.

VDC

Vrip

Figure 3.3: DC bus fluctuation model

The purpose of analysing the robustness to DC bus fluctuations is to assess how well

each current control method maintains similar levels of performance to the ideal case once

the DC ripple is introduced. Perhaps these results may suggest that for certain controls

only minimal DC bus regulation is required, which implies a potential cost saving (i.e. if

a smaller regulating capacitor could be used across the bus).

45

3.3. SIMULATION-BASED ANALYSIS WITH PRACTICAL CONSIDERATIONS

3.3.5 Inductance Parameter Dependency

As with any component, the ability to produce an ideal component value is often limited

to a particular tolerance range. Thus two inductance values corresponding to the ±5 %

inductance tolerance range stated previously shall be tested (i.e. L(1 − 0.05) and L(1 +

0.05)). The aim of this test is to assess the sensitivity of the control to the common issue

of parameter mismatch and results may suggest a need for additional controller tunability

in practice.

3.3.6 Behaviour from Feedback Inaccuracies (Noise and Lag)

Closed-loop current control methods all require feedback from the circuit to remove error.

However, such feedback may be subject to signal noise, measurement noise (e.g. ADC

quantisation error) or signal-to-feedback lag (e.g. ADC conversion time or sensor lag).

For this simulation test, signal noise will be injected by adding a random source to the

normal feedback imeas and signal-to-feedback lag via time delay block of the imeas signal.

Signal noise here is simulated as a uniform distributed random variable between ±0.1 A

(i.e. 0.2Apk−pk centred about 0). Time delay shall be set at 1.02µs based on current

measurement sensor lag specified in a datasheet for a suitable closed loop hall-effect sensor

device (1µs) plus additional propagation delay through the control (assumed to be 20 ns).

3.3.7 All Conditions from 3.3.1 to 3.3.6 are Combined

Combining all the previous non-ideal characteristics into the same scenario will offer an

all-round test that might reasonably correspond to implementing the system in the real-

world. For the cases where varied levels of the non-ideal characteristic are tested (i.e.

not simply the binary state of having or not having the non-ideal characteristic), then a

specific level will be chosen such that it would be towards minimising the potential affects

of that non-ideal characteristic. Two examples are the:

• inductance, where the larger inductance is chosen to minimise the current ripple;

and

• blanking time, where the smallest level considered (1% of switching period) to min-

imise its impact on the switching instance (but still assumed to be suitable for the

gating devices intended for the system)

46



Blanking Time (1 % of 1/fsw) 0.5µs 25µpu

Dc Bus Ripple Voltage (Vrip) (@100Hz)

17 V (≈ 12.02 V RMS) 50.09mpu

Filter Inductance (L) 3.15mH 41.23mpu

Feedback (Random) Noise (In) 0.2Apk−pk (≈ 0.577 A RMS) 5.774mpu

Feedback Delay 1.02µs 51µpu

Table 3.3: Combined Non-Ideal Parameters For 20 kHz System

3.3.8 Lower Target Switching Frequency

For a more demanding test, reconsider the test cases 3.3.1 to 3.3.7 with a reduced target

switching frequency of 5 kHz. The adjusted 5 kHz system should correspond to higher

power ratings (e.g. inductance and blanking time would be multiplied by 4). Table 3.4

summarises the changes to the ideal system parameters.


Target Switching Frequency (fsw)(if applicable)

5 kHz 100 pu

Filter Inductance (L) 12 mH 0.1571 pu

Inductance ESR (RL)** 0.416 Ω 17.33 mpu

Table 3.4: Adjusted Ideal System Paramters For 5 kHz

3.3.9 Adjusting the Control Methods for Analysis

For fixed switching frequency methods, simply choosing the target switching frequency to

match will allow these methods to be compared fairly. However, this raises a question as to

how to treat variable switching frequency methods like Hysteresis. In hopes of unbiased

comparison of the various current control techniques, it is proposed that each control

method is necessarily tuned/adjusted to produce a similar amount of switching per line

cycle — which maintains the same meaning for fixed switching frequency methods. Thus to

meet this requirement, the hysteresis bands of standard Hysteresis current control method

(variable switching frequency) are adjusted to make the number of switching instances

within in a line-cycle similar to what is expected in a fixed switching frequency controls

for ideal configuration (Section 3.3.1).

Normally, when an engineer knows what kind of issues they may encounter in their

system they will try to factor these by including extra “safety margins”. However, in the

scenarios described previously, they will not have such safety margins designed into the

control unless specifically allowed for. The only scenario where re-tuning of the control may

be permitted is when the DC bus voltage is being specifically set (3.3.3). This is because

47

3.4. ACTIVE POWER FILTER AS A BENCHMARK

the choice of higher controllability margin is dedicated at the design stage and many of

the control methods incorporate this parameter as part of normal tuning design. All other

variations will not be factored into re-tuning, because the control methods considered in

this work did not directly include them as part of normal design/tuning procedures. It is

thus the intention to show where attention is required and how much additional margin

might be needed per control method.

3.4 Active Power Filter as a benchmark

As discussed earlier, an APF serves the purpose of cleansing grid power and is of particular

interest as a test platform because it would share many common performance requirements

to those being investigated in the simulation-based benchmark approach. Although not

directly comparable to individual simulation scenarios, the APF requirements should ag-

gregate as if many of the scenarios were being tested at once and this would probably be

more efficient, especially if the purpose was just to measure applied performance (instead

of trying to gain insight into how performance is affected under various conditions). As

such, only the current-related aspects of the active power filtering are considered. This

experiment would basically involve the APF being connected to a distortion generating

load (in our case a diode rectifier load) and the grid. Figure A.1 of the Appendix A.1 is

a schematic for the experimental system that was initially designed and pre-evaluated in

simulation before any physical construction began.

Table 3.5 summarises the initial system parameters used for our APF experiment,

where some design choices came from the convenience of the components already in the lab

and the assumption that the results would still be applicable in a more realistic system.

Notice that this initial APF hardware setup (as per [32]) is considered relatively low-

powered compared to the subsequent work extending from this initial investigation. This

was justified for these reasons:

• this was the first time working on an APF setup and thus it was deemed necessary

to work at lower-power levels to gain familiarity with how the system should behave;

• it would decrease the likelihood of damaging expensive components/equipment and

reduce risk in harming ourselves, especially when testing prototyped control boards;

• since the primary goal of this experiment was to measure current control fidelity, it

was felt that the results from a lower-power APF setup would still remain valid; and

• once we had developed sufficient confidence in our understanding of the system,

moving to higher-power levels should no longer prove discomforting.

48


Parameter Value

Grid/load voltage (vGrid) 27.5 V RMS

Non-linear load current (iLoad) ≈2 A RMS

Line Frequency (f1) 50 Hz

DC Bus Voltage (VDC) 62 V

Switching Frequency (fsw) 16 kHz

Inverter Ripple Inductance (Linv) 1.1 mH

Load Inductance (Lload) 1.1 mH

Grid line inductance (Lgrid) 1.9 mH

Grid AC capacitance (Cgrid) 30µF

DC Bus capacitance (CDC) 10000µF

Load capacitance (Cload) 10000µF

Load resistance (Rload) 22 Ω

Blanking Time (deadtime) 1.9µs

Table 3.5: Initial APF System Parameters

Measuring RTH (defined in in Section 3.1.2) for both imeas and igrid should give an

indication of how well the LC filter works on different current control techniques. A good

current control should deliver imeas that can be filtered out smoothly, which often leads

to the criteria of narrow switching frequency band. Since the switching frequency band

determines the frequencies of current ripple, these would need to be filtered out and having

a narrow switching frequency band simplifies the filter design. Combined with a sufficiently

high switching frequency (i.e. considered far enough from the expected fundamental line

frequency), then this can also reduce filter size and thus cost. Similar works for comparing

current control methods in APF applications have been done [3, 5], but not with the same

APF current control approach described previously in Section 2.1.2.

49

3.4. ACTIVE POWER FILTER AS A BENCHMARK

50

Chapter 4

Results and Discussion

Presented in this chapter are the findings from following the methodology described in

the previous chapter. It was noticed that upon calculation, the previously defined mea-

sures arrived at values that varied slightly with different time windows being considered.

Variation in the results for the steady-state reference waveform could be attributed sim-

ply to noise. However, for the transient reference waveform results, it is plausible that

the slightly more significant variation derives from how optimally the control performed

during the transient region. Also, the time windows for the calculations are assumed to

be consistent with a 50 Hz line cycle because the controls are expected to be well-capable

of maintaining output waveform.

4.1 Results from the Simulation-based Analysis

The simulation resolution is specifically set very high so that it can record detailed in-

formation regarding our switching signals. Thus the simulations use a time-step of 10ns,

which provides 25 times the minimum resolution to discern 1 % blanking time for the

switching signal of 20 kHz. Another way to think about it is that with a 20kHz switching

signal, this simulation resolution would allow for up to 5000 distinct duty-cycles to be

recorded.

Current control Symbol

PI Triangular Carrier

Hysteresis 4Parabola Ramptime ∗

Table 4.1: Legend for Charts

51

4.1. RESULTS FROM THE SIMULATION-BASED ANALYSIS

4.1.1 General Observations

Interestingly, Hysteresis and Parabola both feature similar distortion characteristics under

the steady-state 20 kHz system (consider Figure 4.1). A similar correlation is observed

between PI triangular carrier and Ramptime. This pattern also emerges in the results for

blanking time and feedback inaccuracies of the same steady-state 20 kHz system (discussed

in later sections). Also incorporating all the conditions into the single setup (Section 3.3.7)

shows that the tested conditions do not necessarily result in additive distortion, so some

must cancel another.

4.00

4.50

5.00

5.50

6.00

6.50

Ideal Blanking500ns

DC Ripple Delay &Noise

Higher L All Non-Ideal

Dis

tort

ion

(%)

Figure 4.1: Distortion: Overview of analysis (Steady-state, 20 kHz)

Based on the distortion measure (shown in Figures 4.1, 4.8, 4.10 and 4.11), Hysteresis

was generally able to achieve the best level of distortion (even under all the non-ideal

conditions) and PI is generally the worst. Yet results for both PI and Ramptime show that

they have better robustness to change of system parameters for the given test conditions

with the exception of the DC bus voltage tests.

It was noticed that a multiplier relationship between the 20 kHz and 5 kHz raw phase-

shift values, which pointed towards phase-shift being related to the target switching fre-

quency of the system. Thus the phase-shift results are presented as a ratio of the switching

period (Tsw) (i.e. lag in terms of number of switching cycles) and observed that the tested

effects on phase-shift for both systems were indeed quite consistent (most obvious from

Tables 4.2 and 4.3). Such results imply that phase-shift is predictable and may mean that

there is a way to compensate for it.

It was observed that Hysteresis and Parabola managed the lowest amount of phase-shift

throughout all tests, which is not very surprising because of their hysteretic nature (see

Figures 4.2 and 4.3 and Tables 4.2 and 4.3). It may be noticed that amongst the results

52

RESULTS AND DISCUSSION

φ (ofTsw) Blanking 500ns Blanking 1.5µs Blanking 2.5µs

PI 141% 149% 154%

Hysteresis 1% 2% 3%

Parabola 2% 5% 7%

Ramptime 11% 13% 15%

0% DC margin 3% DC margin 6% DC margin

PI 144% 139% 136%

Hysteresis -2% 0% 0%

Parabola 1% 2% 2%

Ramptime 9% 10% 10%

Delay & Noise Delay only Noise only

PI 136% 136% 135%

Hysteresis 0% 1% 1%

Parabola 4% 4% 0%

Ramptime 10% 9% 11%

Higher L Ideal L Lower L

PI 136% 136% 136%

Hysteresis 0% 0% 0%

Parabola 2% 2% 1%

Ramptime 9% 10% 10%

Table 4.2: Phase-shift: Criteria specific results (Steady-state, 20 kHz)

φ (ofTsw) Blanking 2mus Blanking 6mus Blanking 10mus

PI 140% 146% 151%

Hysteresis 1% 2% 3%

Parabola 0% 2% 4%


0% DC margin 3% DC margin 6% DC margin

PI 150% 140% 135%

Hysteresis 0% 0% 1%

Parabola -1% -1% 0%

Ramptime 9% 10% 10%

Delay & Noise Delay only Noise only

PI 135% 135% 135%

Hysteresis 1% 0% 0%

Parabola -1% 0% -1%


Higher L Ideal L Lower L

PI 135% 135% 135%

Hysteresis 0% 1% 0%

Parabola 0% 0% 0%

Ramptime 9% 10% 10%

Table 4.3: Phase-shift: Criteria specific results (Steady-state, 5 kHz)

53


for Hysteresis and Parabola there were some small negative phase-shifts, which would

normally be interpreted as phase-leads. However, these could be argued as being small

enough to accept as inaccuracies of the fitting algorithm. Apart from blanking delay, most

other conditions tested did not reveal much impact on the phase-shift measure. However,

it was noticed that reducing the DC margin had increasingly (although small) adverse

affects on PI as the DC margin was reduced to 0 (Tables 4.2 and 4.3).

-20

0

20

40

60

80

100

120

140

160

IdealBlanking500ns DC Ripple

Delay &Noise Higher L

All Non-Ideal

Pha

se-s

hift

(% o

f Tsw

)

Figure 4.2: Phase-shift: Overview of analysis (Steady-state, 20 kHz)

-20

0

20

40

60

80

100

120

140

160Ideal

Blanking2µs DC Ripple

Delay &Noise Higher L

All Non-Ideal

Pha

se-s

hift

(% o

f Tsw

)

Figure 4.3: Phase-shift: Overview of analysis (Steady-state, 5 kHz)

Consistent with our phase-shift observations, any significant phase-shift results in a

large fundamental error component and thus the ESD measure also reflects the poorer

performance of PI (Figures 4.4 and 4.5).

Curiously, some additional simulations were run with standard PI control at 5 kHz

steady-state operation and it was noticed that the inherent distortion may manifest itself

54


0.00%

0.50%

1.00%

1.50%

2.00%

2.50%

Ideal Blanking500ns



ES

D

Figure 4.4: ESDi: Overview of analysis (Steady-state, 20 kHz)

0.00%

1.00%

2.00%

3.00%

4.00%

5.00%

6.00%

7.00%

8.00%

9.00%

10.00%

Ideal Blanking2µs



ES

D

Figure 4.5: ESDi: Overview of analysis (Steady-state, 5 kHz)

55


differently from a phase-shift, depending on whether the current is in-phase with the

voltage or not. Originally, simulation of current reference in-phase with the voltage shows

that the output current are roughly of the correct magnitude, but there is some phase-shift

compared to the reference current. When simulated with the reference current 90 out of

phase with the voltage, the output was observed to have little phase-shift relative to the

reference current and instead the amplitude was noticed to be quite significantly different

from the reference current (see Figure 4.6). This shows that the simple PI current control

is highly system dependent and once tuned for a particular set of system parameters

and assumptions, it is unlikely to cope with significant system changes (e.g. dynamic

changes in load conditions that affect power factor) without the addition of other control

mechanisms.

105 110 115 120 125−2

−1

0

1

2

Time (ms)

Cu

rre

nt

(A)

Figure 4.6: Example of steady-state PI waveform in 5 kHz system with 90 out-of-phasereference

From comparing ESD transient results to the distortion transient results (e.g. com-

pare Figures 4.7 against Figures 4.8 and 4.9 against 4.10), it is noted that the harmonics

measured for each control method under the varying test conditions show very similar

characteristic under each corresponding test condition. The main difference noticed was

the ESD showed Ramptime moving much closer to Hysteresis and Parabola and some-

times even under. Thus the ESD results would indicate that under stressful conditions

(i.e. transients and non-ideal system), Ramptime is relatively on-par with Hysteresis and

Parabola in achieving similarly low levels of low-order harmonics.

56


2.00%

2.50%

3.00%

3.50%

4.00%

4.50%

5.00%

5.50%

6.00%

6.50%

Ideal Blanking500ns



ES

D

Figure 4.7: ESDi: Overview of analysis (Transient, 20 kHz)

6.00

6.50

7.00

7.50

8.00

8.50

9.00

Ideal Blanking500ns



Dis

tort

ion

(%)

Figure 4.8: Distortion: Overview of analysis (Transient, 20 kHz)

57


6.00%

7.00%

8.00%

9.00%

10.00%

11.00%

12.00%

13.00%

14.00%

15.00%

16.00%

Ideal Blanking2µs



ES

D

Figure 4.9: ESDi: Overview of analysis (Transient, 5 kHz)

8.00

9.00

10.00

11.00

12.00

13.00

14.00

15.00

16.00

17.00

Ideal Blanking2µs



Dis

tort

ion

(%)

Figure 4.10: Distortion: Overview of analysis (Transient, 5 kHz)

58


4.1.2 Base Case for Ideal Performance

For an ideal system with switching at 20 kHz (or an equivalent number of switching

instances in a line-cycle for Hysteresis), all methods achieve quite similar levels of distortion

(within a 1-2 percent, see Figures 4.1 and 4.8). This suggests that for our initial system,

20 kHz operation is sufficiently high for each method to effectively control the system (i.e.

irrespective of the control method used). However, ideal case distortion results at 5 kHz

switching shows the separation of PI from the other methods being quite distinct (Figures

4.11 and 4.10). This will be explained later, but basically PI has an inherently greater

phase-shift.

3.00

4.00

5.00

6.00

7.00

8.00

9.00

10.00

11.00

Ideal Blanking2µs



Dis

tort

ion

(%)

Figure 4.11: Distortion: Overview of analysis (Steady-state, 5 kHz)

4.1.3 Blanking Time Effects

Consistent with expectations, increasing blanking time was observed to increase distortion

in general (see Figures 4.12a, 4.12b, 4.12c and 4.12d). Even though PI does not manage

the lowest amounts of distortion in the ideal case, results for the 20 kHz system show

that PI can perform quite well, with near insignificant changes to the distortion measure

from changes in blanking time (Figures 4.12a, 4.12b). Hysteresis and Parabola suffer most

from introducing blanking delay based on the amount of variation in distortion experienced

on the high-end of the tested range compared to their initial ideal results. Also notice

that results for Ramptime indicate a robustness across the combinations of blanking time,

current reference type and switching frequencies. The pairing up pattern is also noticeable

in the Steady-state 20 kHz setup, where Hysteresis and Parabola are observed to correlate

with each other and similarly the pairing of Ramptime and PI (Figure 4.12a).

As expected, the increase of blanking time does increase the phase-lag across all meth-

59


4.00

4.50

5.00

5.50

6.00

6.50

7.00

Idea

l

Bla

nkin

g50

0ns

Bla

nkin

g1.

5µsB

lank

ing

2.5µsD

isto

rtio

n (%

)

(a) Steady-state, 20 kHz

7.50

8.00

8.50

9.00

9.50

10.00

10.50

Idea

l

Bla

nkin

g 50

0ns

Bla

nkin

g 1.

5µsB

lank

ing

2.5µsD

isto

rtio

n (%

)

(b) Transient, 20 kHz

4.00

5.00

6.00

7.00

8.00

9.00

10.00

11.00

12.00

Idea

l

Bla

nkin

g 2µs

Bla

nkin

g 6µs

Bla

nkin

g 10

µsDis

tort

ion

(%)

(c) Steady-state, 5 kHz

10.00

11.00

12.00

13.00

14.00

15.00

16.00

17.00

Idea

l

Bla

nkin

g 2µs

Bla

nkin

g 6µs

Bla

nkin

g 10

µsDis

tort

ion

(%)

(d) Transient, 5 kHz

Figure 4.12: Distortion: Blanking time (Steady Steady and Transient, 20 kHz and 5kHz)

60


ods (Figures 4.13a and 4.13b), but to varying levels. The phase-shift for Hysteresis and

Parabola were observed to be most affected by blanking time relative to their ideal case.

This suggests that during the design stage it would be important to consider blanking

time for Hysteresis and Parabola control methods. So if the blanking time required for

the switching devices is expected to relatively large then another control method could

perhaps achieve more optimal performance.

0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

2.5E-02

3.0E-02

Bla

nkin

g50

0ns

Bla

nkin

g1.

5µsB

lank

ing

2.5µs

Pha

se-s

hift

(rad

ians

)

(a) Blanking time

0.0E+00

1.0E-02

2.0E-02

3.0E-02

4.0E-02

5.0E-02

6.0E-02

7.0E-02

8.0E-02

9.0E-02

1.0E-01

Bla

nkin

g2µs

Bla

nkin

g6µs

Bla

nkin

g10

µsP

hase

-shi

ft (r

adia

ns)

(b) Blanking time

Figure 4.13: Phase-shift: Blanking time (Steady-state, 20 kHz and 5 kHz)

The ESD measure reveals that again blanking time poses a significant issue for Hys-

teresis and Parabola in the 20 kHz steady-state system (Figure 4.14), where they approach

the same level of low-order harmonics as PI at 5 % blanking delay.

0.00%

0.50%

1.00%

1.50%

2.00%

2.50%

3.00%

Idea

l

Bla

nkin

g50

0ns

Bla

nkin

g1.

5µsB

lank

ing

2.5µs

ES

D

Figure 4.14: ESDi: Blanking time (Steady-state, 20 kHz)

For a possible explanation for why Parabola current control might be more severely

impacted, recognise that when the system approaches (and are at) duty-cycle extremes,

blanking delay imposes limits on the controls ability to switch with the desired duty-cycle.

In the case of Parabola current control, this may affect the behaviour of the control itself,

61


since the reset of the parabolic band generation relies on the timing of the switching

instances.

4.1.4 DC Voltage Requirements for Controllability

It was expected that by varying the DC voltage, a smaller margin reduces controllabil-

ity and thus degrades control performance as shown in Figures 4.15b, 4.15c and 4.15d.

However, Figure 4.15a shows an exception for the steady-state 20 kHz system in that the

fixed switching frequency methods had the opposite trend (i.e. reducing the DC margin,

decreased the distortion). On the surface this would be counter-intuitive, but perhaps this

can be attributed to the dominance of a reduced current ripple over any improvement in

controllability.

4.00

4.20

4.40

4.60

4.80

5.00

5.20

5.40

5.60

5.80

6.00

0% DCgap

3% DCgap

6% DCgap

Dis

tort

ion

(%)


6.00

7.00

8.00

9.00

10.00

11.00

12.00

13.00

0% DCgap

3% DCgap

6% DCgap

Dis

tort

ion

(%)


3.00

4.00

5.00

6.00

7.00

8.00

9.00

10.00

11.00

12.00

13.00

0% DCgap

3% DCgap

6% DCgap

Dis

tort

ion

(%)


8.00

10.00

12.00

14.00

16.00

18.00

20.00

22.00

0% DCgap

3% DCgap

6% DCgap

Dis

tort

ion

(%)


Figure 4.15: Distortion: DC margin (Steady-state and Transient, 20 kHz and 5 kHz)

Reaffirming our existing design knowledge for the DC bus voltage level to always be

some margin above the AC voltage, notice that the effects of a lowered DC voltage become

62


particularly significant under transients (see Figures 4.15b and 4.15d). Our results would

suggest that the DC bus voltage be maintained to be at least 103 % of the AC output peak

amplitude (given the larger initial reduction in distortion observed at the 3 % DC margin

level) for continued acceptable control fidelity of any method assuming an ideal system.

Looking at the ESD measures in Figures 4.16a and 4.16b reinforces this recommendation

and note that beyond 3 % there is less benefit of reduced harmonics.

0.00%

0.50%

1.00%

1.50%

2.00%

2.50%

0% DCgap

3% DCgap

6% DCgap

ES

D


0.00%

2.00%

4.00%

6.00%

8.00%

10.00%

12.00%

0% D

C g

ap

3% D

C g

ap

6% D

C g

ap

ES

D

(b) Steady-state, 5 kHz

Figure 4.16: ESDi: DC margin (Steady-state, 20 kHz and 5 kHz)

In terms of designing the system, these results for ESD may provide an indication of

the amount distortion to expect assuming your system remains fully controllable. And as

shown in this results, increasing your DC margin level will give marginally smaller gain

so it may not be necessary in all applications to go for very large DC margin (reducing

component costs).

4.1.5 Robustness to DC Bus Fluctuation

As depicted in Figures 4.1 and 4.11, the introduction of DC ripple was found to be of little

concern for any control methods in steady-state. However, under transients (Figures 4.8

and 4.10) all methods experienced an increase in distortion over their ideal case with the

exception of Hysteresis. The slight benefit gained by Hysteresis may simply be coincidental

due to an increased current slope around the transient regions (the 100 Hz DC ripple is

in-phase with the AC voltage) — compare Figures 4.17a and 4.17b.

The results also reveal that Ramptime in the transient 20 kHz system was impacted

the worst, where introducing DC ripple causes it to almost approach the same level of

distortion as PI (Figure 4.8). This would suggest that whilst Ramptime maintains con-

trollability of the system, it is vulnerable to detracted performance when the DC bus has

similar levels of fluctuations and the current reference waveform contains transients.

63


(a) Ideal case (b) With DC Bus Fluctuations

Figure 4.17: Potential explanation for supposed improved performance in Hysteresis

4.1.6 Inductance Parameter Dependency

In both the 20 kHz and 5 kHz systems (refer to Figures 4.18a, 4.18b, 4.18c and 4.18d),

introducing the small inductance value mismatch is observed to have a mild effect on most

of the control methods. However, for Hysteresis given a transient reference encounters

relatively more significant variation, which may just be coincidental (like the DC bus

fluctuations results).

It is comforting to find that the tested inductance variations have reasonably little

effect on these control methods. The results would indicate that the change in performance

Ramptime tends to follow the same change in performance PI incurs, but on average the

distortion levels for Ramptime are closer to those of Hysteresis and Parabola.

4.1.7 Behaviour from Feedback Inaccuracies (Noise and Lag)

Referring to Figures 4.19a, 4.19b, 4.19c and 4.19d, feedback delay and noise are shown

to have negligible effects on PI triangular carrier and Ramptime. Notice that the results

imply noise reduces distortion for Hysteresis and Parabola. Proceeding to examine the

time-domain waveform more closely it was found that noise causes hysteretic methods to

switch a bit earlier, which results in a smaller current ripple thus the improvement in

the distortion measures. Again, distortion results under the steady-state 20 kHz system

indicate similarities between Hysteresis and Parabola in their correlated performance and

similarly between Ramptime and PI (Figure 4.19a).

Delay in the sensed current was found to have some impact on all methods except

PI, with the two hysteretic methods observed to be more significantly affected in most

cases. Perhaps it is more obvious when comparing the feedback inaccuracies back against

64


4.00

4.50

5.00

5.50

6.00

6.50

HigherL

Ideal L Lower L

Dis

tort

ion

(%)


6.00

6.50

7.00

7.50

8.00

8.50

9.00

Hig

her

L

Idea

l L

Low

er L

Dis

tort

ion

(%)


3.00

4.00

5.00

6.00

7.00

8.00

9.00

10.00

HigherL

Ideal L LowerL

Dis

tort

ion

(%)


8.00

9.00

10.00

11.00

12.00

13.00

14.00

15.00

16.00

HigherL

Ideal L LowerL

Dis

tort

ion

(%)


Figure 4.18: Distortion: Inductance variation (Steady-State and Transient, 20 kHz and5 kHz)

65


3.00

3.50

4.00

4.50

5.00

5.50

6.00

6.50

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

Dis

tort

ion

(%)


6.00

6.50

7.00

7.50

8.00

8.50

9.00

9.50

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

Dis

tort

ion

(%)


3.00

4.00

5.00

6.00

7.00

8.00

9.00

10.00

11.00

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

Dis

tort

ion

(%)


8.00

9.00

10.00

11.00

12.00

13.00

14.00

15.00

16.00

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

Dis

tort

ion

(%)


Figure 4.19: Distortion: Feedback Inaccuracies (Steady-state and Transient, 20 kHz and5 kHz)

66


the ideal base case and then the all non-ideal case (see Figures 4.1, 4.8, 4.11 and 4.10).

Fortunately, when noise and delay are combined, they partially cancel the negative effects

of each other out. This would suggest it is possibly unnecessary to make any changes

to reduce the given level of noise in sensing, but any sources of significant delays in the

sensing signal should definitely be investigated.

The ESD results for this case, show that some of the increases seen in the distortion

measure can be attributed to an increase in lower-order harmonic content (Figures 4.20a,

4.20b, 4.20c and 4.20d).

0.00%

0.50%

1.00%

1.50%

2.00%

2.50%

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

ES

D


3.00%

3.50%

4.00%

4.50%

5.00%

5.50%

6.00%

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

ES

D


0.00%

1.00%

2.00%

3.00%

4.00%

5.00%

6.00%

7.00%

8.00%

9.00%

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

ES

D


6.00%

7.00%

8.00%

9.00%

10.00%

11.00%

12.00%

13.00%

14.00%

15.00%

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

ES

D


Figure 4.20: ESDi: Feedback Delay (Steady-state and Transient, 20 kHz and 5 kHz)

Results show no significant effect on phase-shift by feedback inaccuracies, where the

angles are very small anyway (Figures 4.21a and 4.21b).

67


0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

2.5E-02

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

Pha

se-s

hift

(rad

ians

)


-1.0E-02

0.0E+00

1.0E-02

2.0E-02

3.0E-02

4.0E-02

5.0E-02

6.0E-02

7.0E-02

8.0E-02

9.0E-02

Del

ay &

Noi

se

Del

ay o

nly

Noi

se o

nly

Pha

se-s

hift

(rad

ians

)(b) Steady-state, 5 kHz

Figure 4.21: Phase-shift: Feedback Delay (Steady-state, 20 kHz and 5 kHz)

4.1.8 All Conditions from 3.3.1 to 3.3.6 are Combined

Unexpectedly, the distortion results under the all non-ideal case with a steady-state wave-

form (Figures 4.1 and 4.11) was found to have near identical performance to their initial

ideal case result. Some control methods even showed a slightly improved result under the

all non-ideal conditions. The only plausible explanation for this is that the DC margin de-

signed for the base ideal case is still providing enough controllability for the all non-ideal

case with a steady-state current reference and that the size of current ripple has likely

reduced as a result of the non-ideal conditions.

However, under an all non-ideal system with a transient current reference (Figures

4.8 and 4.10), the distortion results show that most current control methods incur an

increased amount of distortion compared to their initial ideal case results. An outlier

result for Hysteresis is probably due to the DC bus fluctuations (as previously mentioned

in Section 4.1.5). Given that no significant spiked increase of the distortion was observed

for any of the current control methods, then results showed controllability was sufficiently

maintained despite the all non-ideal system.

4.1.9 Lower Target Switching Frequency

As mentioned earlier, when the target switching frequency was reduced to 5 kHz, the phase-

shift results show that PI suffers from the largest phase-lag (Figure 4.3). Compare this to

the other methods and observe that the other methods had phase-shifts at least an order

of magnitude smaller. Considering PI redesigned for the 5 kHz system, the raw phase-lag

was proportionally larger and suggests that standard PI alone, becomes far less capable

at lower switching frequencies. Also, the capabilities of all current control methods were

68


reduced significantly due to the lower target switching frequency. To see this, compare

the general levels of distortion in Figure 4.8 againt Figure 4.10.

4.2 Initial results from hardware-based Active Power Filter

experiment

It was unfortunate that the Parabola current control board suffered from noise-related

problems that were not ever satisfactorily resolved (although it was working fine under

very low-power conditions, i.e. below even that of the system considered here). From the

results, the following were most interesting:

• If it was briefly assumed that the %Error measure determined after LC filtering for

each current control is the absolute performance measure (Table 4.5), then it would

be reasonable to say that Hysteresis is the best control for an APF application

followed closely by Ramptime. This is reflected in the nice time and frequency

domain plots shown in Figures 4.26a, 4.26b, 4.27a and 4.27b.

• However, the LHDi and RLHi measures before LC filtering in Table 4.4, both

indicate that Hysteresis generates more lower order harmonics than Ramptime. This

is also reflected in Figures 4.23a, 4.23b, 4.24a and 4.24b, with Hysteresis having the

wider switching frequency spectrum. If the size of the LC filter was reduced (i.e.

allowing more frequencies to pass through), then this aspect would show up more

predominantly in Hysteresis’s post-filtering results.

Current Control %Error ∆I1 (%) THDi (%) RTHi (%) LHDi (%) RLHi (%) Φ ()

PI Triangular 13.9 4.32 17.6 18.3 11.2 11.7 5.3Hysteresis 12.3 0.64 12.6 12.6 1.21 1.21 -0.1Ramptime 13.6 0.61 13.9 14.0 1.19 1.20 0.1

Table 4.4: Measure values before the LC filter

Current Control %Error ∆I1 (%) THDi (%) RTHi (%) LHDi (%) RLHi (%) Φ ()

PI Triangular 27.1 9.71 12.2 29.9 12.0 29.9 12.2Hysteresis 13.8 4.37 2.77 3.65 2.77 2.89 7.3Ramptime 14.6 4.67 3.89 4.07 3.25 3.40 7.8

Table 4.5: Measure values after the LC filter

69

4.2. INITIAL RESULTS FROM HARDWARE-BASED ACTIVE POWER FILTEREXPERIMENT

-10 -5 0 5 10-4

-2

0

2

4

Time (ms)

Cur

rent

(A)

PI current control: imeas & iref

imeas

iref

(a) Time domain imeas

0 200 400 6000

0.2

0.4

Harmonics no - n

Cur

rent

am

plitu

de (A

) PI Error FFT Spectrum: imeas-iref

(b) Frequency domain imeas spectrum

Figure 4.22: PI current control (pre-filtered current)

-10 -5 0 5 10-4

-2

0

2

4

Time (ms)

Cur

rent

(A)

Hysteresis current control: imeas & iref

imeas

iref

(a) Time domain imeas waveforms

0 200 400 6000

0.2

0.4

Harmonics no - n

Cur

rent

am

plitu

de (A

) Hysteresis Error FFT Spectrum: imeas-iref


Figure 4.23: Hysteresis current control (pre-filtered current)

-10 -5 0 5 10-4

-2

0

2

4

Time (ms)

Cur

rent

(A)

Ramptime current control: imeas & iref

imeas

iref

(a) Time domain imeas waveforms

0 200 400 6000

0.2

0.4

Harmonics no - n

Cur

rent

am

plitu

de (A

) Ramptime Error FFT Spectrum: imeas-iref


Figure 4.24: Ramptime current control (pre-filtered current)

70


-10 -5 0 5 10-4

-2

0

2

4

Time (ms)

Cur

rent

(A)

PI current control: imeas & iref

imeas

iref

(a) Time domain igrid waveforms

0 200 400 6000

0.2

0.4

Harmonics no - n

Cur

rent

am

plitu

de (A

) PI Error FFT Spectrum: imeas-iref

(b) Frequency domain igrid spectrum

Figure 4.25: PI current control (post-filtered current)

-10 -5 0 5 10-4

-2

0

2

4

Time (ms)

Cur

rent

(A)

Hysteresis current control: imeas & iref

imeas

iref


0 200 400 6000

0.2

0.4

Harmonics no - n

Cur

rent

am

plitu

de (A

) Hysteresis Error FFT Spectrum: imeas-iref


Figure 4.26: Hysteresis curent control (post-filtered current)

-10 -5 0 5 10-4

-2

0

2

4

Time (ms)

Cur

rent

(A)

Ramptime current control: imeas & iref

imeas

iref


0 200 400 6000

0.2

0.4

Harmonics no - n

Cur

rent

am

plitu

de (A

) Ramptime Error FFT Spectrum: imeas-iref


Figure 4.27: Ramptime current control (post-filtered current)

71

4.2. INITIAL RESULTS FROM HARDWARE-BASED ACTIVE POWER FILTEREXPERIMENT

• At first glance of the %Error measure in the pre-filtered results in Table 4.4, it

would be reasonable to claim that PI performs competitively against Hysteresis and

Ramptime. Unfortunately, it was found that a high amount of harmonic content,

especially in the lower-order frequencies, has caused a significant downgrade in per-

formance following LC-filtering. Also, it was observed that PI suffers some loss

of stability during regions of stress, as evident by the significant deviations of the

measured current from the reference current and (Figures 4.22a, 4.22b, 4.25a and

4.25b). Hence why the LHDi and RLHi measures showed a significant amount of

lower-order harmonics over those in Hysteresis and Ramptime.

• Recall that RLHi and RTHi are both relative to the current reference and observe

in Tables 4.4 and 4.5 that they are both generally higher than their cousins LHDi

and THDi. This indicates that the fundamental magnitude of the output is slightly

higher than the desired current reference as seen in the ∆I1 measure.

• Referring to results before filtering in Table 4.4, notice that the THDi and RTHi are

pretty close together per control method. Similarly, the pairs of LHDi and RLHi are

close. This can be explained by the fact that the difference in fundamental betweens

the reference and the output is small (see ∆I1). So the difference in denominator in

each pair does not change much. Given that each result pair was close, implies that

the amount of harmonic content as a result of higher frequencies (e.g. switching)

was pretty good even before any LC filtering.

• Now contrast this to what happens after LC filtering in Table 4.5, where instead

THDi and LHDi are pretty close to each other for Hysteresis and PI. Recalling the

LHDi and THDi definitions, the closeness is quite expected if the higher frequencies

(such as switching) was mostly removed by the filter. Potentially, RLHi and RTHi

could be close for the same reason.

• The higher %Error after the LC filter is a result of the LC filter itself, since it causes

a phase-shift and thus is captured as a distortion in this measure. This phase-shift is

about 7 as seen when comparing Φ before and after LC filtering in Tables 4.4 and

4.5 respectively. That said, Hysteresis and Ramptime still manages to achieve very

“clean” post-filtered grid currents (especially compared to PI) as evident in Figures

4.26a, 4.26b, 4.27a and 4.27b versus Figures 4.25a and 4.25b).

• Also from Table 4.5, it was found that phase-shift on the LC-filtered grid side rep-

resented quite a large proportion of the distortion, despite many of the harmonic

measures showing relatively low values.

72

Chapter 5

General Implementation Advice

5.1 Some Implementation Warnings and Issues

This is a general discussion about the issues encountered when designing and implementing

the CC-VSI system in hardware. Although all of the control methods considered in this

work were mainly implemented in analogue circuitry, it should be realised that analogue

elements are typically accompanied by the following issues:

• non-ideal characteristics: there are many aspects to this, but an example would

be the fact that analogue components will never be manufactured to absolute per-

fection. Thus simplified/idealised component models used in design are not truly

representative of their behaviour in reality (e.g. losses in the system).

• noise capturing loops: whenever the return ground path does not follow along the

original signal, it presents opportunities for noise to be “captured” into these signal

loops and thus corrupt the signal. Such noise may come from many sources, even

from the system itself — such as interference derived by switching at high-voltages.

• distortions and offsets: analogue systems rely on either the voltage or current for

signal representation, so there are many potentials ways these may be affected. This

may happen when signals are unbuffered or the ground is not physically separated

for the analogue circuits from and digital circuits (see ground bouncing).

Digital circuitry also has its own issues. These include:

• quantisation error: the conversion of an analogue signal to a digital signal generally

involves sampling.

73

5.1. SOME IMPLEMENTATION WARNINGS AND ISSUES

• ground bouncing: digital circuits generally switch between on and off states and

thus draw sudden currents that may produce noise on the supply lines. Without

careful consideration of these effects, your digital circuits may well interfere with the

analogue portions.

• protection: digital logic devices are usually designed for low-power (low current and

voltage) operation. Thus any outputs from devices usually require an intermediary

driver circuit before interfacing back to the analogue world. An example in this

topology would be the digital logic controlling the switch gates should be isolated

by a proper driver.

The VSI topology poses some additional considerations of its own:

• switching noise: There is a lot of switching from the gates, which due to their power

levels will also be a source of significant interference. It would be advisable to keep

all control logic as far away as possible.

• lower power and high power interface: The gating devices would be considered the

high power components in the inverter that need to interface with the low power

control logic.

• DC bus capacitor: more of a danger warning than anything else, but there can be

potential for serious harm if the capacitor is accidentally discharged inappropriately.

• over-current: another danger is if the control is misbehaving and allows high-currents

to develop, where it may cause any number of components to fail (i.e. the weakest).

5.1.1 Dealing with some common issues

• Analogue buffering plays a very important role in any control circuits, whether dig-

ital or analogue — mainly because they capture the analogue input signal without

affecting the value it represents. An op-amp configured in differential input mode

is a typical choice for buffering signals, as this allows the ground to taken from the

original location of the input signal along with the signal itself. Combined with

use of twisted-pair wires, this will reduce the potential for noise to be captured by

any loops. A scaling and filtering on the buffered signal can also be performed by

the op-amp if necessary. Another advantage is that if designed properly it provides

protection to the rest of the circuit, which is certainly important when measuring

signals from high power levels.

• The conversion of that signal to digital format for input to digital controls is often

done by an analogue-to-digital converter (ADC). This will impose additional require-

ments on the analogue buffering of signals mentioned above. With care in the design,

74

GENERAL IMPLEMENTATION ADVICE

the buffered signals should be scaled appropriately to use the full resolution avail-

able on the ADC (reducing the magnitude related quantisation effects), but should

also protect the ADC from damage. Strategic timing of the ADC sampling may be

important too in reducing signal noise. For example, it is known that switching of

the gates generally causes a lot of noise, so it should be possible to avoid sampling

the signals when that happens. Digital filtering may also help, but be sure that it is

relatively fast (e.g. simple) to keep the control bandwidth high.

• Comparator outputs can be sensitive to noise around the crossover point, commonly

known as “bouncing” of the output signal. Adding hysteresis to the comparator is

the generally accepted method of removing this affect and is achieved by pulling

one of the inputs signals away from the other whenever a crossover is detected. This

produces an additional margin to which the noise will have to exceed before affecting

the signal. The pulling away of one of the signals need only be sustained for long

enough till the other input signal has moved far enough away (i.e. away from the

crossover location).

• To handle for the non-ideal characteristics faced in many parts of the system, it may

be necessary to build certain amount of tuning support into the circuits. This would

be particularly useful in the controller implementation, since a control may well need

to compensate for unexpected system losses.

• An appropriate choice in a pre-manufactured line driver will certainly reduce effort

involved in interfacing between the low-power control logic and the high-power gating

devices, since such switching modules often take care of the isolation between the

low-power control circuit from the high-power gate driver. Also the choice of a smart

switching module that has built-in blanking delay is a great precautionary measure,

for if by some chance blanking delay is not already produced in the control signals

then the gating devices in the bridge need not be destroyed instantly.

• Its a good idea to have an automatic way for the the DC cap to safely discharge when

the system is not in operation. Of course, whatever method used to discharge the

cap should not be left enabled during operation, because that would imply serious

losses.

• The first measure to avoid damage from overly high current is to put in place an

automatic fail-safe that detects the over-current situation and breaks the circuit

before any damage is done. It would be preferable that this fail-safe can be reset

without too much hassle (i.e. it is not a fuse). Also the selection of inductors are

important, because they can behave very differently (non-ideally) when saturated.

• Always plan for measurements and diagnosis of the control system, regardless of

an analogue or digital implementation. For example, consider providing test points

75

5.2. ALLOWING FOR CONTROL TUNING

and/or other forms of feedback (e.g. LEDs) for any signals/values of interest. Oth-

erwise, it may sometimes be very difficult to inspect important signals and having

test points will avoid accidental circuit alterations whilst the system is online (e.g.

a short caused by careless probing).

5.2 Allowing For Control Tuning

Any control would usually require some level of tuning to ensure it operates optimally for

the realised system. Thus this is a quick discussion of the implementation considerations

to allow for control tuning.

• Outer loop PI VDC control: Knowing that an empirical tuning technique would be

used for the outer loop control meant that the implementation of this control would

require a lot of flexibility for changes to the PI coefficients. This was addressed by

implementing the outer loop control in an FPGA, such that there was live control

over the coefficients. Then once suitable values were determined, these would be set

as the initial default values that the outer loop control would start up with.

• PI Triangular Carrier current control: Implemented in analogue circuitry, the PI

control board was built with trimpots to adjust the KP and KI coefficients. For the

pure inverter setup, these coefficients were initially set using the guidelines described

in Section 2.3.1. Importantly, the Nichols-Ziegler iterative tuning is used under the

shunt APF configuration because in this configuration the PI current control becomes

dependant on both the load as well as the inverter. Since the load in this case is

non-linear, deriving the KP and KI coefficients via a system model would be quite

difficult. If the same model was to apply from before, then it would only work if the

PI current control was given a compensation reference current waveform — not the

sinusoidal reference used in this shunt APF setup. Fine-tuning the control when the

system was live was not undertaken — mainly because of the many different and

often competing PI performance optimisations to consider.

• Hysteresis current control: Implemented mostly in analogue, the control board could

accept any h-band within circuit limitations or use the adjustable on-board offset

that was initially tuned based on targeting an average switching frequency that

matched the fixed switching frequency to be compared with. Once the system was

live, the h-band was empirically fine-tuned by counting the number of switching

instances per line cycle and adjusting the bands — where undoubtedly system losses

amongst other non-ideal considerations will have an effect on the average switching

frequency.

76


• Parabola current control: Similar to Hysteresis, the Parabola control board was im-

plemented mostly in analogue and accepted a constant for the parabola band gener-

ator. Since it approaches fixed switching frequency operation, it would be easier to

fine-tune than Hysteresis when the system is online — adjusting the constant whilst

observing the switching period. It should be noted that this was only successfully

demonstrated in a low-power rated system.

• Ramptime current control: Given it was implemented in the FPGA, it was relatively

easy to change the target switching frequency for the particular system configuration.

Once the system was online, Ramptime did not require further tuning.

5.3 Suggested Future Development Platform

5.3.1 Analogue or Digital Implementation?

When it comes to implementing the current control method, a designer will have to con-

sider whether it will be realised as a digital or analogue control. This becomes a question

of what can be gained from digital control over analogue control. Typically, a digital sig-

nal offers increased certainty in signal quality compared to the equivalent analogue signal

which are often much more susceptible to interference and/or offsets. This is because the

primary sources of error for digital signals are quantisation and resolution, where both

errors are well-understood and thus have predictable behaviour. Quantization and resolu-

tion usually go hand-in-hand, but are still separate ideas because quantization is a process

for converting a real-world analogue signal into a digital value and digital resolution is the

number of bits that can be used to represent a value in the digital domain. Therefore the

process of quantization will determine how accurately your value will be converted from

analogue to digital and usually relies on how well the hardware was designed (e.g. op-

amp pre-scaling and centering of the analogue signal before analogue-to-digital converter).

Resolution will affect quantisation and the rest of the digital controller as a whole because

it determines how many possible unique values can be represented digitally. For exam-

ple, a sequence of multiply-before-divide operations will generally have less loss due to

resolution when compared to performing a sequence of divide-before-multiply operations.

Once in the digital domain, digital devices have the benefit of very effective shielding from

known sources of digital interference (e.g. radiation) by proper materials selection for IC

packaging. If further protection is required, then this can be done by further enclosure in

an outer shielding case.

Other advantages of digital control implementations include:

• amount of space required for a digital controller implementing complex control al-

77

5.3. SUGGESTED FUTURE DEVELOPMENT PLATFORM

gorithms will often be much less than that required by an analogue controller of

similar complexity. This is because the complexity is “hidden away” inside of the

digital devices, which have undergone significant miniaturisation compared to ana-

logue components.

• it is easier to alter the control algorithm by changing the configuration/programming

of the digital control device as opposed to analogue control implementation. Whilst

you might be able to design an analogue control to have some tunability, it would

not be easy to implement a critical change in control behaviour without requiring

significant redesign.

• mentioned earlier, but some functions are difficult to implement in analogue. As

an example, a zero-able (resettable) integrator may be difficult to achieve ideally

compared to a similar digital construct.

• perhaps unique to power electronics, note that power electronics systems typically

involve switching to perform power conversion. Thus it would be logical to use

digital control because it already outputs binary states of “on” and “off” suitable

for switching signals.

Given the findings from the investigation, using a digital platform for implementation

should be highly appropriate — especially assuming that the control strategy will involve

more complexity. The matter now is to decide on which device to use as there are many.

However, no matter which device is considered, the choice of device should always be

decided based on meeting the requirements of the application and potentially leverage

upon existing skill base of the designer. The author would suggest the digital signal

processor as one such candidate here, due past experiences with such devices.

5.3.2 Digital Signal Processor

As the name suggests, a digital signal processor (DSP) is a type of processor that specialises

in digital signal processing. DSPs in digital control applications can be considered similar

to typical micro-controllers, but with the added capacity to perform complex mathematical

operations in the DSP’s hardware. This aspect is important since closed-loop bandwidth of

controls need to be fast and if the computations involved in determining control behaviour

are not sufficiently quick then this would obviously affect the speed of response from the

control loop. Whilst it is possible for a micro-controller to implement the same complex

calculations, albeit by emulating the DSP’s hardware-optimised operations in software —

the typical result is a slow control-loop that is unable to meet real-time constraints for use-

fully implementing the complex control. Thus DSPs can cater for implementations of very

complex control algorithms based on approaches that are typically too computationally

intensive to be achieved by standard micro-controller devices.

78


DSP applications

The DSP platform has been receiving continued interest and growth throughout its his-

tory despite some slight slowdowns [33]. Today, the markets for DSPs are very diverse

with significant demand driven by communications technologies (mobile phones and other

wireless telecommunications), multimedia (e.g. digital video and audio processing) and

smarter (i.e. more complex) control systems [34, 35]. There are competing DSP offerings

from Freescale (formerly Motorola, but more recently spun-off its semiconductor business),

Analog Devices and Texas Instruments (TI).

As an example, advanced motor control strategies can be considered to be of the same

level of complexity (if not more complex) as our expectations for an improved current

control scheme. In terms of motor control applications, the employment of a DSP-based

controller has allowed improved cost effectiveness and efficiency due to the selection of

a best-suited motor. Take white goods (such as a washing machine) for example, which

under traditional analogue-based control methods would require larger (oversized) AC

induction motors to handle transient loads. However, with the use of a digital motor

controller, the motor can be driven via an inverter with advanced control strategies to

deal with the transient load conditions. Hence the designer is able to choose a smaller

aptly-sized motor that achieves the equivalent mechanical power output and/or choose a

different type of suitable motor altogether (e.g. permanent magnet synchronous motors)

[36]. Another “smart” motor control possibility is to perform variable load (and/or speed)

drive, which will avoid the need for mechanical transmission (a source of loss itself).

DSPs versus field-programmable gate arrays (FGPAs)

A field-programmable gate array (FPGA) is also a popular choice for implementing digital

control logic. As the “field-programmable” keyword implies, FPGAs are semiconductor

devices that allow designers to re-configure their function in the field (i.e. after it has

already been manufactured). With typical FPGA architecture being designed to mimic

and interconnect discrete logic blocks, contrast this to an application specific integrated

circuit (ASIC) that is designed and manufactured to perform a particular function with

limited (if any) flexibility to be altered subsequently. Comparing FPGAs to DSPs is

basically a comparison of parallel processing versus serial processing, where FPGAs are

(by design) particularly well-suited for implementing real-time parallel combinatorial logic.

Some common FPGA suitability considerations are:

• FPGA outputs do not necessarily depend on a particular number of clock cycles like

a DSP output would. Thus an FPGA can (if logic is designed correctly) outperform

DSPs in terms of closed-loop responses.

79


• an FPGA can support a multiple of completely parallel control loops that operate

(if necessary) totally independent of each other, where as a single-core DSP can at

most emulate the multiple parallel control-loops and are in reality always serially

processed and thus conjoined.

• A former drawback of an FPGA was that it was not particularly suitable for imple-

menting complex calculations as the design tools were often too low-level and thus

involved a lot of effort. However, a new breed of FPGA architectures have attempted

to address this.

Type of DSP in FPGA Commercial examples

FPGA configurable DSP hardware blocks (e.g.multiplier-accumulation blocks, ROM/RAM blocksand memory addressing units)

Altera StratixXilinx VirtexLattice ECP2/XP2

DSP softcores that are purely based on FPGA fab-ric

Altera NiosXilinx MicroBlaze

Potentially any “optimal” mixture of the above(e.g. DSP softcore that would take advantage ofthe DSP hardware blocks built-in)

Xilinx MicroBlaze

Table 5.1: DSP inside an FPGA

These newer generation FPGA devices are overcoming previous shortcomings by in-

corporating much more advanced blocks and in some cases they even have a DSP built-in.

Such offerings are summarised in Table 5.1 where a few commercial examples of each kind

are listed. With the lines between FPGAs and DSPs blurred, each approach would have

their own pros and cons. For example, the softcore DSP implementations would generally

have slower clock speeds than the equivalent true hardware implementations, but having

DSP softcores also means that multiple cores can be instantiated within the confinement

of an FPGA.

Other new devices

Massively parallel cores are also stepping in to share the DSP limelight for running algo-

rithms that might once have been dominated by DSP implementations. This market grew

out of the multifaceted nature of many digital devices commonly available in modern so-

ciety (e.g. mobile phones with cameras and advanced personal information management

functionality of the likes of calendars and email, etc). Since there has been increasing

demand for RISC processors that have interfaces to DSP-oriented processing (e.g. speech

processing), once the fabrication process and miniaturisation of DSP cores became feasi-

ble for embedding DSP functionality into RISC processors, these new devices have quickly

been adopted in a similar to the trend seen with FPGAs [37]. A competitor to the FPGA

devices built-in DSP hardware is the picoArray series, which consists of an array of many

80


DSP cores on the same chip that are linked together via switches. The picoArray claims

to be as fast a the FPGAs with embedded DSP hardware with less power consumption

and can be programmed like a traditional DSP [38].

Development Tools

A major part of the development process involves the ability to inspect what the DSP

is doing whilst running the software. The ability to use an oscilloscope to examine most

intermediary signals of an analogue circuit could once be considered unparalleled in the

digital world, where the probing of different points in the circuit can often be performed

with relatively little effort as long as external access to the signals existed. However, more

recent advances have started to bring similar diagnosis capabilities to the digital domain

too. Whilst a certain level of monitoring is available from some integrated development

environments (IDE) via debugging features, the designer should be mindful of the cases

where monitoring may negatively affect the performance of the control (e.g. a breakpoint

within an interrupt routine or any other time critical code section should definitely be

avoided). As an example of some IDE-based monitoring features, the Code Composer

Studio IDE offered (for a Texas Instruments TMS320F28xx DSP) the ability to monitor

memory locations and/or registers and even included data logging capabilities.

81


82

Chapter 6

Conclusion

6.1 What has the investigations revealed?

This is a summary of the notable observations/experiences gained from the investigation

carried out in this work:

• For the considered current control methods, phase-shift between the measured cur-

rent output and the reference current was found to be proportional to the target

switching frequency, so perhaps it is predictable and can be compensated.

• Results indicate that phase-shift is proportional to blanking time, which would justify

using appropriate blanking-time compensation methods.

• Feedback delay was observed to contribute to additional low-order harmonic content

and thus such delays should be minimised whenever possible (e.g. better sensor

choice).

• A control method that performs well independent of DC bus variation will make

it easier to design for, since then it would be sufficient to just design the DC bus

level to meet a certain controllability margin (where this margin will ensure that the

system remains controllable even under transients and non-ideal assumptions).

• However, also take into consideration that there are diminishing returns from over

specification of the DC bus margin.

• Hysteretic or sliding mode controls using just the current as feedback is a very

useful quality, since the current controller tends to be more robust than those based

on modelling the system (e.g. Hysteresis, Parabola and Ramptime did not require

significant redesign to change its operation from a pure inverter setup to the shunt

active power filter configuration).

83

6.2. FUTURE CONTINUATION

6.2 Future Continuation

There are several areas identified from our results that a particular type of control can

perform very well-in and if it was possible such characteristics should be incorporated into

an improved or new control method. Here I consider how it may be possible to convert

these methods into something suitable for DSP implementation, and attempt to indicate

specific issues that would need to be addressed.

From the results, Ramptime would be deemed to have the most desirable characteristics

to offer:

• Usually immune to parameter variation;

• Near fixed-frequency switching;

• Performance is generally very decent;

• Maintains reasonable control even in adverse situations; and

• Very simple tuning.

That said, Ramptime could be argued as one of the more internally complicated control

methods compared to the others tested. The implementation of Ramptime in a DSP has

already be proven possible.

6.2.1 Possible avenues for control design/improvement

• The development of an improved/new current control method will likely involve

increased control complexity. Thus using a DSP would probably be most appropriate

for the task. Also given previous DSP working knowledge and background of this

researcher, there is the added benefit from being able to reuse DSP development

skills. The Ramptime control algorithm will likely be the inspiration if the author

were to pursue a DSP-based implementation as it has many desirable qualities. Then

once the current control algorithm is sufficiently mature based on simulations, the

current control would be prototyped and tested on the APF platform. This allows for

performance comparison against other previously analysed control methods, whilst

simultaneously verifying the suitability of the improved current control in an APF

application.

• DSP-based implementation of Parabola current control may perhaps be another di-

rection with potential, as it was found to have desirable qualities shared by Hysteresis

and Ramptime. Since a DSP would not be the traditional choice for implementation

of such controls, it would definitely present some challenges especially in the area of

84

CONCLUSION

responsiveness/speed. But when observing the more significant impact of blanking

delay on Parabola current control, accommodating for blanking time should be a

valuable achievement. Also, the parabolic band generator could benefit from using

resettable digital integrators for improved accuracy.

• In the shunt APF application, it should be entirely possible to factor in the phase-

shift caused by the LC filter. This might be achieved by slightly offsetting current

reference generation, which is normally in-phase with inverter line voltage. The

question is whether it would be preferable to determine this via measurement of

additional system variable(s), or alternatively be made into a tunable offset that

should be fixed one tuned for a particular APF system. The latter would be simpler,

but in a DSP the prior should also be feasible.

• Further exploration of the affects of non-unity power factor implications on current

controlled VSI designs should be performed. The change in distortion behaviour for

the simple PI current control was certainly an interesting initial insight. Perhaps

other interesting problems arise for the different current control methods.

• Investigate whether there is any potential to make use of the current sensings tech-

niques developed within the same labs by a fellow research colleague [39, 40]. For ex-

ample, [39] describes a transformer-based sensing method that was once abandoned

as infeasible due to the circuit complexity. However, by applying digital control it

was now possible to leap over the complexity hurdle and even improve some of the

sensing characteristics, thus making it a feasible method of current sensing. Also,

since the sensing method is already oriented for digital interfacing, then it should

prove to be particularly well-suited for future work on this topic.

6.3 Conclusion

The essential considerations for the development of an improved VSI current control has

been presented with plenty of avenues for future research. Although the exploratory work

has been conducted mostly through simulations, this has led into work on a physical

hardware experiment based on similar concepts. It also follows that any new control

method developed, may now use the same benchmark approach to verify its performance

against other methods. Although the simulations may not show much improvement in the

control performance against other methods, it may give the researcher additional insight

as to why that is and hopefully inspires further improvements before going to hardware.

85

6.3. CONCLUSION

86

Appendix A

Technical Data

A.1 Schematics

87

A.1. SCHEMATICS

Out

er L

oop

Vol

tage

Co

ntro

l

Inne

r Lo

op C

urre

nt C

ontr

ol

1-ph

Ful

l-brid

ge V

SI

Dio

de R

ectif

ier

Load

Grid

Low-pass

Filter

Figure A.1: PSIM Shunt APF experiment schematic

88

TECHNICAL DATA

I:\M

aste

rs\H

ystB

oard

\PI_

CC

Board

.sch

- S

heet1

Figure A.2: PI triangular carrier current control implementation schematic

89

A.1. SCHEMATICS

I:\M

aste

rs\H

ystB

oard

\HystB

oard

_R

ev3.s

ch

- S

heet1

Figure A.3: Standard Hysteresis current control implementation schematic

90

TECHNICAL DATA

A.2 Source code

A.2.1 MATLAB

calcMeasVarn.m

% Ca l cu l a t e measures f o r PSIM f i l e s ( g i ven a f i l e path and f i l e input mask )

function calcMeasVarn ( psimDir , psimFileMask )

F1 = 50 ; % fundamental f r e q

Ts = 1e−8; % time−s t ep ( s imu la t i on )

startTime = 0 ;

endTime = 210e−3;

N = round ( ( endTime−startTime ) /Ts ) ;

p s imFi l e s = dir ( f u l l f i l e ( psimDir , psimFileMask ) ) ;

for i = ( 1 : length ( ps imFi l e s ) )

f i l ePa t h = f u l l f i l e ( psimDir , p s imFi l e s ( i ) . name) ;

ou tF i l e s = dir ( f u l l f i l e ( psimDir , strrep ( f i l ePa th , ’ . txt ’ , ’ ∗ pctError . csv

’ ) ) ) ;

i f ( length ( ou tF i l e s ) < 2)

[ time i s en i r e f ] = LoadPSIMData( f i l ePa th , startTime , endTime , 0) ;

Tstep = time (2 )−time (1 ) ;

Npts = round ( ( endTime−startTime ) /Tstep ) ;

i f ( length ( time ) < Npts )

error ( ’ Error : P lease r e s imu la t e with the same startTime and

endTime ( not enough data po in t s ) ’ ) ;

end ;

i f ( exist ( strrep ( f i l ePa th , ’ . txt ’ , ’ avePctError . csv ’ ) , ’ f i l e ’ ) ˜= 2

. . .

| | exist ( strrep ( f i l ePa th , ’ . txt ’ , ’ sdPctError . csv ’ ) , ’ f i l e ’

) ˜= 2 . . .

| | exist ( strrep ( f i l ePa th , ’ . txt ’ , ’ vectBeginTime . csv ’ ) , ’

f i l e ’ ) ˜= 2)

avgChan = moving average ( i sen , (1/20 e3 ) /Tstep ) ; %remove

sw i t ch ing v ia moving ave

[ idxCross , tCross ] = c r o s s i n g ( avgChan , time ) ;

%need to ignore any c r o s s i n g s b e f o r e steady−s t a t e ach ieved

% ( i . e . PI r e qu i r e s at l e a s t 2e−3s b e f o r e the f i r s t proper

% steady−s t a t e c ro s s i n g i s made)

idxCrossOk = idxCross ( find ( tCross > 2e−3) ) ;tCrossOk = tCross ( find ( tCross > 2e−3) ) ;% assumes knowledge about s imu la t i on r e f e r ence

tCrossOk = unique (round( tCrossOk ∗1000/5) ∗5) /1000 ;idxCrossOk = round( tCrossOk/Tstep ) ;

91

A.2. SOURCE CODE

i f ( length ( idxCrossOk ) < 3)

error ( ’ Expected at l e a s t 3 zero−c r o s s i n g s ’ ) ;

end

vectBeginTime = [ ] ;

vectPctError = [ ] ;

vectESD = [ ] ;

vectRLH = [ ] ;

vectPhF1 = [ ] ;

for idx = 1 : 2 : length ( idxCrossOk )

tWinBegin = time ( idxCrossOk ( idx ) ) ;

tWinEnd = tWinBegin + 20e−3;i f ( tWinBegin >= time ( length ( time ) ) | | tWinEnd > time ( length

( time ) ) )

break ;

end ;

[ timeWin isenWin ] = dataWindow( time , tWinBegin , tWinEnd , ’n ’

, i s e n ) ;

[ timeWin ire fWin ] = dataWindow( time , tWinBegin , tWinEnd , ’n ’

, i r e f ) ;

I r e f rms = sqrt (sum( i re fWin . ˆ 2 ) / length ( i re fWin ) ) ;

pctError = (100/ I r e f rms ) ∗sqrt (sum( ( isenWin−i re fWin ) . ˆ 2 ) /

length ( isenWin ) ) ;

vectBeginTime = ve r t ca t ( vectBeginTime , tWinBegin ) ;

vectPctError = ve r t ca t ( vectPctError , pctError ) ;

[ f cn fftRaw ] = FFT iWave( timeWin , isenWin , F1) ;

[ f c n I e r r f f t I e r rRaw ] = FFT iWave( timeWin , isenWin−i refWin ,

F1) ;

ESD = (sum( cn I e r r ( 2 : 2 2 ) . ˆ 2 ) /( cn (2 ) . ˆ 2 ) ) . ˆ 0 . 5 ;

vectESD = ve r t ca t ( vectESD , ESD) ;

RLH = (sum( cn ( 3 : 2 2 ) . ˆ 2 ) /( cn (2 ) . ˆ 2 ) ) . ˆ 0 . 5 ;

vectRLH = ve r t ca t (vectRLH , RLH) ;

opts = f i t o p t i o n s ( ’Method ’ , ’ Nonl inear ’ , ’ Normalize ’ , ’On ’ ) ;

f type = f i t t y p e ( ’ s i n (50∗2∗ pi ∗x + ph) ’ , ’ opt i ons ’ , opts ) ;

f i t t e d = f i t ( timeWin ’ , isenWin ’ , f type , ’ S ta r tpo in t ’ , 0 ) ;

ph = f i t t e d . ph ;

f i t t e d = f i t ( timeWin ’ , irefWin ’ , f type , ’ S ta r tpo in t ’ , 0 ) ;

ph = ph − f i t t e d . ph ;

vectPhF1 = ve r t ca t ( vectPhF1 , ph) ;

%phase s h i f t i s a lways based on :

% magRef/ s q r t (2) ∗ s in (50∗2∗ p i ∗ timeWin + ph )

92

TECHNICAL DATA

hf = p l o t I s e n I r e f ( time , i sen , i r e f ) ;

savePlot ( hf , [ tWinBegin∗1 e3 tWinEnd∗1 e3 ] , [−2 2 ] , [ ] ,

linspace (−2 , 2 , 5) , f i l ePa th , ’n ’ ) ; %f u l l −c y c l e a f t e r

i n i t i a l i s t i o n

close ( hf ) ;

end ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ vectBeginTime . csv ’ ) ,

vectBeginTime , ’ d e l im i t e r ’ , ’ , ’ , ’ p r e c i s i o n ’ , 10) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ vec tPctError . csv ’ ) ,

vectPctError , ’ d e l im i t e r ’ , ’ , ’ , ’ p r e c i s i o n ’ , 10) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ vectESD . csv ’ ) , vectESD , ’

d e l im i t e r ’ , ’ , ’ , ’ p r e c i s i o n ’ , 10) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ vectRLH . csv ’ ) , vectRLH , ’


dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ vectPhF1 . csv ’ ) , vectPhF1 , ’


avePctError = mean( vectPctError ) ;

sdPctError = std ( vectPctError ) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ avePctError . csv ’ ) ,

avePctError , ’ d e l im i t e r ’ , ’ , ’ , ’ p r e c i s i o n ’ , 10) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ sdPctError . csv ’ ) , sdPctError

, ’ d e l im i t e r ’ , ’ , ’ , ’ p r e c i s i o n ’ , 10) ;

aveESD = mean( vectESD) ;

sdESD = std ( vectESD) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ aveESD . csv ’ ) , aveESD , ’


dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ sdESD . csv ’ ) , sdESD , ’


aveRLH = mean( vectRLH) ;

sdRLH = std ( vectRLH) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ aveRLH . csv ’ ) , aveRLH , ’


dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ sdRLH . csv ’ ) , sdRLH , ’


avePhF1 = mean( vectPhF1 ) ;

sdPhF1 = std ( vectPhF1 ) ;

dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ avePhF1 . csv ’ ) , avePhF1 , ’


dlmwrite ( strrep ( f i l ePa th , ’ . txt ’ , ’ sdPhF1 . csv ’ ) , sdPhF1 , ’


else

disp ( [ ’ Skipped perError ( r e l e van t f i l e s e x i s t ) : ’ , f i l ePa t h ] ) ;

end ;

end ;

end ;

93

A.2. SOURCE CODE

LoadPSIMData.m

% This func t i on e x t r a c t s the ( time , isen , i r e f ) from the PSIM s imu la t i on

data f i l e

% − Matlab 6 compat i b l e code

function [ time , i s en , i r e f ] = LoadPSIMData( f i l ePa th , t imeStart , timeEnd ,

maxLoadLen)

i f ( t imeStart > timeEnd )

error ( ’ Error : Must have t imeStart < timeEnd ’ ) ;

end ;

f i d = fopen ( f i l ePa th , ’ r t ’ ) ;

i r e fCo l I dx = 0 ;

i s enCo l Idx = 0 ;

lineNum = 0 ;

timeStep = 0 ;

colVarCount = 0 ;

while 1

i f ( lineNum == 0)

t l i n e = fget l ( f i d ) ;

i f ˜ i s c ha r ( t l i n e )

error ( ’ Error : Empty f i l e ’ ) ;

end ;

[ matchStart , matchEnd ] = regexp ( t l i n e , ’ [ ˆ ]+ ’ ) ;

for i = 1 : length ( matchStart )

matchStr = t l i n e ( matchStart ( i ) : matchEnd( i ) ) ;

i f (˜ isempty ( s t r f i n d ( lower ( char ( matchStr ) ) , ’ i a c t ’ ) ) )

i s enCo l Idx = i ;

end ;

i f (˜ isempty ( s t r f i n d ( lower ( char ( matchStr ) ) , ’ i r e f ’ ) ) )

i r e fCo l I dx = i ;

end

colVarCount = colVarCount + 1 ;

end

lineNum = ( lineNum + 1) ;

i f ( i r e fCo l I dx == 0 | | i s enCo l Idx == 0)

error ( ’ Error : Couldn ’ ’ t f i nd i a+n/ iac t , i r e f data columns ’ ) ;

end ;

else

dataVals = fscanf ( f i d , ’%f ’ , colVarCount ) ;

i f ( length ( dataVals )< 1) , break , end ;

t = dataVals (1 ) ;

i f ( timeEnd > 0 && t > timeEnd ) , break , end ;

94

TECHNICAL DATA

i f ( t >= timeStart )

time ( lineNum ) = t ;

i r e f ( lineNum ) = dataVals ( i r e fCo l I dx ) ;

i s e n ( lineNum ) = dataVals ( i s enCo l Idx ) ;

% pre−a l l o c mem

i f ( lineNum == 2)

timeStep = time (2 ) − time (1 ) ;

timeTmp = zeros (1 , round ( ( timeEnd − t imeStart ) / timeStep ) ) ;

irefTmp = zeros (1 , round ( ( timeEnd − t imeStart ) / timeStep ) ) ;

isenTmp = zeros (1 , round ( ( timeEnd − t imeStart ) / timeStep ) ) ;

timeTmp(1) = time (1 ) ;

timeTmp(2) = time (2 ) ;

irefTmp (1) = i r e f (1 ) ;

irefTmp (2) = i r e f (2 ) ;

isenTmp (1) = i s en (1 ) ;

isenTmp (2) = i s en (2 ) ;

time = timeTmp ;

i r e f = irefTmp ;

i s e n = isenTmp ;

end


i f (maxLoadLen > 0 && lineNum > maxLoadLen) , break , end ;

end ;

end

end

time = time ( 1 : ( lineNum−1) ) ;i r e f = i r e f ( 1 : ( lineNum−1) ) ;i s e n = i s en ( 1 : ( lineNum−1) ) ;fc lose ( f i d ) ;

disp ( [ ’ Loaded PSIM data f i l e : ’ , f i l ePa t h ] ) ;

dataWindow.m

%Extrac t s data f o r p a r t i c u l a r time window

function [ timeOut dataOut ] = dataWindow( timeAxis , startTime , endTime ,

inclEnd , dataIn )

i f ( startTime < t imeAxis (1 ) )

error ( ’ Error : I nva l i d startTime (must be with in timeAxis ) ’ ) ;

end ;

i f ( endTime > t imeAxis ( length ( t imeAxis ) ) )

error ( ’ Error : I nva l i d endTime (must be with in timeAxis ) ’ ) ;

end ;

t imeStep = timeAxis (2 )−t imeAxis (1 ) ;

i f ( inclEnd == ’y ’ )

count = round ( ( endTime − startTime ) / timeStep ) ;

95

A.2. SOURCE CODE

else

count = round ( ( endTime − startTime ) / timeStep ) − 1 ;

end ;

beg inIdx = round ( ( startTime − t imeAxis (1 ) ) / timeStep ) + 1 ;

endIdx = beginIdx + count ;

timeOut = timeAxis ( beg inIdx : endIdx ) ;

dataOut = dataIn ( beginIdx : endIdx ) ;

savePlot.m

%Save p l o t s wi th c e r t a i n f i g u r e parameters

function savePlot ( hf , xLimits , yLimits , xTicks , yTicks , f i l ePa th , showLegend

)

%add the path to e x p o r t f i g

exportFigPath = [ cd , ’ \ . . \ . . \ . . \ NewSims\ e x p o r t f i g \ ’ ] ;i f isempty ( s t r f i n d (path , ’ e x p o r t f i g ’ ) ) disp ’ Adding e x p o r t f i g path ’ ;

addpath ( exportFigPath ) ; end ;

ha = get ( hf , ’ CurrentAxes ’ ) ;

set ( ha , ’XTickMode ’ , ’ auto ’ ) ;

set ( ha , ’YTickMode ’ , ’ auto ’ ) ;

set ( ha , ’XLim ’ , xLimits ) ;

i f ( showLegend == ’y ’ )

legend ( ha , ’ show ’ ) ;

else

legend ( ha , ’ h ide ’ ) ;

end ;

i f (˜ isempty ( yLimits ) )

set ( ha , ’YLim ’ , yLimits ) ;

end ;

or igXTick = get ( ha , ’XTick ’ ) ;

i f (˜ isempty ( xTicks ) )

set ( ha , ’XTick ’ , xTicks ) ;

e l s e i f ( xLimits (1 ) ˜= origXTick (1 ) | | xLimits (2 ) ˜= origXTick ( length (

origXTick ) ) )

newXTick = linspace ( xLimits (1 ) , xLimits (2 ) , length ( origXTick )+1) ;

set ( ha , ’XTick ’ , newXTick ) ;

end ;

i f (˜ isempty ( yTicks ) )

set ( ha , ’YTick ’ , yTicks ) ;

end ;

i f ( length ( f i l ePa t h ) > 0)

plotName = get ( hf , ’Name ’ ) ;

e x p o r t f i g ( strrep ( f i l ePa th , ’ . txt ’ , [ ’ ’ , plotName , ’ win ’ , num2str(

xLimits (1 ) ) , ’− ’ , num2str( xLimits (2 ) ) , ’ms . pdf ’ ] ) , hf , ’−pdf ’ , ’−

96

TECHNICAL DATA

nocrop ’ ) ;

saveas ( hf , strrep ( f i l ePa th , ’ . txt ’ , [ ’ ’ , plotName , ’ win ’ , num2str(

xLimits (1 ) ) , ’− ’ , num2str( xLimits (2 ) ) , ’ms . emf ’ ] ) , ’ emf ’ ) ;

disp ( [ ’ Saved p lo t between ( ’ , num2str( xLimits (1 ) ) , ’− ’ , num2str( xLimits

(2 ) ) , ’ms) f o r : ’ , f i l ePa t h ] ) ;

end ;

FFT iWave.m

% This func t i on computes the FFT of from supp l i e d curren t waveform ( iWave ) ,

% where iWave shou ld be f o r a f u l l l i n e−c y c l e o f the fundamental f r e q (

fundFreq ) .


function [ f , cn , f f tOut ] = FFT iWave( time , iWave , fundFreq )

Ts = time (2 )−time (1 ) ;

Fs = round(1/Ts ) ;

L = length ( iWave ) ;

f = linspace (0 , Fs , L+1) ;

f = f ( 1 :L) ;

i f (˜ i s e qu a l ( f ( 2 ) , fundFreq ) )

error ( ’ Error : fundFreq did not match . Check input l ength o f a r rays : L =

(1/ fundFreq ) /Ts ) ’ ) ;

end

f f tOut = f f t ( iWave ) /L ; % ge t Fourier c o e f f i c i e n t s

cn = 2∗abs ( f f tOut ) ; % ca l c ampl i tude o f Fourier c o e f f i c i e n t s

moving average.m (third-party) [41]

function [Y,Nsum] = moving average (X,F ,DIM)

%MOVINGAVERAGE Smooths a vec t o r through the moving average method .

%

% Syntax :

% [Y,Nsum] = moving average (X,F,DIM) ;

%

% Input :

% X − Vector or matrix o f f i n i t e e lements .

% F − Window semi−l e n g t h . A p o s i t i v e s c a l a r ( d e f a u l t 0) .

% DIM − I f DIM=1: smooths the columns ( d e f a u l t ) ; e l s e i f DIM=2 the rows .

%

% Output :

% Y − Smoothed X elements .

% Nsum − Number o f not NaN’ s e lements t ha t f i x e d on the moving window .

% Provided to g e t a sum ins t ead o f a mean : Y.∗Nsum.

%

% Descr ip t i on :

% Quick ly smooths the vec t o r X by averag ing each element a long wi th the

% 2∗F elements at i t s s i d e s . The e lements at the ends are a l s o averaged

97

A.2. SOURCE CODE

% but the extrems are l e f t i n t a c t . With the windows s i z e de f i ned in

% t h i s way , the f i l t e r has zero phase .

%

% Example :

% x = 2∗ p i ∗ l i n s p a c e (−1 ,1) ’ ;

% yn = cos ( x ) + 0.25 − 0.5∗ rand ( s i z e ( x ) ) ;% ys = moving average (yn , 4 ) ;

% p l o t ( x , [ yn ys ] ) , l e gend ( ’ noisy ’ , ’ smooth ’ , 4 ) , a x i s t i g h t

%

% See a l s o FILTER, RECTWIN and MOVING AVERAGE2, NANMOVINGAVERAGE,

% NANMOVINGAVERAGE2 by Carlos Vargas and RUNMEAN by Jos van der Geest .

% Copyright 2006−2008 Carlos Vargas , nubeobscura@hotmai l . com

% $Revis ion : 3 .1 $ $Date : 2008/03/12 18 :20 :00 $

% Written by

% M. in S . Car los Ad r i n Vargas Agui l e ra

% Phys i ca l Oceanography PhD candida te

% CICESE

% Mexico , march 2008

%

% nubeobscura@hotmail . com

%

% Download from :

% h t t p ://www. mathworks . com/mat l a b cen t ra l / f i l e e x c h an g e / loadAuthor . do? ob j e c

% tType=author&o b j e c t I d =1093874

% 2008 Mar . Use CUMSUM as RUNMEAN by Jos van der Geest , no more

% sub func t i on s .

%% Error check ing :

i f ˜nargin

error ( ’ Moving average : Inputs ’ , ’ There are no inputs . ’ )

e l s e i f nargin<2 | | isempty (F)

F = 0 ;

end

i f F==0

Y = X;

return

end

F = round(F) ;

ndim = ndims (X) ;

i f (ndim ˜= 2)

error ( ’ Moving average : Inputs ’ , ’ Input i s not a vec to r or matrix . ’ )

end

[N,M] = s ize (X) ;

i f nargin<3 | | isempty (DIM)

DIM = 1 ;

i f N == 1

DIM = 2 ;

98

TECHNICAL DATA

end

end

i f DIM == 2

X = X. ’ ;

[N,M] = s ize (X) ;

end

i f 2∗F+1>Nwarning ( ’ Moving average : Inputs ’ , . . . % bug f i x e d 06 Mar 2008

’Window s i z e must be l e s s or equal as the number o f e lements . ’ )

Y = X;

i f DIM == 2

Y = Y. ’ ;

end

return

end

%% Window width

Wwidth = 2∗F + 1 ;

%% Smooth the edges but wi th the f i r s t and l a s t e lement i n t a c t

F2 = Wwidth − 2 ;

Nsumedge = repmat ( ( 1 : 2 : F2) ’ , 1 ,M) ;

Y1 = X( 1 :F2 , : ) ;

Y2 = fl ipud (X(N−F2+1:N , : ) ) ;

Y1 = cumsum(Y1 , 1 ) ;

Y2 = cumsum(Y2 , 1 ) ;

Y1 = Y1 ( 1 : 2 : F2 , : ) . / Nsumedge ;

Y2 = Y2 ( 1 : 2 : F2 , : ) . / Nsumedge ;

%% Recurs ive moving average method

% With CUMSUM t r i c k cop ied from RUNMEAN by Jos van der Geest (12 mar 2008)

Y = [ zeros (F+1,M) ; X; zeros (F ,M) ] ;

Y = cumsum(Y, 1 ) ;

Y = Y(Wwidth+1:end , : )−Y(1 :end−Wwidth , : ) ;

Y = Y/Wwidth ;

%% Sets the smoothed edges :

Y( 1 :F , : ) = Y1 ;

Y(N−F+1:N, : ) = flipud (Y2) ;

%% Get the number o f e lements t ha t were averaged f o r each element :

i f nargout == 2

Nsum = repmat (Wwidth , s ize (Y) ) ;

Nsum( 1 :F , : ) = Nsumedge ;

Nsum(N−F+1:N, : ) = fl ipud (Nsumedge ) ;

i f DIM ==2

Nsum = Nsum . ’ ;

end

end

99

A.2. SOURCE CODE

%% Return the co r r e c t s i z e :

i f DIM == 2

Y = Y. ’ ;

end

%% % Recurs ive moving average code b e f o r e Jos t r i c k :

% Y = X;

% Y(F+1 ,:) = sum(X(1 :Wwidth , : ) ,1) ;

% fo r n = F+2:N−F% Y(n , : ) = sum ( [Y(n−1 ,:) ; X(n+F , : ) ; −X(n−F−1 ,:) ] , 1 ) ;

% end

% Y = Y/Wwidth ;

crossing.m (third-party) [42]

% − Patched to ca t e r f o r data which s t a r t s /ends wi th a zero

function [ ind , t0 , s0 , t 0 c l o s e , s 0 c l o s e ] = c r o s s i n g (S , t , l e v e l , imeth )

% CROSSING f ind the c r o s s i n g s o f a g iven l e v e l o f a s i g n a l

% ind = CROSSING(S) re tu rns an index vec t o r ind , the s i g n a l

% S cro s s e s zero at ind or at between ind and ind+1

% [ ind , t0 ] = CROSSING(S , t ) a d d i t i o n a l l y r e tu rns a time

% vec to r t0 o f the zero c r o s s i n g s o f the s i g n a l S . The c ro s s i n g

% times are l i n e a r l y i n t e r p o l a t e d between the g iven t imes t

% [ ind , t0 ] = CROSSING(S , t , l e v e l ) r e tu rns the c r o s s i n g s o f the

% given l e v e l i n s t ead o f the zero c r o s s i n g s

% ind = CROSSING(S , [ ] , l e v e l ) as above but wi thou t time i n t e r p o l a t i o n

% [ ind , t0 ] = CROSSING(S , t , l e v e l , par ) a l l ow s a d d i t i o n a l parameters

% par = ’ none ’ | ’ l i n ea r ’ .% With i n t e r p o l a t i o n turned o f f ( par = ’none ’ ) t h i s f unc t i on always

% re turns the va lue l e f t o f the zero ( the data po in t t h a t s neare s t

% to the zero AND sma l l e r than the zero c ro s s i n g ) .

%

% [ ind , t0 , s0 ] = . . . a l s o re tu rns the data vec t o r corresponding to

% the t0 va l u e s .

%

% [ ind , t0 , s0 , t 0 c l o s e , s 0 c l o s e ] a d d i t i o n a l l y r e tu rns the data po in t s

% c l o s e s t to a zero c ro s s i n g in the arrays t 0 c l o s e and s 0 c l o s e .

%

% This ve r s i on has been r e v i s e d inco rpo ra t i n g the good and v a l u a b l e

% bu g f i x e s g i ven by user s on Mat l abcen t ra l . Sp e c i a l thanks to

% Howard Fishman , Chr i s t i an Roth l e i tne r , Jonathan Kel logg , and

% Zach Lewis f o r t h e i r input .

% S t e f f e n Brueckner , 2002−09−25% S t e f f e n Brueckner , 2007−08−27 r e v i s e d ve r s i on

% Copyright ( c ) S t e f f e n Brueckner , 2002−2007% brueckner@sbrs . net

% check the number o f input arguments

100

TECHNICAL DATA

error (nargchk (1 , 4 ,nargin ) ) ;

% check the time vec t o r input f o r cons i s t ency

i f nargin < 2 | | isempty ( t )

% i f no time vec t o r i s given , use the index vec t o r as time

t = 1 : length (S) ;

e l s e i f length ( t ) ˜= length (S)

% i f S and t are not o f the same leng th , throw an error

error ( ’ t and S must be o f i d e n t i c a l l ength ! ’ ) ;

end

% check the l e v e l input

i f nargin < 3

% se t s tandard va lue 0 , i f l e v e l i s not g i ven

l e v e l = 0 ;

end

% check i n t e r p o l a t i o n method input

i f nargin < 4

imeth = ’ l i n e a r ’ ;

end

% make row ve c t o r s

t = t ( : ) ’ ;

S = S ( : ) ’ ;

% always search f o r z e ro s . So i f we want the c ro s s i n g o f

% any o ther t h r e s h o l d va lue ” l e v e l ” , we s u b t r a c t i t from

% the va l u e s and search f o r ze ros .

S = S − l e v e l ;

% f i r s t l ook f o r exac t z e ro s

ind0 = find ( S == 0 ) ;

% then look f o r zero c r o s s i n g s between data po in t s

S1 = S ( 1 :end−1) .∗ S ( 2 :end) ;

ind1 = find ( S1 < 0 ) ;

% br ing exac t z e ros and ” in−between” ze ros t o g e t h e r

ind = sort ( [ ind0 ind1 ] ) ;

% and p i ck the a s s o c i a t e d time va l u e s

t0 = t ( ind ) ;

s0 = S( ind ) ;

i f strcmp ( imeth , ’ l i n e a r ’ )

% l i n e a r i n t e r p o l a t i o n o f c r o s s i n g

for i i =1: length ( t0 )

i f abs (S( ind ( i i ) ) ) > eps (S( ind ( i i ) ) )

% in t e r p o l a t e on ly when data po in t i s not a l r eady zero

101

A.2. SOURCE CODE

NUM = ( t ( ind ( i i )+1) − t ( ind ( i i ) ) ) ;

DEN = (S( ind ( i i )+1) − S( ind ( i i ) ) ) ;

DELTA = NUM / DEN;

t0 ( i i ) = t0 ( i i ) − S( ind ( i i ) ) ∗ DELTA;

% I ’m a bad person , so I s imply s e t the va lue to zero

% in s t ead o f c a l c u l a t i n g the p e r f e c t number ; )

s0 ( i i ) = 0 ;

end

end

end

% Addit ion :

% Some peop l e l i k e to g e t the data po in t s c l o s e s t to the zero cross ing ,

% so we re turn th e s e as w e l l

%[CC, I I ] = min( abs ( [ S ( ( ind−1)) ; S( ind ) ; S( ind+1) ] ) , [ ] , 1 ) ;

%ind2 = ind + ( II −2) ; %update i n d i c e s

% −−− hwz (Hartmut Wziontek ) 2008−08−26% make i t work f o r data s t a r t i n g / ending wi th a zero c ro s s i n g !

ind0 = find ( ind > 1 & ind < length (S) ) ;

[CC, I I ] = min(abs ( [ S ( ind ( ind0 )−1) ; S ( ind ( ind0 ) ) ; S ( ind ( ind0 )+1) ] ) , [ ] , 1 ) ;

I I = ind0 ( I I ) ;

ind2 = ind ;

ind2 ( ind0 ) = ind2 ( ind0 ) + ( I I −2) ; %update i n d i c e s

t 0 c l o s e = t ( ind2 ) ;

s 0 c l o s e = S( ind2 ) ;

LoadScopeData.m

% This func t i on e x t r a c t s the ( time , chanVals , chanUnit ) from a Texas

Instrument scope data f i l e


function [ time , chanVals , chanUnit , t imeStep ] = LoadScopeData ( f i l ePa th ,

maxLoadLen)

f i d = fopen ( f i l ePa th , ’ r t ’ ) ;

lineNum = 0 ;

recLen = 0 ;

timeTmp = zeros ( 1 , 1 ) ;

chanValsTmp = zeros ( 1 , 1 ) ;

chanUnit = ’ ? ’ ;

t imeStep = 0 ;

while 1

i f ( lineNum == 6 | | lineNum == 7 | | lineNum == 10 | | lineNum == 12 | |lineNum == 15)

dataVals = text scan ( f id , ’%s %s %s %f %f ’ , 1 , ’ d e l im i t e r ’ , ’ , ’ ) ;

i f ( lineNum == 7)

i f ( strcmpi ( dataVals 1 ,1 , ’ V e r t i c a l Units ’ ) ˜= 1)

102

TECHNICAL DATA

error ( ’ Error : Wrong f i l e format ( expected ” Ve r t i c a l Units ”) ’

) ;

end

chanUnit = char ( dataVals 1 ,2 ) ;end

else

dataVals = text scan ( f id , ’%s %f %s %f %f ’ , 1 , ’ d e l im i t e r ’ , ’ , ’ ) ;

i f ( lineNum == 0)

i f ( strcmpi ( dataVals 1 ,1 , ’ Record Length ’ ) ˜= 1)

error ( ’ Error : Wrong f i l e format ( expected ”Record Length ”) ’ )

;

end

recLen = dataVals 1 ,2 ;timeTmp = zeros (1 , recLen ) ;

chanValsTmp = zeros (1 , recLen ) ;

e l s e i f ( lineNum == 1)

i f ( strcmpi ( dataVals 1 ,1 , ’ Sample I n t e r v a l ’ ) ˜= 1)

error ( ’ Error : Wrong f i l e format ( expected ”Sample I n t e r v a l ”)

’ ) ;

end

t imeStep = dataVals 1 ,2 ;end

end


i f ( lineNum > recLen ) , break , end ;

i f (maxLoadLen > 0 && lineNum > maxLoadLen) , break , end ;

%disp ( lineNum) ;

timeTmp( lineNum ) = dataVals 1 ,4 ;chanValsTmp( lineNum ) = dataVals 1 ,5 ;

end

time = timeTmp ( 1 : ( lineNum−1) ) ;chanVals = chanValsTmp ( 1 : ( lineNum−1) ) ;

fc lose ( f i d ) ;

disp ( [ ’ Loaded scope data f i l e : ’ , f i l ePa t h ] ) ;

ScopeDataFFT.m

% Perform FFT fo r scope data loaded by LoadScopeData ( . . )

function [ f r eqAxis , chanFFTMag , chanFFTRaw , avgChan , avgFreq ] = ScopeDataFFT

( chanVals , time ) ;

avgChan = moving average ( chanVals , 20) ;

[ idxCross , tCross ] = c r o s s i n g ( avgChan , time ) ;

i f ( length ( idxCross ) < 3)

103

A.2. SOURCE CODE

error ( ’ Expected at l e a s t 3 zero−c r o s s i n g s ’ ) ;

end

l a s tC ro s s = length ( idxCross ) ;

i dxSta r t = idxCross ( l a s tC ro s s − 2) ;

idxEnd = idxCross ( l a s tC ro s s ) ;

t S t a r t = tCross ( l a s tC ro s s − 2) ;

tEnd = tCross ( l a s tC ro s s ) ;

[ timeOut dataOut ] = dataWindow( time , tStar t , tEnd , ’n ’ , chanVals ) ;

avgFreq = 1/( length ( dataOut ) ∗( timeOut (2 )−timeOut (1 ) ) ) ; %f i x e d bug

[ f r eqAxis , chanFFTMag , chanFFTRaw ] = FFT iWave( timeOut , dataOut , avgFreq ) ;

104

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