BG2000

bitGate data systems GmbH Landgraf Hermann Str. 11 D-36304 Alsfeld Germany

Features

• 8 / 16 / 32 bit data bus

• From 50 kHz up to 104 MHz

• Master or slave operation

• Cell buffer for 131k cells

• Traffic generation / analysis

• Trigger, filter, and statistics

• Cell decode functions

• Support of AAL 0/1/2/3/4/5

• Remote control

• Online streaming to disc

• Measurements between different interfaces.

Analyzer Highlights

Utopia Cell Capture 131.000 cells deep receive buffers. Cells can be filtered

before capturing. Start and stop of cell recording can be

controlled by trigger events.

POS Packet Capture Up to 64Mbyte deep receive buffer. Packets can be filtered

before capturing. Stop of Packet recording can be

controlled by trigger events.

Utopia Cell Analysis Segmentation and reassembly of all AAL types

(including AAL2). Cell decode function for OAM, RM, AAL,

O.191 cell type. Detection of HEC, AAL-CRC, AAL-SN,

OAM-CRC, O.191-CRC, O.191-SN errors. Timestamp for

each received cell.

Statistics Global Counters for number of cells, packets, tagged

cells, all errors and matching pattern. Individual

counters for 64k channels.

Counters for each Utopia or POS Phy address can be

online displayed in a table or as histogram bars in a

histogram window.

Trigger 4 trigger events or the combination of them can be

used for triggered capture, filter and statistics.

Trigger and recorder functions can be externally

gated.

BG2000

bitGate data systems GmbH Landgraf Hermann Str. 11 D-36304 Alsfeld Germany

General Description

The CPCI based BG2000 POS / Utopia Test System is the

ideal test tool for interface-testing during development and

production. A 2 Slot and a 4 Slot Mainframe (with integrated

keyboard and monitor) is available. The System can be

equipped with up to 4 Plug-in boards having different

interfaces.

A mixed mode with any other bitGate CPCI Modul is

possible as well. It may be used either stand-alone

or in a network. When used in a network several

users can access the system simultaneously to run

their own tests. Each user can select an analyzer

and generator part to work with.

BG2000 POS / Utopia Tester Utopia and POS-PHY Level 2 and Level 3 Test system for ASIC tests, VHDL/Verilog Code verification production testing.

BG2000

Generator Highlights

Utopia Cell Generation Cells can be user defined by cell editor,sequence profiler,

import of raw or AAL type data or by automatic generation

of o.191 test cells. 131.000 cell buffer for user defined

cells.

POS Packet Generation Packets can be userdefined by a packet editor up to

64kbyte length. Automatic generation of PRBS (O.191 like)

packets. Maximum buffersize 8Mbyte (64Mbyte as an

option). Up to 1024 Queues are supported

Error Insertion A basic error insertion allows to create different

errors like missing SOP, additional SOP, lost EOP

....... to test corner cases on the hardware.

Traffic Profiling Traffic statistics can be controlled manually or

automatically.

Manually: Each cell is given a timestamp, defining

when to be sent.

Automatic: A profiler allows to generate cell

sequences with an individual traffic profile. Different

sequences can be merged.

bitGate data systems GmbH Landgraf Hermann Str. 11 D-36304 Alsfeld Germany

BG2000 POS / Utopia Tester

Miscellaneous

Internal Logic Analysis System An internal Logicanalyzer allows to monitor POS signals

without connecting additional cables. The signals are

visualized to investigate the functional timing of the different

POS signals.

Adaptation to DUT Device Under Test is adapted through a Level3 or Level1/2

Probe. Refer an extra datasheet for connector pinnings and

dimensions of the probes.

Clock Generator There are three sources for Utopia clock: internal

clock generator, external clock input connector and

Utopia interface clock signal. Clockmaster-slave is

independent from the handshake.

Traffic Analysis A Bit Error Rate test can be started by only one

click. Statistics on cell interarrival time, cell transfer

delay, lost- and errored cells are shown in a statistic

table or bargraph.

Signal Clamping The user can select signals to be driven either high

or low continuously. This is an easy way to make

first troubleshooting tests and to verify connections.

BG2000

POS-PHY Level 2/3 Interface Support

POS Level 2 interface

POS Level 3 interface

Utopia Level 1/2/3 Interface Support

Bus width 8 / 16 / 32 bit Function ATM layer (master), PHY layer (slave) internal / external Clock up to 55 MHz for Level 1 and 2

up to 110 MHz for Level 3 Signal Level 3.3 Volts Handshake Level 1 Single PHY

Level 1 Extended Level 2 Standard Address Polling (SAP) Level 2 Direct Status Indication (DSI) Level 2 Extended Level 3 Single PHY

Cell Length 52 to 64 byte

Bus width 8 / 16 bit Function Link (master), PHY (slave) internal / external Clock up to 55 MHz Signal Level 3.3 Volts Handshake Multi PHY packet level Packet Length up to 64kbyte

Bus width 8 / 16 / 32 bit Function Link (master), PHY (slave) internal / external Clock up to 110 MHz Signal Level 3.3 Volts Handshake Single PHY packet level

Multi PHY packet level Packet Length up to 64kbyte

BG2000 POS / Utopia Tester

ATM Layer Device

TCLKTENB_L

TADR(4:0)TCLAV3:0)TDAT(15:0)

TPRTYTSOC

RCLKRENB_L

RADR(4:0)RCLAV(3:0)RDAT(15:0)

RPRTYRSOC

PHY Layer Device

TCLKTENB_LTADR(4:0)TCLAV(3:0)TDAT(15:0)TPRTYTSOC

RCLKRENB_LRADR(4:0)RCLAV(3:0)RDAT(15:0)RPRTYRSOC

Utopia Level 2 Interface

Transmit Interface

Receive Interface

TxCLKTxENB_L

TxADDR(10:0)TxDTPA(7:0)

TxSTPATxPTPA

TxDATA(31:0)TxPRTYTxSOP

TxMOD(1:0)TxEOPTxERR

RxCLKRxENB_L

RxVALRxDATA(31:0)

RxPRTYRxSOP

RxMOD(1:0)RxEOPRxERRRxSOX

POS-PHYLEVEL 3

LINK LAYER

TxCLKTxENB_LTxADDR(10:0)TxDTPA(7:0)TxSTPATxPTPATxDATA(31:0)TxPRTYTxSOPTxMOD(1:0)TxEOPTxERR

RxCLKRxENB_LRxVALRxDATA(31:0)RxPRTYRxSOPRxMOD(1:0)RxEOPRxERRRxSOX

POS-PHYLEVEL 3

PHY LAYERTransmit Interface

Receive Interface

电话： 020-3874 4528; 3874 4538 e-mail:

广州虹科电子科技有限公司 广州市五山华南理工大学国家科技园 2 号楼 504-505 室（510640）

sales@hkaco.com 网站：www.hkaco.com