Guest Editors’ Introduction..........................................................................................................................................................................................................................

BIG CHIPS

......For many years, classical siliconscaling (that is, Dennard scaling) providedthree benefits: doubling of integration capac-ity to deliver twice the number of transistorsper unit area every two years at constantprice, increased transistor performance, andreduced energy per transistor. With thesteady erosion of the latter two benefits, thelow-hanging fruit for performance increasehas been to exploit integration capacity viamultithreading, multicore, and now many-core. Indeed, a basic premise of multicorehas been that, by scaling supply voltage andusing more transistors, one can deliverimproved throughput with lower power.On the other hand, the erosion of energyper transistor raises the specter of dark silicon:with constant power budgets but increasingpower densities, an ever-smaller portion ofthe chip can be on at any given moment.This suggests that architects can shrink diesizes, rather than integrate unusable transis-tors, as transistor budgets meet hard powerlimits across both mobile and server productspaces.

Why, then, does the industry still producebig chips? In a personal communication,Shekhar Borkar, an Intel Fellow, notes thesteady stream of creative ways in which inte-gration capacity has been exploited: aggres-sive supply-voltage scaling with moretransistors, new paradigms in computationsuch as special-purpose hardware and acceler-ators for higher power efficiency, and imple-mentation of more functions on a chip thancan be afforded power-wise, along with fine-grained power management to activate selec-tively what can be afforded at any given

point in time. Borkar concludes, ‘‘All ofthis will require tremendous transistor inte-gration capacity, and there will be no darksilicon. Therefore, big chips will continueto have a future.’’

Indeed, recent chip sizes from IBM andIntel have been in the 500 to 600 mm2

range, exceeding the values posited in recenteditions of the International TechnologyRoadmap for Semiconductors. At the 45-nmtechnology node, with eight cores per socket,IBM’s Power7 chip is 567 mm2, and Intel’sNehalem-EX chip is 684 mm2. Tilera hasintegrated 64 cores in a single chip, andIntel’s research vehicle, the Single ChipCloud, has 48 cores. As the semiconductorindustry strives to keep Moore’s law ontrack with respect to utility in future pro-cessor products, futures that avoid ‘‘big’’(transistor counts) and ‘‘many’’ (cores) aredifficult to envision. Thus, a fundamentalchallenge for the future will be the intelligentuse of silicon area to maximize performancewhile keeping power and packaging costswithin budget.

As guest editors, we are privileged to in-troduce this IEEE Micro special issue onBig Chips. This special issue aims to sharesome of the trade-offs inherent in big chipswith respect to performance capability,power density challenges, scalability of com-munication, and packaging and coolingcosts. This issue also explores new technolo-gies that can achieve the effect of big chips,such as 3D integration, along with associatedtrade-offs. Submissions were solicited acrossa broad range of issues involved in buildingand sustaining big chips in the future,

[3B2-9] mmi2011040003.3d 20/7/011 15:10 Page 3

Andrew B. Kahng

University of California

at San Diego

Vijayalakshmi Srinivasan

IBM T.J. Watson

Research Center

0272-1732/11/$26.00 �c 2011 IEEE Published by the IEEE Computer Society

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including how to partition the chip betweencaches and CPU, network scalability for inter-core communication, impact on reliability andsparing of cores and cache, impact of yield ofdifferent configurations, and system integra-tion with heterogeneous special-purposecores, accelerators, and field-programmablegate arrays (FPGAs). The articles in thisissue cover only a small subset of challengesrelated to building effective big chips. Never-theless, we hope that this issue will lead tofurther dialogue and contemplation thatwill help define a roadmap for future bigchips.

Models and fundamental challengesfor big chips

In ‘‘Toward Dark Silicon in Servers,’’Nikos Hardavellas et al. begin with the prem-ise of dark silicon—that server chips will beinherently unscalable beyond several hun-dreds of cores, with mounting fractions ofdark silicon that can’t be powered up. Theauthors propose a combination of heteroge-neous, specialized compute engines in combi-nation with bandwidth-mitigating approachesto break the near-term performance energy-efficiency barriers.

In ‘‘Scaling with Design Constraints:Predicting the Future of Big Chips,’’ WeiHuang et al. use an analytical model to ex-plore the scalability of current multicoredesigns based on design constraints includingvoltage/frequency scaling, thermal designpower (TDP), core count growth, and in-crease in cache size. They argue for architec-tural innovations to bridge the gap betweenpromised throughput due to technology scal-ing, and the TDP-constrained throughputrealized in practice. They predict adoptionof new packaging solutions, including 3D in-tegration to realize throughput growth.

Scalable big chipsIn ‘‘Rigel: A 1,024-Core Single-Chip Ac-

celerator Architecture,’’ Daniel Johnson et al.target a broad class of data- and task-parallelapplications with Rigel, a single-chip 1,024-core accelerator. The authors walk usthrough the evolution of Rigel and highlightthe challenges of scaling the memory systemsand maintaining coherent caches. The article

closes with a discussion of future opportuni-ties and design challenges for such large-scaledesigns.

‘‘MOPED: Accelerating Data Communi-cation on Future CMPs’’ by Junli Gu et al.presents the challenges of data movementwithin many cores in a big chip. MOPEDis an explicit hardware communicationmechanism that enables off-loading synchro-nization and communication from CPUs.Detailed simulation results are presented tostudy MOPED’s benefits in reducing effec-tive memory latency and network latencyand in effectively overlapping computationwith communication to improve overallperformance.

Design methodologies for big chipsIn ‘‘Physical Synthesis with Clock-

Network Optimization for Large Systemson Chips,’’ David Papa et al. describe thedeficiencies of traditional physical-synthesismethodologies and present a new methodol-ogy to improve timing closure throughclock-network synthesis and careful place-ment of flip-flops and latches. The authorsdemonstrate the proposed methodology’s ef-fectiveness on IBM’s large CPU designs anddocument significant improvements in tim-ing, wire length, and area.

Enabling technologies for big chips‘‘Attaining Single-Chip, High-Performance

Computing through 3D Systems withActive Cooling’’ by Ayse K. Coskun et al.makes a case for efficient 3D liquid-cooledsystems based on design-time thermal anal-ysis with respect to flow rate, dynamic volt-age and frequency scaling (DVFS), and jobscheduling decisions. The authors use an inte-grated controller that monitors temperatureand core utilization and tunes the controlknobs to dynamically set the DVFS settingof each core and the coolant flow rate ofthe chip, based on a set of predefined rules.

This special issue provides a snapshotand a sampling of the tremendous

activity going on in the area of design ofbig chips. It is useful for microarchitects tounderstand the limitations and challenges ofpresent technologies as they explore new ideasto realize scalable big chips in the future.

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GUEST EDITORS’ INTRODUCTION

We hope that you will enjoy the selectedarticles, and we encourage you to providefeedback on this issue. MICR O

AcknowledgmentsWe are grateful to be able to present such

a strong collection of ongoing work relatedto the challenges of designing big chips.We thank all the authors who submittedarticles, and we thank the reviewers for pro-viding detailed and constructive commentsduring the review process.

Andrew B. Kahng is a professor of CSEand ECE at the University of California atSan Diego. His research interests includeintegrated-circuit physical design and perfor-mance analysis, the integrated-circuit design-manufacturing interface, combinatorialalgorithms and optimization, and the road-mapping of systems and technology. Kahngholds a PhD in computer science from the

University of California at San Diego. He isan IEEE Fellow.

Vijayalakshmi Srinivasan is a research staffmember at the IBM T.J. Watson ResearchCenter. Her research interests are in computerarchitecture, especially processor microarchi-tecture, and multicore and multiprocessormemory systems. Srinivasan holds a PhD inelectrical engineering and computer sciencefrom the University of Michigan. She is asenior member of IEEE.

Direct questions and comments aboutthis article to Andrew B. Kahng at abk@cs.ucsd.edu or to Vijayalakshmi Srinivasanat viji@us.ibm.com.

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