biquad ota

Analog Integrated Circuits and Signal Processing 3, 243-258 (1993) © 1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

OTA-C Biquad-Based Filter Silicon Compiler

MICHAEL R. KOBE Motorola, 6501 William Cannon Drive, West, Austin, TX 78735-8598

EDGAR SANCHEZ-SINENCIO Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3]28

JAIME RAMIREZ-ANGULO Department EE&CE, New Mexico State University, Las Cruces, NM 88003-0001

Abstract. An integrated software system that facilitates the design, and integrated-circuit layout of continuous-time OTA-C filter biaquad-based structures with typical cutoff frequenceis for a 3 gm technology in the 500 kHz-8 MHz range is described. The proposed integrated software system consists of three separate software modules written in the C language for the Apollo workstation (DN3000). The first module is a general filter approximation package. This program can approximate conventional magnitude, arbitrary magnitude, arbitrary group delay equalizer, arbitrary magnitude with group delay specifications. The second module aides in the synthesis of the biquad-based OTA-C filter structures. This module is unique in that the C code has the rule-based language CLIPS embedded within the code, and takes into account OTA-C filter nonidealities. An expert system using CLIPS was developed to select an appropriate OTA-C filter structure based on the nonidealities of the structures. After the filter structure has been chosen, the program will guide the user in the calculation of the capacitor values. These calculations are based on the nonidealities of the OTAs included in the standard cell library for layout, in addition the design of special purpose OTA as another alternative is also considered. Furthermore, the program will develop the necessary inpul: files for the layout generator. The final module is a modified version of AIDE2, a standard cell layout generator for switched-capacitor circuits. The input files to the modified AIDE2 is a C language program that describes the circuit (i.e., standard cells and their netlist). The output file is a CALTECH Intermediate Format (CIF) file that is required for fabrication.

1. Introduction

Recenty there has been a push for the creation of analog silicon compilers. The first work in this area con- centrated on switched-capacitor filters [1-6]. It was realized that a standard cell approach could be applied to the filter design process since the filter structure and the operational amplifiers within the structure were usuai[ly fixed, and only the capacitor ratios needed to be parameterized. For demanding applications high- performance op amps can be tailored to satisfy specifications as in [6]. Nonidealities of operational amplifiers and switches limit conventional switched-capacitor (SC) filters to lower frequencies than continuous-time filters. There are currently several groups [7, 8, 9] in- vestigating OTA-C filters operating at frequencies higher than 15 MHz. Monolithic filter structures, OTA- C, is well suited for frequencies in the range of 500 kHz-18 MHz. This technique [10, 11, 12] often uses CMOS operational transconductance amplifiers (OTA) and capacitors. Besides the advantage of the superior

high-frequency performance of OTA-C filters, these filters [10, 11, 12] are inherently voltage programmable and can occupy smaller silicon area than the SC filters.

Silicon compilers for switched-capacitor filters first appeared in the literature in 1985 [1, 2]. Since then, silicon compilers for operational amplifiers have also been reported [13, 14, 15]. Up until now no silicon compiler has been reported for continuous-time filters. The first step in the design of continuous-time filters is the approximation of a transfer function that satisfies a set of specifications. After a transfer function has been obtained, an appropriate filter structure is strategically selected and the component values are calculated. When the designer is satisfied with the filter's performance, the monolithic filter circuit is ready to be laid out for fabrication. Process variations and temperature variations severely affect continuous-time filters. Therefore, continuous-time filters require tuning circuits to yield accurate filters [12, 16, 9], thus, a complete filter silicon compiler should include these tuning circuits.

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244 Kobe, S&nchez-Sinencio and Ram[rez-Angulo

FIESTA, ~ the integrated software system described in this paper comprises three separate software modules: approximation, synthesis, and integrated circuit layout. The first and third modules can be applied to the design of any type of analog filter. The filter approximation module was written in the C language for the Apollo workstation (DN3000). The program can design conventional or arbitrary magnitude, arbitrary group delay equalizer, or a combination of these two, as well as low-Q magnitude approximation. 2 Typically, in second-order filters [10, 11] the Q value is approximately determined by a ratio of capacitors or transcon- ductances, consequently high Q values are area ineffi- cient which makes a low-Q approximation [11, 17-19] very desirable. The approximation process is governed by a set of menus making the program extremely user- friendly. In addition, the program takes full advantage of the workstation's graphic capabilities by plotting the different filter responses on the computer screen.

The synthesis module is written in the C language but has the rule-based language CLIPS [10] embedded within the code. Developed at NASA, CLIPS is written in the C language and can be transported to almost any computer. Besides selecting strategically the optimal OTA-C filter structure, this module selects the OTA from a library or from a special purpose OTA design 2 block of the type described in [15]. The layout of the OTA-C filter structures is accomplished by a modified version of AIDE2 [1, 20, 21]. AIDE2, also written in the C language, uses a standard cell approach for the layout synthesis, and was originally focused for switched-capacitor circuit design. An overview of FIESTA is illustrated in figure 1 where the three major modules are shown.

2. Approximation Techniques

The approximation problem is an old and mature one. There are many excellent software approximation pack- ages available. We decided to incorporate these approximation techniques for convenience and to have a self- contained design tool. One additional advantage of having access to modify the source code is to add recent approximation developments periodically appearing in the literature.

2.1. Types of Filters

FIESTA can design six types of filters: conventional magnitude, arbitrary magnitude, arbitrary group delay,

I~ i~N!NI&EXPE~ SYS E see:~sNNN~ N ~ ............................ :,i:~i~i~i~

!:! ii iiiiiii!i iiii i! ii iii iii ii ii!! i!i! ili FIESTA: nTA-C FILTER SIL[CnN CE]MPZLER

Fig. 1. Overall structure of modules of FIESTA.

arbitrary magnitude with group delay specification, and low-Q magnitude. 2

2.2. Conventional Magnitude

Under the conventional magnitude option, the Butter- worth (or maximally flat), Chebyshev, inverse Cheby- shev, and elliptic (or Cauer) approximations are available. For each of these approximation types, low-pass, high-pass, bandpass, and band-reject filter types can be designed. Details about these approximations are well discussed elsewhere [23, 24] and not repeated here. Furthermore, this module allows optimally distributed voltage gain of each second-order block to obtain maximum dynamic range [23]. The user can input (a) the frequency (and magnitude) specifications, (b) the order of the filter or (c) a predetermined transfer fimction file.

2.3. Arbitrary Magnitude

Approximating arbitrary magnitude filters with FIESTA involves three steps. The first step is to enter specifications of the arbitrary response on a point by point basis where a frequency, a lower bound, and an upper bound

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OTA-C Biquad-Based Filter Silicon Compiler 245

(window specifications) are specified. The second step is to approximate the arbitrary response with a conventional magnitude filter. The last step consists Of modifying the approximated response until the response satisfies all specifications. The nonconventional opti- mization approach implemented in FIESTA is described in the appendix. In addition, a practical approximation is contemplated dealing with cases resulting in high-Q sections which are typically obtained in conventional approximations, in those cases we will resort to the multiple-pole and zero-approximation [17-19]. This approximation yields second-order sections with low Q- factors. Low-Q sections have lower sensitivity and do not require sophisticated blocks in comparison with high-Q sections. Note, that in some cases, a trade-off between low-Q sections and the order of the approximation is involved.

2.4. Arbitrary Group Delay Equalization

The group delay approximation also involves three steps. The first step is to enter the specifications on a point by point basis as described above. The second step is to obtain an approximated solution, i.e., see [25]. The l~ird step is to apply the nonconventional optimiza- tion approach (see Appendix) until all specification is are satisfied. Furthermore, FIESTA allows the user to obtain approximation for several simultaneous combina- tions of magnitude and group delay specifications.

3. Fi l ter Synthe s i s

Analog IC filters are key components in telecommuni- cation applications as well as in video, radio, and in hard-disk drives. In these applications for a frequency range between 1 MHz to nearly 100 MHz continuous- time filters are very suitable. In particular, OTA-C filters have been proved to operate satisfactorily in the MHz range: for commercial applications and several hundreds of MHz frequency ranges [12, 26, 7, 8] in experimental results. The basic components of OTA-C filters are the OTA, which is a voltage to current transconductor, and the capacitor usually fabricated with polysilicon. OTA- C filters signal to noise ratios in the range of 60 and 90 dB are feasible with very linear and efficient transcon&rotors [16]. This S/N range is comparable with SC filters but with at least an order higher in frequency of operation.

The performance of OTA-C filters [27] depends on (i) the OTA architecture which is the main noise con-

Y C Vo

Fig. 2. Basic differential integrator.

tributor of the filter, and (ii) and the OTA-C filter structure. Even though several filter structures ideally can provide the same transfer function, when real OTAs are considered, the resulting transfer functions yield quite different frequency deviations and bandwidth or Q enhancement.

Next, we discuss some of the sources of the OTA-C filter nonidealities, and a design methodology that allows trade-offs to yield optimal OTA-C filter performance. Let us consider the basic cell, an integrator as shown in figure 2. the ideal transfer function is Vo(s ) / (V i+(s ) - IZ~n(S)) = gm/SC.

Finite Output Impedance Effects. Assume the output impedance consists of a capacitor and resistor, Co and Ro, respectively. The effect of Co can be absorbed by C, in fact, Co in many cases, is up to 25 % of the value of the integrating capacitor C. However, the output resistor Ro will make lossless integrator a lossy one. The (ideal) unity gain frequency for a voltage integrator is % = gm/C and a phase 4 = - 9 0 °, the nonideal voltage gain remains roughly unity, but the phase at co = c0 o becomes 4~ = - tan-lgmRo = -tan-1 Avo.

Transconductance Frequency-Dependent Effect. gm can be expressed [28, 27] as gm e-sT° ~ gm(1 -- sTo); where T O is the inverse of the effective 3-dB cutoff frequency. Thus, for ~ = Wo, the unity gain is not af- fected, and the phase yields

~ 1 -~ (la) = -tan-l~°°T° - 90° ~- - tan-~ w--O-~Oj

where ~ooT o is also known as the excess phase. Taking into account, simultaneously, the To and Ro effects, the actual integrator phase yields

cb = -tan-loooTo - tan -1 Avo (lb)

and ff can be approximated as

1 7r cb =- -oooTo + - - - - (2)

Av ° 2

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246 Kobe, S[mchez-Sinencio and Ram[rez-Angulo

Then, at ~0o = WoC = 1/AvoTo a critical frequency, the nonidealifies are cancelled out and the ideal - 7r/2 phase is reachable. Observe that the cancellation approach is not practical due to the process variations and the nonlinear variations [27] of Avo and To w.r.t, the control bias voltage of the OTA. A sound design approach requires Avo as large as possible, and To as small as possible. When these Ro and To nonidealities are considered in a two-integrator loop biquad filter a severe Q, quality factor, deviation is obtained. For instance, the actual Qa of the filter [29] shown in figure 3b, leads to

Q Qa ~ 1 + 2(1/Avo - o~oTo)Q (3)

The effect of Avo can be partially compensated by using OTAs with large output impedance stages (i.e., cascode, regulated cascode). The T o effect cancellation requires a fast OTA as well as a phase compensation circuit [26, 29] and a tuning circuit [9, 12, 16]. The Q deviations are dependent on Ro and T O as well as on the biquadratic OTA-C architectures [11, 28, 27]. Thus, for a set of filter specifications, both OTA characteristics and filter architecture must be considered.

Feedthrough Effects. It will next be shown that when both OTA input terminals are employed, additional deviations due to the OTA input capacitance could be critical. Consider figure 2 and connect points y and z together, then ideally the transfer function for an ideal OTA becomes

Vo(s) H i ( s ) - V+(s)

where

n i ( j ,~ ) l~ -~= = 0

gm gm + sC

(4a)

(4b)

Now, if we consider the OTA differential input capacitance, Cd, between nodes x and y, the transfer function becomes

Vo(s) = gm + sCa (5a) H(s) = Vi+(s) gm + S(Cd + C)

and

_ Cd 1 Hfj~o)l~_~ Cd + C - 1 + C/Cd < 1 (5b)

Notice from (4b) and (5b) that the ideal low-pass filter, at high frequency, becomes a voltage divider, i.e., Cd = 0.1C then the minimum output voltage at high frequency becomes 0.091z m or only -21 dB of attenuation

versus - ~ for the ideal case. Whereby the influence of Cd on the filter performance is topology dependent, and should be carefully considered in meeting filter design specifications.

Based on the desired filter type (LP, BP, etc.), filter specifications and transconductance nonidealities discussed before, the selection of the OTA and filter architecture [27] can be accomplished. This is further discussed with the objective, for a given set of design specifications, to obtain the minimum parasitic effect biquadrafic OTA-C filter architectures.

3.1. Selection of Filter Structures

The program for the synthesis of the filter is unique in that the filter structure is chosen by an expert system that has been embedded in the C code. The expert system, based on the previous discussion of OTA nonidealities, was written in CLIPS, a rule-based language written in the C languge by NASA. The computer language LISP was inadequate for NASA's needs since expert systems implemented in LISP are costly, are not easily integrated with other languages, and not available for many computer systems [30]. CLIPS on the other hand has an extremely simple syntax allowing for the quick prototype of expert systems. If the C language source code of CLIPS is available, CLIPS can be embedded within an application. In addition, it can be integrated with several languages, and can be transported to almost any computer. The CLIPS syntax has two con- cepts: rules and facts. The behavior of the rules and facts make CLIPS an excellent choice for the implementation of the filter structure selection. In addition, as more knowledge is obtained about the different filter structures, new rules can be implemented without having to recompile any of the existing FIESTA source code.

The OTA-C filter structure [10, 25] selection (con- sidering reduced parasitic effects) that has been implemented is derived from an extension of [28]. The results [27] are summarized in table 1 and figure 3. Table 1 was derived based on the following observations.

1. Injecting an input signal through OTAs with both inputs floating creates an undesirable new signal path (that is parasitic zeros). This causes a feedthrough factor, i.e., see equation (5).

2. The open-loop OTA voltage gain and the feedthrough factor place a limit on the maximum (real) attainable Qp, i.e., consider equation (3).

86


"C2 m

m

(a)

(b)

V 2

~ n 2 -

1 V3_ ½ in~ C2

_L

"C e

v1

(c )

Fig. 3. Basic filter structures: (a) loop of one lossless and one lossy integrator; (b) loop of two lossless integrators with two feedback summing nodes; (c) two-integrator loop with a single feedback summing node.

3. I f only deviations due to excess phase are considered, OTA-C filter structures with only two OTAs have the minimum effect on Qp but larger on fp. The filter of figure 3c has the largest ( fp, Qp) deviations, and the filter of figure 3b has an inherently

undesirable parasitic path associated with OTA gin2 (see equation (3) and [27]).

4. A node connecting several OTA outputs will deteri- orate the effective real output impedance at the node under consideration. This is due to the fact that the

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248 Kobe, S;mchez-Sinencio and Ram{rez-Angulo

Table 1. Obtainable filter structures of figure 3.

Outputs

Filter Input V1 V2 113

Figure 3a /in, BPR LP lin~ L_~P BP

Figure 3b /in, BPR L._.PP LP /in~ LP __BP /3P lin3 LP BP NOTCH

Figure 3c /in, BPR LP BP lin2 LP BP BPR Iin3 LP B_P_P UP

BPR = bandpass resonator (i.e., s + k) Underscore = best choice

output conductance is proportional to the total output current.

5. The location of the injecting input is ideally irrele- vant, but crucial in dealing with practical OTA-C filter structures, taking into account nonideal parasitic components. The output node of the filter is also important in determining a specific filter type with reduced parasitic effects.

6. High Q values force internal voltage nodes of bi- quads to be much larger (or smaller) than the output node voltage under consideration. This problem can be easily overcome by sound scaling, however, some structures with a limited number of OTAs have not enough degrees of freedom to allow this required scaling.

Particular filters are obtained from table t by injecting an input signal into a node and taking the output at the point that gives the closes to the desired response. Several options can exist for a particular filter type, however, other factors will determine the optimal structure for a particular application (a given o~ o, Q, maximum voltage gain, power dissipation, and dynamic range.). We have eliminated the option to inject an input signal through a capacitor since this requires an ideal voltage source. Also, we have eliminated the option to inject an input signal through an OTA with both input terminals floating; this is to minimize the feedthrough effects.

Rules regarding these structures were obtained taking into account OTA nonidealities (i.e., finite output (Co, Ro) and input impedances (Cd) and transconductance frequency dependence (To)). The selection of a filter structure for a given transfer function is made by choosing the structure satisfying the specifications with

a minimum number of OTAs. If specifications are not satisfied additional OTAs may be required. In this alternative, a single input is injected into several filter nodes. A summation of the nodes is performed to obtain the desired transfer function. Filters obtained 3 from figure 3a are good for high frequencies since all OTAs have a load capacitor and the differential input capacitance can be either included in the capacitance load or can be made negligible in comparison with C1 and C 2. One of the major factors limiting high-frequency performance is due to the fact that OTAs [24] have an excess phase

-sro" i.e., see equations (2) and (3). (i.e., gm = gmoe ), In particular, the excess phase of this filter is due mainly to two OTAs determining the bandwidth of the filter. Filters from figure 3c are good for low-frequency applications since the parasitic capacitance at the output of gm3 and gm4 are not cricital at low frequency. Two factors that determine the frequency limitations [28, 27] are the gm tuning range of the available OTAs and the allowable capacitance for the filter. For example, the ideal pole frequency for figure 3a is given by

N QC2

High frequencies are reached with the OTAs with large gin'S and capacitors with small values. For stringent applications, high-performance OTAs can be tailored by using the sub-module special purpose designer [31] (see figure 1). Currently, the largest gm allowed by any of the standard cells is 506/zsiemens (/~S) while the smallest capacitor is 0.5 pE Another factor that limits the frequencies obtainable by the filters (as mentioned before) is the excess phase ~ooT o, associated with the OTAs. Filters ranked from increasing excess phase are figures 3a, b, and c, respectively. The maximum frequency obtained by a particular filter is inversely proportional to the excess phase of the filter structure. OTAs can be compensated for excess phase (delay) by using two OTAs connected in parallel [29] with one input port interchanged or by a passive compensation [261.

Facts for the expert system are read from the file "FIESTA.FACTS" that is developed in the approximation program. The facts that are generated by the approximation module regard pole frequencies, Q values (and their degrees of freedom), and filter types. This file can be periodically updated by taking into account experiences from experimental results and new results reported in the literature.

88


3.2. Calculation of Component Values

Component values are typically calculated by choosing convenient values for certain components and calculat- ing the other values through coefficient matching (i.e., the coefficients of the filter structure are matched with the coefficients of the approximated transfer function). The OTA components are the main limiting factors in the design of OTA-C filter structures. Although the OTAs are programmable, their tuning range is very limited.

qChe calculation of the capacitor values and the selection of the OTAs occur simulataneously. The process is governed by a set of menus in which the designer has a selection of capacitor values. The capacitor values that appear in the menu selections are based on the geo~rnetric mean of the gm range of the available OTAs. There are four OTAs in the standard cell library with geometric means 25.0, 32.5, 50.0, and 250.0/xS. They will be referred to in table 2 as Nedungadi, impota2, impota2-5, impota2-10, respectively. If the coefficient to be matched has the form

B 2 =

Thus, other capacitors are similarly computed; this sometimes causes the use of different OTAs in the same biquad. This method of component selection allows for maximum tuning capability of the OTAs.

In the calculation of the capacitor values, the input and output capacitances of the OTAs (i.e., C i and Co) must be taken into account. In addition, if the parasitic capacitances are known from the layout (i.e., circuit extractor), these parasitics must also be considered for high-frequency applications.

3.3. AIDE2 Input File

After the falter structure has been chosen and the component values have been calculated, the filter is ready to be laid out for fabrication. The layout generator used in FIESTA is a modified AIDE2 version of [3]. The Input to AIDE2 is a C language program that describes the designed circuit topology (i.e., components and in- terconnections). To develop these input files, a knowledge of the C language and a complete understanding of the AIDE2 format are a must. To evaluate hte level of design, the input file for AIDE2 is developed auto- maticaily by the synthesis program.

four different capacitor values are obtained by substitut- ing the gm geometric mean of the four available OTAs, that is,

4. Integrated Circuit Layout Generation

4.1. Generalities

C - - gmi i = 1, 2, "3, 4 B2 '

An integrated circuit of the designed filter can be obtained using a modified version of AIDE2 [3] or a more

Table 2. Available standard cells.

Cell Name Cell Description No. Terminals

impota2 impota2 - g impota2 + g

impota2 - 5 impota2 - 5 - g impota2 - 5 + g impo ta2 - 10 impota2 - 10 - g impota2 - 10 + g ashok ashok - g ashok + g abuffer met poly_cap met polycap_g logo pad

lmpota2 from [23] lmpota2 with " - " grounded lmpota2 with " + " input grounded

lmpota2 - 5 from table 1 lmpota2 - 5 with " - " input grounded lmpota2 - 5 with " + " input grounded lmpota2 - 10 from table 1 lmpota2 - 10 with " - " input grounded lmpota2 - 10 with " + " input grounded Nedungadi's original OTA Nedungadi's OTA with " - " grounded Nedungadi's OTA with °' + " grounded Nedungadi's buffer Metal-poly capacitor -0.5 p F

Metal-poly capacitor with bottom plate grounded

TAMU logo Bonding pad

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250 Kobe, S&nchez-Sinencio and Ramirez-Angulo

sophisticated software [31]. AIDE2 is the second generation of the Analog Integrated Circuit Design program (AIDE) that performs standard cell layout with automated routing of the circuit. The aspect ratio (height with respect to width) of the chip can be selected by the user. The input file to AIDE2 is a C language program that defines the standard cells to be used and the netlist of the designed circuits. The output of AIDE2 is a CALTECH Intermediate Format (CIF) file necessary for fabrication. We used AIDE2 for availability of the software at that time, more elaborate software has been developed elsewhere [31, 9] that could be incorporated in a new version of FIESTA.

4.2. Modifications to AIDE2

Several key modifications were made to the original AIDE2 software. The first modification was the addition of the option for routing to the edge of the circuit without defining the bonding pads. In the original AIDE2, bonding pads are always placed for the I/O signals and the power supply bus. In many cases the bonding pads are not in any particular pattern. The option for routing to the edge of the circuit without bonding pads defined is helpful if a standard pad frame must be used (e.g., different standard pad frames are used in the MOSIS fabrication process), or if the filter is a part of a larger circuit. The second modification was in the CIF layer names. The layer names that were provided with the original software were not compatible with the layer names required by the Berkeley layout editor denomi- nated MAGIC. In order to view the layout output files from AIDE2, the CIF layer names had to be redefined.

The third modification was in the geometry of the standard cell. The geometry of the original standard cell is shown in figure 4 (the - 5 on the axis is AIDE2 convention). This geometry was designed for circuits that require a two-phase clock (i.e., switched-capacitor filters, A/D and D/A converters). Many of the OTA standard cells had already been laid out and character- ized in the MOSIS process. The geometry required for these circuits is shown in figure 5. Note that the height requirement for the OTA circuit is much less than that originally defined. In addition, the two-phase clock signals are not required for OTA-C filter structures. However, a control signal is required (Fc) for the OTAs and its location should be on the opposite side of the cell geometry then the clock signals. To eliminate wasted space and unneeded signals, and to define a new control signal, a new cell geometry was developed.

microns 500

485 48O 470 465 455 450 - 435 -

10-

--5--

_! _1

I

I

Gnd ] Phi 1 "]

Phi 2 J

Vdd 'i

Circuit Layout

Vss

Fig. 4. Geometry of original standard cell.

microns

330 -

315 -

310 -

295 -

2 7 -

1 5 -

I 0 -

- - 5 - -

I G.d 1 I Vdd !

Circuit Layout

I vc ]

I ] Fig. 5. Modified standard cell geometry.

Redefining the cell geometry required rewriting the power bus routing routines, and modifying the constraints found in the preprocessor that relate to the standard cell height.

4.3. Standard Cells

The standard cells that have been implemented in this program are shown in table 2. The connection between cells is accomplished with the routing routines; however it is impossible to connect the input of a standard cell

90


directly to ground with the existing software; hence, a standard cell ending in '°g" is an instance in which the OTA named has an input grounded. For example, " impota2-g" has the inverting input of the OTA connect~ to ground while "impota2 +g" has the noninvert- ing :input grounded. The "met_poly cap g" standard cell is a 0.5pF metal-poly capacitor 4 with the bottom plate grounded. Table 2 is not a complete list of all the standard cells available° Some of the standard cells not listed are used internally by the program (e.g., jumpers). The standard cells listed in table 2 are the ones that are called by the C language input file to AIDE2.

5. Example

This example will illustrate the design, synthesis, and integrated circuit layout of a Chebyshev bandpass filter. For this example, experimental CMOS test-chip results are presented.

Specifications. The filter to be designed is a sixth-order Chebyshev ban@ass filter with lower and upper frequencies, and a ripple specification of

fpl = : 0.5732 MHz, fPh = 0.9554 MHz, and

Am~ = 0.125 dB

The order constraints option with the conventional magnitude approximations was used with the optimum gain distribution [23]. The transfer function that re- suits is

2.2051 × 106s T(s) -- s2 + 2.2050 × 106s + 21.623 × 1012

2.2539 x 106s "s 2 + 1.4246 x 106s + 39.479 x 1012

0.4076 x 107s • s 2 + 0.7803 x 106s + 11.8438 × 1012

The pole frequencies and Q factors of the transfer function are

Stage Pole Freq. (MHz) Q Factor

1 0.7400 2.108 2 1.0 4.410 3 0.5477 4.410

Component Calculation. The chip for this example was fabricated in a MOSIS tiny-chip process. The 3-#m CMOS tiny-chip process used limits the area of the cir-

cuit to 2000 by 3000 microns. This size limitation will allow for only one filter stage to be laid out. However, MOSIS returns four chips for testing. Under certain conditions (i.e., close pole frequencies and close Q factor values), it may be possible to design one filter stage that will realize an N stage filter (by cascading the same chip N times). With this in mind, the geometric mean of the transfer coefficients were obtained and the one- stage filter became

2.9979 x 106s T(s) = s2 + 1.31175 x 106s + 21.623 × 1012

The components were calculated based on this one- stage transfer function. The filter structure chosen was from figure 3a. The capacitor values were C2 = 9.5 pF and C1 = 6.0 pF. The OTAs and capacitor values chosen were based on the fact that

6% = .~mlgm2 and Q = l ~m3 Cl

Assuming a transconductance adjustment range of a factor of 2 and capacitances and transconductance tolerances of +__30%. We selected

gml = gins = impota2 (250/zS geometric mean) gm2 = Nedungadi (32.5 /zS geometric mean) gm~ = Nedungadi (43 /~S geometric mean) gm,= impota2-5 (50 IzS geometric mean)

Note that the transconductance adjustment values allow us to compensate ~o o and Q for practical tolerances. The gins OTA provides the input for low-pass filter (i.e., both low-pass and bandpass filters can be realized with the same chip). In this case, the OTA associated with gm 5 is not needed to implement the bandpass filter considered here.

Experimental Results. A photograph of the chip, fabricated using 3#m CMOS technology, is shown in figure 6. A map of the chip is shown in figure 7. From figure 6, it can be seen that most of the available chip area is used (possibly two more OTAs could be placed). The monolithic filter was fabricated through and thanks to MOSIS. The practical transconductance tuning range was about a factor of 2.

The circuit in figure 6 was tested in the laboratory. Figure 8 shows the three experimental frequency responses (in broken lines) of each second-order bandpass. The solid line represents the overall frequency response of the sixth-order Chebyshev which meets line represents the overall sixth-order filter response. A summary of the experimental results of fo and Q for

91

252 Kobe, Sfinchez-Sinencio and Ram[rez-Angulo

F/g. 6. Photograph of fabricated circuit.

each stage are presented in table 3. The present building blocks (standard cells) in FIESTA limit approximately the operation of the filter to a factor ~ooQ = 10 MHz. More demanding specifications will require better OTAs or excess phase compensated OTA techniques [29].

6. Conclusion

FIESTA is an integrated software system for the design, synthesis, and integrated circuit layout of continuous- time OTA-C filter structures. Furthermore, due to the flexible overall structure of FIESTA, new additions or modifications can be easily incorporated with minimum effort. In its present form, FIESTA yields the layout of a filter with available terminals for manual or automatic tuning adjustments. A future addition to the software package is the implementation of user-selected automatic tuning approaches and a practical, versatile analog placement and routing software technique as well as a new wide tuning range OTAs.

FIESTA comprises three separate modules. The first module is a completely general approximation package for continuous-time filters. The second module aids in

gm2

gm 5

gm3

a Buffer

gin1

gm4

met_po ly_cap_g

met_po ly_cap_g

met_po ly_cap_g

Fig. 7. Map of fabricated circuit,

the selection of filter topologies via an expert system written in CLIPS that has been embedded within the code. After the filter structure has been judiciously selected and the component values have been calculated, an input file to AIDE2 is automatically generated. The third module is a modified version of AIDE2. AIDE2 is a program that has automatic place and route capabilities. AIDE2 was modified to make the output fries compatible with the Berkeley layout editor denomi- nated MAGIC. In addition, the standard cell geometry was modified to accommodate the OTA circuits.

92


1 0 . 0 = = = , n = I I

0.0'

'~ - - 1 0 . 0 '

, - - . , - 2 0 . 0 '

-30.0'

z~ -40.0'

-50.0'

- 6 0 . 0 ,

Table 3. Experimental results of OTA-C filter.

Stage Parameter Ideal Parameter % Error

| i I I I I

1 0 6

F r e q u e n c y [ H e r t z ]

Fig. 8. Experimental results of example.

order m that can be expressed as the product of m/2

second order all-pass biquadratic factors:

(S 2 -- (6ool/al)s + 6o2l) 0.10 TGD(S ) = (S 2 + (O~ol/Q1)s + 6021 ) . . .

- 2 .80 2

0.6 ( S2 -- 6oom/2/Qm/2 + 6oom/2) --0.4 (S 2 -t- (Wom/2/Qm/2)s + 2 ( A . 2 ) 6oom/2)

o.05 The magnitude transfer function TM(s) is an nth-order 0.45

transfer function of the form

1 )Co 0.740 MHz 0.74 MHz Q 2.108 2.05

2 f0 1.00 MHz 1.006 Q 4.41 4.393

3 fo 0.5477 0.5479 Q 4.41 4.43

Appendix: Approximation Procedure and Algorithm for Nonconventional Magnitude and Group Delay Specifications

A.1. Approximat ion Procedure Used in FIESTA

In dais section the procedure to approximate filter transfer functions with arbitrary magnitude and group delay responses is described, the transfer function of the filter, T(s), is assumed to have the form of the product of a "magnitude" and a "group delay" transfer functions, TM(s) and TaD(S) respectively, according to

T(s) = TM(S ) • T~D(S) (A. 1)

where TeD(s) is an all-pass transfer function of even

s 2 + (6oz l /az l )S + 6o2zt TM(S) $2 + (6opl/apl)S + (.021

2 $2 q- (6ozn/2/ Qzn/2) S "}- 6ozn/2 S 2 + (Wpn/2/Qpn/2)s --}- 6o2n/2

for n even and of the form

s 2 2 s -k- 6ozl , + (6ozz/Qzz)S + 6OZ2

(A.3)

T M ( s ) = - - - 2 " " " S "+" 6opl $2 q- (6op2/Qp2) S + 6op2

s 2 + (6oz(n - 1/2) /Qz(n - 1/2)s + o~2z(n - 1/2) s 2 "~- (wp(n - l / 2 ) /Qp(n - 1/2)s + 6o2p(n - 1/2)

(A.4)

for n odd. The filter magnitude response ] T(jw)J is determined

only the poles and zeros of the magnitude transfer function which can be expressed explicitly as

93

254 Kobe, Simchez-Sinencio and Ram[rez-Angulo

I TM~j~)I = I TM~j~,/SM)I (m.5)

where/SM is defined as a 2n-dimensional vector of poles and zeros of TM(S), that is

/SM=

[rc°pl, Qpl, O~zl, Qpl, O3p2, Qp2, . . . , n/21 z for n even (A.6a)

/SM = I [~Opl, Oazl, ¢Op2, Qp2, Wz3, Qp3, . . . , (n -1) /2 f f ~_ for n odd (A.6b)

The group delay response r(w) of the filter is obtained by adding the delay responses of TM(S) and T6D(S ) so that it depends on the poles and zeros of both TM(S) and of T6o(s) according to

T(O), /SM, P6D) -~" TM(O'), /SM) "[- TGD(~, /56D) ( A . 7 )

where PGD is defined as an m-dimensional vector of pole frequencies and Q factors of T6D(S ).

The task of filter approximation can be established as that of determining v e c t o r s / S M and/560 for which the magnitude and group delay response of the transfer function satisfies given upper and lower performance limits or "window" specifications (box constraints) for the magnitude and the group delay response.

The fulfillment of the window specifications for magnitude and group delay responses can be verified by calculation of the magnitude and delay responses at a large number of frequency points and comparing the calculated values to the upper and lower performance limits. Formally the approximation of a nonconventional filter for window specifications can be established as that of finding vectors/560 and/SM for which following inequalities are satisfied:

_ _ maxM g/minM < I TM,(/SM)[ < gi ,

i ~ {1, 2, . . . , IM} (A.8a)

_ _ maxGD gj minGD < TGDj(/SM, /SGD) < gj ,

j E {1, 2 . . . . . l~o} (h.8b)

min M gmaXM where gi , , are the lower and upper limits for the magnitude response at the frequency wi and gj minGD and gj ~xGD are the lower and upper tolerance limits for group delay response at the frequency wj, and it has been assumed that there are lM frequency points for verification of the magnitude response and lGD frequency points for the verification of group delay response (figure A.1).

Very powerful analytical techniques have been developed to approximate certain standard types of window specifications for magnitude responses like low-pass, bandpass, band rejection, high-pass, etc., responses [23,

24]. These approximations are the well know Butter- worth, Chebychev and elliptic approximations which lead to poles and zeros which are optimal in the sense of requiring the minimum order n for given specifications and type of response.

There are also very efficient techniques for the approximation of all-pass transfer functions with a delay response that matches an arbitrary nominal delay response at a small number m of frequency points, where m is the order of the delay equalizer [25]. These techniques are based on interpolation and in general the delay response obtained will still violate the window specifications, but the design provided by these techniques constitutes in general a good starting point (initial guess) which can then be refined to make it meet the window specifications for group delay.

The approximation of filters with arbitrary delay and magnitude response is iterative in nature. In FIESTA the techniques discussed above are used to obtain initial guesses for the magnitude and group delay vectors:/~t and /5~D which are then refined using the window specification design algorithm (WISE) described in the next section until it meets the desired specifications. The approximation procedure used in FIESTA is described in the flow chart of figure A.2.

A. 2. Window Specification Approximation Algorithm: WISE

The design algorithm presented in this section (WISE), allows to modify iteratively an existing "nonfeasible" design vector/5 so that a set of performance functions fi(P), f2(fi), • •., fl(P) can meet given upper and lower performance limits (window specifications) g/max, g/rain respectively, this task is established formally as that of finding a design vector/5 for which the inequalities

g~n < fi(/5) < g~n~x for k E {1, 2, . . . , l} (A.9)

are satisfied. It can be seen that the task expressed by (A.9) is

identical in form to that of (A.8a) and (A.8b) which define the problem of nonconventional magnitude and group delay approximation, and the same algorithm can be used for both approximations. In the first case the magnitude vector/sm corresponds to/5 and the value of the magnitude response TmifPM) at the magnitude response verification frequencies corresponds to f i ~ ) , in the case of the group delay approximation/SM is kept constant and the delay v e c t o r PGD correspond to

94

IT(t01


.'.'.v.v..'. v..:..?)i')i'i('i'i'~-i'). )..v.,-..~ ")))")i'i('i ??))?)))))i'i'??)i('. i'))i'i':)i. • ) i ' i . ' i ' ~ ( ' ) : v . v : . v . v . . . v : : :

i.i.i.))i•i.ii :.?)i.i.?) ' ) ) ) ( 7

. . ' . ' . ' . . . v ~ ' . ' . v . v . ' . v v ? ? . •

:'i-7')))i'. ?i'?)i(')i'. 15".', 'i . . . . . . . . .%)1"1"1"1"i' %1-)?71"71 "i-lvi'ii-:)i'i'.-(v):" "i

. . . . . . . : . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H . . v . . ' . v : . . - -. •

• i ' i ) . ( i i i : . . . . . . . .

• : . . . . . . . . - . . . . . . . . . .

tO m,, . . ._

(a)

~ i il !ill iil l i~ !i ~i~ . . . . . . . . . . . . . . . i I~I~

i i i i i i i . i i i i i i i . . i i i . i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i ( . i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i l f i i i l f i i i i i l f i l f i i l l i I iii I : i I • ~ii

i ) i ~ ) ~ . ) . ( ~ . . ) ~ . ~ ( . ~ . ~ ) ~ . ~ ) ~ . ) ) ) ) ) ) ~ ( . ) ~ ) ~ . ~ . ) ) ? ) ) ~ . ~ . ) ~ . ~ . ) ) ) ) ~ . ~ . ) ) ~ . ~ ( . ) ) ) ~ ( ~ ) ~ ( . ) ) ~ ( ~ . ) ) ~ . ~ . ~ . ~ . : . . ~ ( ) ) ~ i i

(9

(b) Fig. A l. (a) N o n c o n v e n t i o n a l w i n d o w s p e c i f i c a t i o n s for m a g n i t u d e r e s p o n s e ; (b) a r b i t r a r y w i n d o w s p e c i f i c a t i o n s for g r o u p d e l a y r e s p o n s e .

/3, the group delay response Tj(/3u,/3GD) at the group delay verification frequencies correspond to f~(/3).

The algorithm is stochastic and based on the fact that a design/3 corresponds to a point in an n-dimensional design parameter space. Points in this space that satisfy (A.9) from the so called "acceptability region,"

denoted Ra, whose boundaries are not known in ad- vance. The approximation task can be visualized as that of shifting an initial nonfeasible design (a point out- side RA) to the interior of R~. WISE is an iterative algorithm and during each iteration of following steps are performed.

95

256 Kobe, S[mchez-Sinencio and Ramtrez-Angulo

No

yYu

I z~emR WINDOw ~GrmmDE SP~C*TIONS: ~, ,.,~.ie |,.2....I,I I ENTER CONVENTIONAL WINDOW SPECIFICATIONS

FOR MAGNITUDE A,. Aj. f., f~. ....

t USE STANDARD APPROX]MATION TECHNIQUES ( BU'I'rERWORTH. CI-IEBYCHEV, ...) TO APPROXIMATE ANALYTICALLY CONVENTIONAL

FILTER : p~,

No

USE STANDARD APPROXIMATION TECHNIQUES (BUTTERWORTI~ CHEBYCHEV, . .) TO APPRO]QMATE CONVENTIONAL FILTER RESEMBLING NONCONVENTIONAL

RESPONSE TO OBTAIN INITIAL GUESS FOR MAGNITUDE VECTOR p~

t REFINE rrz~vELY mm~ MAGNr~ V~TOR us.~ WINDOW SPECIFICATION APPROX~IIATION ALGORITHM (WISE) UNTIL ALL

NONCONVENTIONAL MAGNITUDE SPECIFICATIONS ARE SATISFIED

P ; - - ~ P . UNTIL g ~ " < T.,(~.)_< S ~ , for iE 11,2,..~1.]

DEFINE PIECEWISE LINEARLY NOMINAL GROUP DELAY RESPONSE

FOR INTERPOLATION TECHNIQUE : "~=

USE INTERPOLATION TECHNIQUES OF [16] TO OBTAIN INITIAL DELAY VECTOR MATCHING NOMINAL RELAY RESPONSE q~mm AT M POINTS----d~p~

t REFINE ITERATIVELY DELAY VECTOR USING WINDOW SPECIFICATION

APPROXIMATION ALGORITHM (WISE) UNTIL DELAY SPECIFICATIONS ARE SATISFIED: F_" ~ ~.UNTIL ~ m . < T , ( P.. P. ) < I P - for j E, It,2..., l .]

Fig. A. 2. Signal-flow graph of approximation procedure used in FIESTA for filters with nonconventional magnitude and group delay response.

1. Define a "relaxed" acceptability region R~R in terms of the performance of the current nonfeasible d e s i g n / ) i SO that ffi lies at the boundary of RiAR (it can be shown that the true acceptability region Ra is a subset of the relaxed acceptability region).

2. Center the current design within RJtR by moving it to the center of a line with random direction origi- nated at the current design and extending to intersect boundary of the relaxed acceptability region.

3. Go to step 1, if after a certain number of iterations the number of violations does not decrease to zero the user is advised to stop the procedure and increase the order of the approximation.

WISE always provides an improved design after each step since, due to its nature, it always brings the current design away form the boundary of the relaxed acceptability region R~R contracting it gradually so that in the limit it becomes the true acceptability region (see figure A.3). WISE has been found to be very efficient for the approximation of nonconventional filters in FIESTA, more details about this algorithm can be found in [32]. Some of the advantages of WISE are its versatility, its good convergency characteristics, its simplicity, the fact that it does not require any type of gradient informa- tion and that the computational cost does not depend strongly on the order of the filter.

96

Pa °)


p, .

Fig. A.3. Illustration of iterative design improvement using WISE (window specification approximation algorithm) leading to a gradual con- traction of relaxed acceptability region.

Notes

1. The first version of FIESTA [22] was written in basic for personal computers and it is a primitive (and reduced) version of the second version here discussed.

2. Not yet implemented in current version of FIESTA. 3. In figure 3 the input currents/in,, lin2, Iin3 can be implemented

using OTAs. 4. The OTA-C filter can be tuned using the tail currents of the OTAs.

Therefore, the capacitors do not need to be any exact value.

References

1. P.E. Allen et al., "AIDE 2: an automated analog IC design sys.tem," in Proc. IEEE Custom Integrated Circuits Conf., pp. 498-501, 1985.

2. E S~inchez-Sinencio and J. Rami'rez-Angulo, "AROMA: an area optimized CAD program for cascade SC filter design" IEEE Trans. Computer-Aided Design, Vol. CAD-14, pp. 296-303, 1985.

3. J. Assael, P. Senn, and M.S. Tawfik, 'A switched-capacitor filter silicon compiler," IEEEJ. Solid-State Circuits, Vol. SC-23, pp. 166-174, 1988.

4. DG. Nairn and A.S. Sedra, "Auto-SC, an automated switched- capacitor design program," IEEE Circuits Dev. Mag., Vol. 4, pp. 5-8, 1988.

5. C.L. Winder and R.E. Massara, 'A design assistant approach to the implementation of analogue integrated circuits with particular reference to switched-capacitor filters," in Proc. 30th Midwest S3~np. Circuits and Systems, Syracuse, NY, pp. 1312-1315, 1988.

6. A. Barlow, K. Takasuka, Y. Nambu, T. Adachi, and J. Konno, '~m integrated switched capacitor filter design system," in Proc. IEEE Custom Integrated Circuits Conf., pp. 4.5.1-4.5-5, 1989.

7. B. Nauta, "CMOS VHF transconductance-C lowpass filter" IEE Electron. Lea., Vol. 26, pp. 421-422, 1990.

8. M. Snelgrove and A. Shoval, 'A CMOS biquad at VHF," in IEEE Proc. CICC-91, San Diego, pp. 9.2.1.-9.2.6, 1991.

9. W.R. Daasch, M. Wedlake, R. Schaumann, and P. Wu, 'Automa- tion of the IC layout of continuous-time transconductance- capacitor filters," Int. J. Orcuit Theory Appl., Vol. 20, pp. 267-282, 1992.

10. R.L. Geiger and E. S~inchez-Sinencio, 'Active filter design using operational transconductance amplifiers: a tutorial," IEEE Circuits Dev. Mag., pp. 20-32, 1985.

11. E. S~nchez-Sinencio, R.L. Geiger, and H. Nev~rez-Lozano, "Generation of continuous-time two integrator loop OTA filter structures," IEEE Trans. Circuits Syst., Vol. 35, pp. 936-945, 1988.

12. E Krummenacher and N. Joehl, 'A 4 MHz CMOS continuous- time filter with on-chip automatic tuning," 1EEE J. Solid-state circuits, Vol. SC-23, pp. 750-758, 1988.

13. R. Harjani, R.A. Rutenbar, and L.R. Carley, 'A prototype frame- work for knowledge-based analog circuit synthesis," in Proc. IEEE Design Automation Conf., pp. 42-49, 1987.

14. H.Y. Koh, C.H. Sequin, and P.R. Gray, 'Automatic synthesis of operational amplifiers based on analytic circuit models," in Proc. IEEE Int. Conf. Computer-Aided Design, pp. 502-505, 1987.

15. M.G.R. Degrauwe et al., "IDAC: an interactive design tool for analog CMOS circuits" IEEEJ. Solid-State circuits, Vol. SC-22, pp. 1106-1115, 1987.

16. M. Steyaert and J. Silva-Martinez, 'A 10.7 MHz CMOS OTA-R-C bandpass filter with 68 dB dynamic range and on-chip automatic tuning;' in 1EEE Int. Solid-State Circuits Conf., pp. 66-67, San Francisco, 1992.

17. M. Biey and A. Premoli, "Design of low-pass maximally flat RC-active filters with multiple real pole: the MURROMAF poly- nomials;' IEEE Trans. Circuits Syst., Vol. CAS-25, pp. 196-200, 1978.

18. A. Premoli, "Multiple-pole- and zero-approximation of general attenuation specifications," IEEE Trans. Circuits Syst., Vol. CAS-27, pp. /218-1224, 1980.

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258 Kobe, Sfnchez-Sinencio and Ram[rez-Angulo

19. M. Majid, J. Barby, and J. Vlach, "Minimizing sensitivities by restrictions on the largest Q'" Proc. IEEE/ISCAS, Vol. 3, pp 2008-2011, 1989.

20. P. Barton, D. Ellsworth, and S. Hong, AIDE2.1 User's Guide, School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, June 1986.

21. EE. Allen and M. Yu, AIDE2.1 Programmer's Manual, School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA, December 1987.

22. M.R. Kobe, J. Ra~'rez-Angulo, and E. S~inchez-Sinecio, "FIESTA--a filter, educational synthesis teaching-aid," IEEE Trans. Education, Vol. 12, pp. 280-286, 1989.

23. A.S. Sedra and EO. Brackett, Filter Theory and Design: Active and Passive, Matrix Publishers: Beaverton, OR, 1978.

24. A.H. Gray and J.D. Market, '~A computer program for designing digital elliptic filters" IEEE Trans. Acoustics, Speech, Signal Process., Vol. ASSP-24, p. 529-538, 1976.

25. R. Gregorian and G.C. Temes, "Design techniques for digital and analog all-pass circuits," IEEE Trans. Circuits Systems, Vol. CAS-25, pp. 981-988, 1978.

26. A. Nedungadi and R.L. Geiger, "High-frequency voltage con- trolled continuous-time low-pass filter using linearised CMOS integrators" Electron. Lett., Vol. 22, pp. 729-731, 1986.

27. H. Nev~ez-Lozano and E. S~inchez-Sinencio, "Minimum parasitic effects biquadratic OTA-C filter architectures," in Analog Integrated Circuits and Signal Processing, Vol. 1, No. 4, pp. 297-319, Kluwer: 1991.

28. H. Nev~rez-Lozano, A. Hill, and E. S~inchez-Sinencio, "Fre- quency limitations of continuous-time OTA-C filters," Proc. IEEE/ISCAS, Vol. 3, pp. 2169-2172, 1988.

29. J. Rami'rez-Angulo and E. S~nchez-Sinencio, "Active compensation of operational transconductance amplifiers using partial positive feedback" IEEEJ. Solid-State Circuits, Vol. 25, pp. 1024-1028, 1990.

30. CLIPS Reference Manual, Mission Support Directorate, Mission Planning and Analysis Division of the National Aeronautics and Space Administration, Houston, TX, Version 4.0, 1987.

31. J.M. Cohn, D.J. Garrod, R.A. Rutenbar, and L.R. Carley, "KOAN/anagmm 1I: new tools for device-level analog placement and routing;' IEEE J. Solid-State Circuits, Vol. SC-26, pp. 330-342, 1991.

Edgar Sfinchez-Sinenelo was born in Mexico City on, October 27, 1944. He received the M.S.E.E. degree from Stanford University, Stanford, CA, and the Ph.D. degree from the University of Illinois at Champaign-Urbana, in 1970 and 1973, respectively. Currently he is with Texas A&M University as a Professor. He is the co-author of Switched-Capacitor Circuits (Van Nostrand-Reinhold, 1984), and co-editor of '~rtificial Neural Networks: Paradigms, Applications, and Hardware Implementation" (IEEE Press Book). His interests are in the area of solid-state circuits, including CMOS neural network implementations and computer-aided design.

Dr. Sa'nchez-Sinencio was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He has been Associate Editor for IEEE Circuits and Systems Mag. (1982-1984), for 1EEE Circuits and Device Mag. (1985-1988), for the IEEE Trans. on Cir- cuits and Systems (1985-1987), and for the IEEE Trans. Neural Net- works (1990-1992). He is Guest-Co Editor for IEEE Trans. on Neural Networks Special Issue on Neural Network Hardware Implementations (1991, 1992, 1993). He was a Committee Member of the Scientific Committee of the Sixth, Eighth and Ninth European Conference on Circuit Theory and Design (ECCTD), Committee Member of the Technical Program: 1EEE International Symposium on Circuits and Systems (ISCAS) in 1983, 1987, 1989, 1990, 1992, and Chairman, IEEE CAS Technical Committee on Neural Systems & Applications (1990-1991). He was a member of IEEE CAS Board of Governors (1990-1992). He was appointed CAS Liaison Representative, IEEE Press. In 1992 he became a Fellow of the IEEE for contributions to monolithic analog filter design.

Mike Kobe graduated with a BA degree from Austin College, and BS and MS degree from Texas A&M University in 1986 and 1989, respectively. From 1989 to the present he has worked in the Memory and Micropmcessor Products Group at Motorola Inc., in Austin, Texas as a circuit designer.

Jaime ~ A n g u l o received a degree in communications and elec- tronic engineering from the National Polytechnic Institute (ESIME- IPN) of Mexico, the M.S.E.E. degree from the CINVESTAV-IPN in Mexico and the Ph.D. degree from the University of Stuttgart, Germany, in 1974, 1976 and 1982 respectively. He is currently associate professor in the Depaitment of Electrical and Computer Engineering at New Mexico State University. From 1982 to 1984 he was a researcher at the National Institute for Astroyphysics, Optics and Electronics (INAOE) in Puebla, Mexico; from 1984-1990 he was assistant professor at Texas A&M Unviersity. His research interests are in the area of analog and digital VLSI microelectronic circuit design.

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