bjt bias circuits emt116 –electronic …portal.unimap.edu.my/portal/page/portal30/lecture...
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BJT BIAS CIRCUITS EMT116 – ELECTRONIC DEVICESDR. NUR SYAKIMAH ISMAIL
CHAPTER OUTLINE
§ DC operating point
§ Base Bias
§ Emitter-Feedback Bias
§Voltage Divider Bias
§ Collector-Feedback Bias
§ Emitter Bias
§ Other Bias Configuration
DC OPERATING POINT
§ A transistor must be properly biased with a direct current (DC) voltage in order to operate as a linear amplifier.
§ A DC operating point must be set so that signal variations at the input terminal are amplified and accurately reproduce at the output terminal.
§ When bias a transistor à establish DC voltage and current values.
§ At DC operating point, !" and #"$ have specified values à referred as Q-point (quiescent point) à !"% and #"$%
DC BIAS
§ Bias establishes DC operating point (Q-point) for linear operation of an amplifier.
§ If not bias with correct DC voltages on the input and output, it can go into saturation and cutoff when input signal is applied.
§ In (a), proper biasing produce output signal which amplified input signal except it is inverted. Output signal swings equally above and below DC bias level of the output !"#(%&')§ improper biasing cause distortion of in output signal (b) & (c)
§ (b) illustrate limiting of positive portion of output voltage àQ-point being too close to cutoff.
§ (c) illustrate limiting of negative portion of output voltage àQ-point being too close to saturation.
DC BIAS
§ Transistor is biased with !"" and !## to obtain certain values of $", $#, $&, !#& .
§ The collector characteristic curve for transistor in (a) are shown in (b)
DC BIAS§ Assign !" values and observe what happen to !#and $#%.
§ !" = 200 )*à !# = +!" = 20 ,*$#% = $## − !#.# = 10 − 20 ,* 220 = 5.6 $Q-point shown as Q1
§ !" = 300 )*à !# = +!" = 30 ,*$#% = $## − !#.# = 10 − 30 ,* 220 = 3.4 $Q-point shown as Q2
§ !" = 400 )*à !# = +!" = 40 ,*$#% = $## − !#.# = 10 − 40 ,* 220 = 1.2 $Q-point shown as Q3
DC LOAD LINE§ DC operation of a transistor circuit can be described graphically using a DC load line.
§ A straight line drawn on the characteristic curves from the saturation value where !" = !"(%&') on y-axis to the cutoff value where )"* =)"" on the x-axis.
§ The load line is determine by the external circuit ()"" and +"), not the transistor itself.
§ From !" equation:
!" =)"" − )"*
+"= )""+"
− )"*+"= − 1
+")"* +
)""+"
Compare to general straight line equation / = 01 + 2 where slope is − 34 56, an x intercept of )"* = )"", and y intercept of 78858
which is !"(%&').
The point at which load line intersect with characteristic curve represent Q-point
LINEAR OPERATION§ Region along the load line between cutoff and saturation à linear region of transistor’s operation.
§ in this region à output voltage is ideally a linear reproduction of the input.
§ Assume a sinusoid voltage, !"# is superimposed on !$$ à %$ vary 100()sinusoidally above & below Q point
§ cause %* vary 10+) sinusoidally above & below Q point
§ As a result, !*, vary 2.2 ! sinusoidally above & below Q point
§ Point A, B and Q correspond to positive peak, negative peak and zero value of sinusoid input voltage.
§ !*,/, %*/, %$/ are DC Q-point values with no input sinusoidal voltage applied.
WAVEFORM DISTORTION
EXAMPLE
§ Determine Q-point for the circuit
§ Draw the DC load line.
§ Find the maximum peak value of base current for linear operation.
Assume !"# = 200.
SOLUTION
EXAMPLE
§ Determine Q-point for the circuit
§ Draw the DC load line.
§ Find the maximum peak value of base current for linear operation.
Assume !"# = 100. 24 V
1 kΩ
BASE BIAS CONFIGURATION§ Simplest transistor DC bias configuration.
§ For DC analysis, capacitors can be replaced with open-circuit equivalent.
§ DC supply, !"" can be separated into 2 supplies to permit a separation of input and output circuit.
BASE BIAS CONFIGURATION
§ Consider the B-E circuit loop:
!"#" + %"& − %(( = 0
!" =%(( − %"&
#"
!( = +!"
BASE BIAS CONFIGURATION
§ Consider the C-E circuit loop:!"#" + %"& − %"" = 0
%"& = %"" − !"#"
%"& = %" − %&%*& = %* − %&
§ Since %& = 0%* = %*&%" = %"&
BASE BIAS CONFIGURATION
§ DC Load Line analysis:!"# = !"" − &"'"
§ During saturation, &( maximum à !"# ≈ 0 !∴ &"(-./) =
!""'"
§ If !"# is small (not 0 V):
∴ &"(-./) =!"" − !"#(-./)
'"§ During cutoff, &1 = 0, &" ≈ 0
∴ !"# = !""
BASE BIAS CONFIGURATION – DC LOAD LINE
If !" is changed by varying #"
If $%% is held fixed and #% increased
If #% is held fixed and $%% decreased
EXAMPLEGiven the DC load line and the defined Q-point.
Determine the required value of !"", $" and $% for a fixed-bias configuration.
Answer:!"" = 20 !$" = 2 )Ω$% = 772 )Ω
EMITTER FEEDBACK BIAS CONFIGURATION
§ Contains emitter resistor to improve stability level over fixed-biased configuration.
EMITTER FEEDBACK BIAS CONFIGURATION
§ Consider the B-E circuit loop:
!"#" + %"& + !&#& − %(( = 0
where !& = !( + !" = +!" + !" = + + 1 !"!"#" + %"& + + + 1 !"#& − %(( = 0!" #" + + + 1 #& = %(( − %"&
!" =%(( − %"&
#" + + + 1 #&!( = +!"
EMITTER FEEDBACK BIAS CONFIGURATION
§ Consider the C-E circuit loop:!"#" + %"& + !&#& − %"" = 0
§ Substitute !& ≅ !"%"& = %"" − !"#" − !"#&%"& = %"" − !"(#" + #&)
Since %& = !&#&%"& = %" − %&
%" = %"& + %& or %" = %"" − !"#"
%-& = %- − %&%- = %-& + %&
EMITTER FEEDBACK BIAS CONFIGURATION
From:
!" =$%% − $"'
(" + * + 1 ('$%' = $%% − !%((% + (')
§ Aside from $"' , resistor (' is reflected back to input base circuit by factor * + 1 .
§ (' is part of C-E loop appears as * + 1 (' in B-E loop.
§ Because * is large value, (' appears great deal larger in base circuit.
(. = * + 1 ('
EMITTER FEEDBACK BIAS CONFIGURATION
§ DC Load Line analysis:!"# = !"" − &"((" + (#)
§ During saturation, &+ maximum à !"# ≈ 0 !∴ &"(/01) =
!""(" + (#
§ If !"# is small (not 0 V):
∴ &"(/01) =!"" − !"#(/01)(" + (#
§ During cutoff, &2 = 0, &" ≈ 0∴ !"# = !""
EXAMPLE
Determine:
a) #$b) #&c) (&)d) (&e) ()f) ($g) ($&
Answer:#$ = 40.125 56#& = 2.006 86(&) = 13.98 ((& = 15.98 (() = 2.006 (($ = 2.706 (
($& = −13.274 (
VOLTAGE-DIVIDER BIAS CONFIGURATION
§ Previous configuration !"# and $"%# were function of &.
§ But & is temperature sensitive and actual value is usually not well defined.
§ Desirable to develop a bias circuit that is less dependent or independent of &à voltage-divider bias configuration.
§ 2 method to analyze – exact method and approximate method.
VOLTAGE-DIVIDER BIAS CONFIGURATION –EXACT ANALYSIS§ Consider the B-E circuit loop using Thevenin equivalent network:
!"# = !% ∥ !' =!%!'!% + !'
)"# =!'*++!% + !'
VOLTAGE-DIVIDER BIAS CONFIGURATION –EXACT ANALYSIS§ Consider the B-E circuit loop:
!"#$% + '"( + !(#( − '$% = 0
where !( = !, + !" = -!" + !" = - + 1 !"!"#$% + '"( + - + 1 !"#( − '$% = 0!" #$% + - + 1 #( = '$% − '"(
!" ='$% − '"(
#$% + - + 1 #(!, = -!"
VOLTAGE-DIVIDER BIAS CONFIGURATION –EXACT ANALYSIS§ Consider the C-E circuit loop:
!"#" + %"& + !&#& − %"" = 0§ Substitute !& ≅ !"
%"& = %"" − !"#" − !"#&%"& = %"" − !"(#" + #&)
Since %& = !&#&%"& = %" − %&
%" = %"& + %& or %" = %"" − !"#"
%-& = %- − %&%- = %-& + %&
VOLTAGE-DIVIDER BIAS CONFIGURATION –EXACT ANALYSIS§ DC Load Line analysis:
!"# = !"" − &"((" + (#)§ During saturation, &+ maximum à !"# ≈ 0 !
∴ &"(/01) =!""
(" + (#§ If !"# is small (not 0 V):
∴ &"(/01) =!"" − !"#(/01)(" + (#
§ During cutoff, &2 = 0, &" ≈ 0∴ !"# = !""
VOLTAGE-DIVIDER BIAS CONFIGURATION –APPROXIMATE ANALYSIS§ Resistance !" is the equivalent resistance between base and ground for the transistor with !#.
§ Resistance between base and emitter: !" = % + 1 !# ≅ %!#§ If !" is much larger than !) à *+ much smaller than *) (current always seeks the path of least resistance) à *) ≈ *-§ If accept this approximation, *+ = 0à *) = *-à !- & !) can be considered series element.
0+ = 012 =!)033!- + !)
§ This approximation analysis only valid if 456 ≥ 895:
EXAMPLE
Determine the levels of !"# and $"%# for the voltage divider configuration using exact and approximate techniques.
Answer:Exact analysis:
!"# = 1.98 +,$"%# = 4.54 $
Approximate analysis:!"# = 2.59 +,$"%# = 0.388 $
COLLECTOR FEEDBACK CONFIGURATION
An improve level of stability can be obtained by introducing a feedback path from collector to base.
§ Consider the B-E circuit loop:!′#$# + !&$& + '&( + !($( − '## = 0
where !( = !# + !& = ,!& + !& = , + 1 !& ≅ ,!& ≅ !#Assume !′# ≅ !#
!#$# + !&$& + '&( + !#$( − '## = 0,!&$# + !&$& + '&( + ,!&$( − '## = 0!& $& + ,($# + $() = '## − '&(
!& ='## − '&(
$& + ,($# + $()
COLLECTOR FEEDBACK CONFIGURATION
COLLECTOR FEEDBACK CONFIGURATION
§ Consider the C-E circuit loop:!′#$# + &#' + !'$' − &## = 0
§ Substitute !' ≅ !# and !′# ≅ !#&#' = &## − !#$# − !#$'&#' = &## − !#($# + $')
Since &' = !'$'&#' = &# − &'
&# = &#' + &' or &# = &## − !#$#
&.' = &. − &'&. = &.' + &'
COLLECTOR FEEDBACK CONFIGURATION
§ DC Load Line analysis:!"# = !"" − &"((" + (#)
§ During saturation, &+ maximum à !"# ≈ 0 !∴ &"(/01) =
!""(" + (#
§ If !"# is small (not 0 V):
∴ &"(/01) =!"" − !"#(/01)(" + (#
§ During cutoff, &2 = 0, &" ≈ 0∴ !"# = !""
EXAMPLE
Determine the Q-point of !"# and $"%#
Answer:!"# = 1.07 +,$"%# = 3.69 $
EXAMPLE
Determine DC level of !" and #$ for the network.
Answer:!" = 35.5 )*#$ = 9.22 #
EMITTER BIAS CONFIGURATION
§ Emitter bias provides excellent bias stability in spite of changes in ! or temperature.
§ it uses both a positive and a negative supply voltage.
-
EMITTER BIAS CONFIGURATION
§ Consider the B-E circuit loop:
!"#" + %"& + !&#& − %&& = 0
where !& = !* + !" = +!" + !" = + + 1 !" ≅ +!" ≅ !*!"#" + %"& + + + 1 !"#& − %&& = 0!"[#"+ + + 1 #&] = %&& − %"&
!" =%&& − %"&
#" + + + 1 #&
EMITTER BIAS CONFIGURATION
§ Consider the C-E circuit loop:!"#" + %"& + !&#& − %&& − %"" = 0
§ Substitute !& ≅ !"!"#" + %"& + !"#& − %&& − %"" = 0!" #" + #& + %"& − %&& − %"" = 0%"& = %&& + %"" − !" #" + #&
§ Since %& = !&#& − %&&%"& = %" − %&
%" = %"& + %& or %" = %"" − !"#"
%+& = %+ − %&%+ = %+& + %&
EXAMPLE
Determine how much the Q-point (!" and #"$) for the circuit will change if %increases from 100 to 200.
COMMON COLLECTOR (EMITTER BIAS)
Determine !"#$ and %#$
Answer:%#$ = 4.16 +,!"#$ = 11.68 !
COMMON BASE
Determine:
a) #$b) #&c) ()$d) ()&
Answer:#$ = 2.75 01#& = 45.08 51()$ = 4.1 (()& = 3.51 (
PNP TRANSISTOR
§ The analysis for pnp transistor biasing circuits is the same as that for npn transistor circuits.
§ The only difference is that the currents are flowing in the opposite direction.
PNP TRANSISTOR
§ Consider the B-E circuit loop:
−"#$# − %#& − "&$& + %(( = 0
where "& = "( + "# = +"# + "# = + + 1 "#−"#$# − %#& − + + 1 "#$& + %(( = 0
%(( − %#& = "# $# + + + 1 $&
"# =%(( − %#&
$# + + + 1 $&
PNP TRANSISTOR
§Consider the C-E circuit loop:
−"#$# − %#& − "&$& + %## = 0
§ Substitute "& ≅ "#%#& = %## − "#$# − "#$&%#& = %## − "#($# + $&)
SUMMARY
§ The purpose of biasing a circuit is to establish a proper stable DC operating point (Q-point).
§The Q-point of a circuit is defined by specific values for !" and #"$ . These values are coordinates of Q-point.
§A DC load line passes through Q-point on a transistor’s collector curves intersecting the vertical axis at !"(&'() and the horizontal axis at #"$(*+(,--).§ The linear (active) operating region of a transistor lies along the load line below saturation and above cutoff.
§ There are many types of biasing such as voltage divider, emitter bias, base bias, emitter-feedback bias, collector-feedback bias, etc.