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1-bit nano CMOS full adder cell for energy efficient arithmetic applications

Design of Low Power ALU using Area Efficient Carry Select Adder



1.1 IntroductionDesign of any Low power VLSI circuit with less area and high speed has become a main concern for digital designers. Building low power VLSI systems has emerged as highly in demand because of the fast growing technology in mobile communications and computation. The battery technology does not advance at the same rate as microelectronics technology. There is a limited amount of power available for the mobile systems. So designers are faced with more constraints such as high speed, high throughput, small silicon area, and at the same time, low power consumption. So building low power, high performance adder cells are of great interest [1]-[5]. In the past few decades ago, the electronics industry has been experiencing an unprecedented spurt in growth, thanks to the use of integrated circuits in computing, telecommunications and consumer electronics. We have come a long way from the single transistor era in 1958 to the present day ULSI (Ultra Large Scale Integration) systems with more than 50 million transistors in a single chip [6].

As the performance of processors has increased, the demand for high speed arithmetic blocks has also increased. With clock frequencies approaching 1 GHz, arithmetic blocks must keep pace with the continued demand for more computational power. The purpose of this thesis is to present methods of implementing the area and power efficient carry select adder. To reduce the power and area requirements of the computational complexities, the size of transistors are shrunk into the deep sub-micron region [7] and predominantly handled by process engineering.

There are several Adder designs have been proposed to reduce the power consumption. Logic minimization not only results in better system throughput but also results in low power consumption designs. For low power results it is always advisable to use CMOS technology in which the power dissipation is a complex function of the gate delays, clock frequency, process parameters, circuit topology and structure, and the input vectors applied. Once the processing and structural parameters have been fixed, the measure of power dissipation is dominated by the switching activity (toggle count) of the circuit .The dynamic power is given by,P=1/2 * Cload * (Vdd2/Tcycle) * E(switching),

Where Cload is the load capacitance of the gate, Tcycle is the clock cycle time, E (switching) is the expected number of signal transitions per cycle and Vdd is the supply voltage [8].1.2 ObjectiveTo design a high speed Arithmetic Logic Unit (ALU) by using the efficient carry select adder. Adder is the important block in ALU, speed of the ALU is limited by the adder because it has to pass carry to more number of bits. In digital adders, for speed up the operation Ripple Carry Adder (RCA) is modified as CSLA. To achieve more speed CSLA is replaces by SQRT CSLA. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum [9]-[10]. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry input Cin=0 and Cin=1, the final sum and carry are selected by the multiplexers(mux) [11]-[15].1.2.1 Existing SQRT Carry Select AdderIn general the complete SQRT CSLA is divided into different blocks. Block size and the number of blocks depend upon the size of SQRT CSLA according to the SQRT technique. From second block onwards, each block contains three different levels, first level is ripple carry adder with input carry zero, second level is ripple carry adder with input carry one and the third level is multiplexer which is used to select one of the ripple carry adders output according to the previous block carry. The disadvantage in SQRT CSLA is more area requirement as it uses two levels of RCAs. For achieving better area efficiency [13]-[15] Binary to Excess-1 Converter (BEC) is replaced in the place of RCA with Cin=1 in the regular CSLA. To replace n bit RCA an n+1 bit BEC is required.Though BEC technique reduces area and power [16] but not up to considerable amount and also the design is not suitable for sub threshold level modifications. The drawback with this logic structure is that it does not reduce the area and power to a satisfactory level. There is still scope to reduce the delay. In order to reduce the power and area a new logic structure for a BEC is proposed.

1.2.2 Proposed SQRT Carry Select AdderThe 16-bit SQRT CSLA using BEC in its second level requires 792 transistors. There is a scope to reduce the number of transistors along with the area reduction and power dissipation reduction by using proposed logic. For the implementation of a 16-bit SQRT CSLA, 736 transistors are required by using proposed logic.The proposed logic implementation for second level RCA is Special Hardware using Multiplexers (SHM). In this the inputs are applied to first level RCA. And the output of RCA is applied to second level SHM and then to third level multiplexer. Third level multiplexer selects either RCA output or SHM output according to the previous carry.By using the proposed logic 8-bit Arithmetic Logic Unit (ALU) which performs arithmetic operations such as addition, subtraction, increment and decrement and logical operations such as AND, OR, XOR and XNOR is designed.1.3 Tools usedSOFTWARE:

Logic Editor: DSCH2.6c

Layout Editor: Micro wind 2.6a.The performance of the proposed design is analyzed. The simulations are performed with 120nm(0.12um) using simulation tool Microwind2, power supply of 1.2V and nominal temperature of 27C to extract the critical path delay and power consumption. 1.4 Thesis outlineThe next chapter describes literature survey such as different types of adders, different types low power design techniques in the design of low power ALU and different logic styles are analyzed.Existing design such as 8- bit ALU using ripple carry adders are designed in chapter 3 along with the implementation of SQRT CSLA using BEC technique.

Chapter 4 describes implementation of proposed SQRT CSLA and proposed ALU using efficient carry select adder.Comparative analysis and results are shown in the chapter 5.

Conclusion and future scope are discussed in chapter 6.CHAPTER 2LITERATURE SURVEY2.1 Introduction In nearly all digital IC designs today, the addition operation is one of the most essential and frequent operations. Instruction sets for DSPs and general purpose processors include at least one type of addition. Other instructions such as subtraction and multiplication employ addition in their operations, and their underlying hardware is similar if not identical to addition hardware. Often, an adder or multiple adders will be in the critical path of the design, hence the performance of a design will be often be limited by the performance of its adders. When looking at other attributes of a chip, such as area or power, the designer will find that the hardware for addition will be a large contributor to these areas. It is therefore beneficial to choose the correct adder to implement in a design because of the many factors it aspects in the overall chip. In this chapter we begin with the basic building blocks used for addition, then go through different algorithms and name their advantages and disadvantages. 2.2 Basic Adder Blocks 2.2.1 Half Adder

The half adder is an example of a simple, functional digital circuit built from two logic gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two bits (S) and the carry (C). Note how the same two inputs are directed to two different gates. The inputs to the XOR gate are also the inputs to the AND gate. The input "wires" to the XOR gate are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate, the A input to the AND gate receives the same voltage. 2.1


Fig.2.1 Half adder2.2.2 Full Adder In electronics, an adder is a digital circuit that performs addition of numbers. Full adders are fundamental units in various circuits, especially in circuits used for performing arithmetic operations such as compressors, comparators, parity checkers, and arithmetic logic units and so on. The full adder takes into account a carry input such that multiple adders can be used to add larger numbers. To remove ambiguity between the input and output carry lines, the carry in is labeled Cin while the carry out is labeled Cout. The full-adder circuit adds three one-bit binary numbers (Cin, A, B) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the circuit "above" itself in the cascade. The carry output from the full adder is fed to another full adder "below" itself in the cascade. Hence, a full adder is a digital circuit that performs an addition operation on three binary digits. The full adder produces a sum and carries value, which are both binary digits. It can be combined with other full adders or work on its own.

Fig.2.2 Schematic Symbol of 1-bit full-adder cell The final OR gate before the carry-out output may be replaced by an XOR gate without altering the re