Boston, MA, USA [ June 1 - 2, 2015 ]

Highly-Efficient Accelerators and Reconfigurable TechnologiesThe Sixth Internatioal Symposium on

http://www.isheart.orgFOURTH CALL FOR PAPERS

Software and applications:

FPGA Design Contest 2015

Important Dates (23:59:59, GMT):

Architectures and systems:

+ Novel applications of high-performance computing and Big-data processing with efficient acceleration and custom computing+ System software, compilers and programming languages for efficient acceleration systems / platforms, including many-core processors, GPUs / FPGAs / other reconfigurable /custom processors+ Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration+ Performance evaluation and analysis for efficient acceleration+ High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems

Following the FPGA design competition in HEART2014, we are planning another Blokus Duo design contest. The contest rules andregulations are posted on http://lut.eee.u-ryukyu.ac.jp/dc15/

March 6, 2015 (firm deadline) April 6, 2015 April 20, 2015June 1-2, 2015

Submission due : Author notification:Camera-ready due:Symposium dates :

The Sixth International Symposium onHighly Efficient Accelerators and ReconfigurableTechnologies (HEART) is a forum to present anddiscuss new research on accelerators and the use of reconfigurable technologies for high-performanceand/or power-efficient computation. Submissionsare solicited on a wide variety of topics related tothe acceleration for high-performance computation,including but not limited to:

+ Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices+ Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation+ Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing+ Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more+ Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices

March 10, 2015 April 1, 2015

April 15, 2015April 15, 2015

Regular paper due : Notification for regular papers:

Camera-ready due:Notification for abstract submission :

April 1, 2015Abstract due :

Technical Program Committee

Technical Program Co-ChairsJason Anderson, University of Toronto, CASuhaib Fahmy, Nanyang Technological University, SGWim Vanderbauwhede, University of Glasgow, UKPublicity Co-ChairsDavid Thomas, Imperial College London, UKYoshiki Yamaguchi, University of Tsukuba, JPPublication Co-ChairsYuichiro Shibata, Nagasaki University, JP

General Co-ChairsMartin Herbordt, Boston University, USAMiriam Leeser, Northeastern University, USA

Sai Rahul Chalamalasetti, Hewlett Packard, USRay C.C. Cheung, City University of Hong Kong, HKFlorent de Dinechin, INSA Lyon, FRDiana Goehringer, Ruhr-University Bochum, DEGary Grewal, University of Guelph, CAToshihiro Hanawa, University of Tokyo, JPYuko Hara-Azumi, Tokyo Institute of Technology, JPMasanori Hashimoto, Osaka University, JPBrad L. Hutchings, Brigham Young University, USTomonori Izumi, Ritsumeikan University, JPPeter Andrew Jamieson, Miami University, USNachiket Kapre, Nanyang Technological University, SGChristos Kartsaklis, Oak Ridge National Labs, USKenneth Kent, University of New Brunswick, CAJoo-Young Kim, Microsoft Research, USDirk Koch, University of Manchester, UKHerman Lam, University of Florida, USPhilip Leong, University of Sydney, AUTsutomu Maruyama, University of Tsukuba, JPSmail Niar, University of Valenciennes, FRGregory D. Peterson, University of Tennessee, USSoojung Ryu, Samsung Advanced Institute of Technology, KRKentaro Sano, Tohoku University, JPHayden Kwok-Hay So, University of Hong Kong, HKIoannis Sourdis, Chalmers University of Technology , SEHenry Styles, Xilinx, USBharat Sukhwani, IBM Thomas J. Watson Research Center, USHiroyuki Takizawa, Tohoku University, JPDavid Thomas, Imperial College, London, UKVivek Venugopal, United Technologies Research Center, USTao Wang, Peking University, CNYu Wang, Tsinghua University, CNMinoru Watanabe, Shizuoka University, JPStephan Wong, Delft University of Technology, NLYoshiki Yamaguchi, University of Tsukuba, JPMasato Yoshimi, University of Electro-Communications, JP

Vice ChairMartin Margala, UMass Lowell, US

Publication Co-Chairs

Yasunori Osana, University of the Ryukyus, JPJames Goebel, Boston University, US

Local ArrangementGabriella McNevin, Boston University, US