Brent Carlson, 2012 NRAO Synthesis Imaging Summer School Cross-correlators for Radio Astronomy ATP-NSI Brent Carlson, NRAO Synthesis Imaging Summer School

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<ul><li> Slide 1 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School Cross-correlators for Radio Astronomy ATP-NSI Brent Carlson, NRAO Synthesis Imaging Summer School 29 May 2012 </li> <li> Slide 2 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 2 Outline What is the purpose of the correlator? Simplified signal flow Basic correlator architectures -XF, FX, hybrid Technology -How do the electronics work The development process JVLA WIDAR correlator Now and the future </li> <li> Slide 3 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 3 Purpose To calculate the integrated cross-power response for each pair of antennas X and Y in the array over some integration time T. Statistically independent signals integrate down, whereas the common radio source signal establishes some power level and the uncertainty in that level integrates down. </li> <li> Slide 4 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School </li> <li> Slide 5 </li> <li> 5 Purpose These are the visibilitiesspatial Fourier componentsfor each baseline B in the u-v plane that are used to build the image. The fun begins: -As N increases, number of pairs of antennas goes as ~N 2 / 2. (e.g. JVLA has 27 antennas378 baselines (including auto correlations). -As bandwidth and number of (spectral) channels increases, the speed of the electronics increases along with power and cost. </li> <li> Slide 6 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 6 Purpose Analog correlators, operating on analog (continuous time) voltage signals have been built and do work But nowadays the analog signal is quantizedin time and amplitudeas soon as possible for stability and to take advantage of cheap high-speed digital electronics. -Once the signal is digitized there are no more unknown/unquantifiable effects (well, unless something broke) </li> <li> Slide 7 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 7 Simplified signal flow STEP #1: -Receive and amplify the signal from the antenna. The LNA adds significant noise to the weak signal, and must be optimized to optimize sensitivity of the telescope. Additive noise stability (or calibrated as such) here is important for stable correlator output. </li> <li> Slide 8 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 8 Simplified signal flow What does the signal look like? -Time domain (analog): </li> <li> Slide 9 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 9 Simplified signal flow STEP #2: -down-convert (mix) and filter the signalready for digital sampling. Gain fluctuations here not so critical as long as additive noise is stable. It is the ratio of radio source signal to system noise that is important. </li> <li> Slide 10 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 10 Simplified signal flow STEP #3: -quantize (digitize/sample) the signal. One of the most critical+difficult steps in the processing chain because it is where the quiet analog world meets the noisy digital world. Speed is important to maximize bandwidth. </li> <li> Slide 11 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School Flash A-to-D converter diagram. </li> <li> Slide 12 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 12 Simplified signal flow What does the signal look like? -Time domain (digital): </li> <li> Slide 13 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 13 Simplified signal flow Sampling: -Nyquist sampling theorem: must sample at least 2X the highest frequency content to obtain all information about the signal. If less, leads to aliasing (confusion). -With noise input: -1-bit results in ~35% sensitivity loss. -2-bit results in ~12% sensitivity loss. -3-bit: 3.5% -- JVLA wideband samplers -4-bit: 1.5% -- JVLA correlator internal samplers </li> <li> Slide 14 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 14 Simplified signal flow Sampling: -adding more bits/sample produces diminishing sensitivity returns for noise input and integrated output. -When narrowband interference is present, need more bits so as not to contaminate the spectrum with saturated sampler-generated harmonics. Get ~6 dB per bit dynamic range for a pure tone. dB=10log(x); if x is a power value. -For real-time signals (music/video) need lots of bits to accurately represent the real-time waveform (e.g. CD ~16-bit sampling=2 16 = 65,536 levels) </li> <li> Slide 15 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 15 Simplified signal flow STEP #4: -Correct for antenna-dependent wavefront delay. Two phases: 1)pure digital delay to +/-0.5 samples. Cheapest is to use memory. Get up to +/-90 deg phase changes at the upper edge of the bandsevere decorrelation, therefore need: 2)sub-sample delay to </li> <li> 38 Correlator architectures More on poly-phase FX: -If many channels ~&gt;1k required, must cascade filterbanks to avoid excessive numbers of poly-phase FIR taps (e.g. 1 stage 1Mchannels ~10Mtaps(!); 2 stage ~2k taps). -Each channel out of the FFT will have some leakage (aliasing) from the adjacent channel since it is critically sampled. -Therefore, must oversample the output. Performed by barrel-rolling the input across phases such that the output after FFT is oversampled. The next stage poly-phase-FFT of a particular channel will therefore not contain aliasing in regions of interest so that all taken together, clean alias-free spectra are obtained </li> <li> Slide 39 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 39 Correlator architectures See: Harris, Dick, Rice, Digital Receivers and Transmitters using Polyphase Filterbanks for Wireless Communications, IEEE transactions on microwave theory and techniques, Vol. 51, No. 4, April 2003. for more detail on poly-phase filterbanks (great paper!) </li> <li> Slide 40 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 40 Correlator architectures Hybrid FX-XF (a.k.a. FXF) -1 st stage: coarse filterbank (FIR or poly-phase FFT). -Useful as digital BBC for frequency-agile sub-band placement. -2 nd stage: XF. -Attractive as an efficient parallel processing method for wideband signals since no large multiplier operations are required (FIRs built with memory LUTs and adders). Has larger noise-power bandwidth in sub-band so can use fewer bits connecting to the X part. -JVLA and ALMA correlators built this way (some slight differences in implementations). Probably the last of this breed! </li> <li> Slide 41 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 41 Correlator architectures The actual signal processing operations are just one piece of the puzzle when putting a system together. Much of the logic and power in a system is consumed by transporting data around, synchronizing things, providing various modes of operation, error detection and recovery etc. Lets look under the hood of the electronics </li> <li> Slide 42 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 42 Technology It all starts with fundamental physicsbut moving up a level or two: -Transistor switch: the FET Field Effect Transistor. </li> <li> Slide 43 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 43 Technology N-MOS: applying a voltage to the Gate opens a conduction channel between the Drain and Source. P-MOS: applying a voltage to the Gate closes the conduction channel between the Source and the Drain. </li> <li> Slide 44 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School MOS: Metal Oxide Semi-conductor. MO is the insulator between the gate and the conduction channel. Extremely sensitive to electro-static discharge (ESD). When the transistor is ON or OFF, no current flows from the gate to the conduction channel (unless it is blown) Current (power) only flows when changing states, to charge/discharge the gate capacitancefaster state changes consumes more power. </li> <li> Slide 45 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School CMOS: Complementary Metal Oxide Semiconductor. Output changes faster since it is being driven both high and low. Small amount of leakage current (power) when the conduction channel is switching states. </li> <li> Slide 46 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School </li> <li> Slide 47 </li> <li> Slide 48 </li> <li> A 4-bit 2s complement multiplier F.A. (Full Adder) </li> <li> Slide 49 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 49 Technology A logic gate immediately reflects changes on its input to its output. It cant store a value. -A bunch of gates doing something is often referred to as combinational logic. A Flip-Flop transfers Data in to the output Data out only on the edge of its clock: A Flip-flop can therefore store a valuea single bit. A Flip-flop is actually a set of cross- coupled gates with feedback implementing an asynchronous Finite State Machine. </li> <li> Slide 50 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 50 Technology In digital electronics, pretty much everything is synchronous. i.e. changes occur on the clock edge all in step. -Its like a production linethe speed of the line is the clock speed and in each clock cycle each worker (bunch of gates doing some logic function) must get their step done before the next clock cycle starts. -As the clock speed increases, the logic workers must go faster to keep up. </li> <li> Slide 51 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 51 Technology Together (and in the millions/billions), Flip-flops and gates (along with memory cells) form the bulk of all digital electronics. As feature sizes (transistors) get smaller, more gates can be packed on a chip, they run faster, and more can be done. -JVLA correlator implemented with 90 nm and 130 nm devices (c. 2005). -Industry currently shipping 28 nm devices20 nm is next </li> <li> Slide 52 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School </li> <li> Slide 53 </li> <li> Slide 54 </li> <li> Slide 55 </li> <li> Slide 56 </li> <li> Slide 57 </li> <li> Slide 58 </li> <li> 58 Development process Fundamentally, engineering a system uses a hierarchical top-down approach: -Take a big problem, hierarchically break into smaller and smaller problems until each small problem can be solved by a human. -Then, put everything together, and it works! (eventually) In reality there are several rounds of iteration and engineering may start at any point in the hierarchy, iterate, iterateto eventually get a coherent picture to proceed with development. </li> <li> Slide 59 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 59 Development process In logic design, at the application level, we dont (or, rarely) design explicitly with gates and flip-flops. We write HDL Hardware Description Language code that describes logic in a high-level fashion. -And there are higher-level approaches as well. Can (optionally) use hierarchical graphical design tools as well to improve the humans ability to understand how it all fits together. </li> <li> Slide 60 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School </li> <li> Slide 61 </li> <li> Slide 62 </li> <li> 62 Development process In an HDL (VHDL, Verilog), all instructions are executed concurrently (i.e. on the clock edge), and so one must think concurrently when writing code. -If some output changes now, it isnt picked up until the next clock edge. -Seems impossible to have program flowbut we create that with pipelining and Finite State Machines. -Logic doesnt pop in and out of existence like functions/objectsit is always there and always active! </li> <li> Slide 63 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 63 Development process Synthesis and place and route software then compiles our HDL logic design to get implemented on our target device. -For an FPGA Field Programmable Gate Array, SRAM cells in the chip are downloaded at run time with the compiled program (firmware--bitstream) and set the chip to execute the program by setting connections/routes/use. -For an ASIC Application Specific Integrated Circuit, the compiled program is used to plunk down gates, flip-flops, and memory and connect them with wires in the design softwarewhich then gets built in a real chip foundry or fab. Wafers, die, </li> <li> Slide 64 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 64 JVLA WIDAR correlator Basic specs: -32 antennas, 8 GHz/polarization (in 2 GHz chunks 3-bit sampling; alternately 4 x 1 GHz 8-bit sampling). -128 independently tunable digital sub-bands; 128 MHz, 64 MHz, downto 31.25 kHz BW per sub-band. -Each sub-band can (will be able to) have a different delay center on the sky, within the antenna primary beam. -&gt;60 dB (10e6:1) spurious spectral dynamic range for high spectral puritywithin XF fundamental limitations. -16,384 to 4 million spectral channels per baseline </li> <li> Slide 65 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 65 JVLA WIDAR correlator Basic specs contd: -Recirculation provides a squared increase in spectral resolution with decrease in sub-band bandwidth. -Agile integration modes: normal, recirculation, pulsar phase binning, burst mode. -Able to flexibly tradeoff sub-band bandwidth for spectral resolution. -High time-resolution output; 10 msec minimum, 1 msec possible with 10G upgrade. -Phased-array output on all sub-bandsVDIF packets, and built-in autocorrelations. </li> <li> Slide 66 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 66 JVLA WIDAR correlator Basic specs contd: -Correlator configuration mapper translates high-level observing requests from the JVLA Executor, into detailed correlator configurations. -The config mapper gets away from mode-based observing, to goal-based observing. -Performs mapping in flexible ways to maximize packing of resources, or maximize real-time performance (short integration times) by spreading out operations amongst available resources. </li> <li> Slide 67 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School 67 JVLA WIDAR correlator Simplified signal processing: 1.Offset the LO in each antenna by a small amount. 2.Filter wideband sampled signals into integer sub-band slots (Stage 1)aliasing. (Other stages dont have the integer slot restriction.) 3.Remove LO offset and fringe phase in complex XF correlatorcausing aliasing to wash out with integration time. 4.Measure power before re-quantizer to allow wideband to be seamlessly stitched together from individually correlated sub-bands after correlation. </li> <li> Slide 68 </li> <li> Brent Carlson, 2012 NRAO Synthesis Imaging Summer School </li> <li> Slide 69 </li> <li> Slide 70 </li> <li> Slide 71 </li> <li> Slide 72 </li> <li> 72 JVLA WIDAR correlator Due to aliasing, there is a fa...</li></ul>

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