btu tpc electronics wbs 1.1 - indico.bnl.gov · 6/23 to 6/24/ 2016 annual btu tcsm review 1 btu tpc...
TRANSCRIPT
![Page 1: BTU TPC Electronics WBS 1.1 - indico.bnl.gov · 6/23 to 6/24/ 2016 Annual BTU TCSM Review 1 BTU TPC Electronics WBS 1.1.2 C. L. Britton K. F. Read D. Simpson Oak Ridge National Laboratory](https://reader030.vdocuments.net/reader030/viewer/2022040423/5e19d9a2baf8f8158270a36c/html5/thumbnails/1.jpg)
6/23to6/24/2016 AnnualBTUTCSMReview 1
BTUTPCElectronicsWBS1.1.2
C.L.BrittonK.F.ReadD.SimpsonOakRidgeNationalLaboratoryandUniversityofTennessee
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Outlineofthetalk
• SAMPA– MPW1tests– MPW2plan– MPW2status
• FECDesign– Finalarchitecture– Prototypestages– Rev0status
26/23to6/24/2016 AnnualBTUTCSMReview
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SAMPA
36/23to6/24/2016 AnnualBTUTCSMReview
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SAMPABlockDiagram
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5
SAMPAReadoutASIC• Designedat
UniversityofSaoPaulo,Brazil
• Processis0.13umTSMC
• ThisisacommonASICtobeusedwithinALICEbybothTPCandMCH.
• Chiphas311pins.
• Finalpackagewillbea372-BallGridArray(BGA)
(80nspeakingremoved)
6/23to6/24/2016 AnnualBTUTCSMReview
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SAMPAMPW1Tests
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ChipsfabricatedontheMPW1
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8
MPW1Linearity
6/23to6/24/2016 AnnualBTUTCSMReview
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MPW1Linearity
6/23to6/24/2016 AnnualBTUTCSMReview 9
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MPW1Noise
6/23to6/24/2016 AnnualBTUTCSMReview 10
Input Capacitance [pF]0 20 40 60 80 100 120
ENC
[e] -
fixe
d G
ain
0
500
1000
1500
2000
2500
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _
SimulationBR3CH2 - Neg - 1.25VBR3CH3 - Neg - 1.25VBR3CH5 - Neg - 1.25VBR3CH5 - Neg - 1.25VDub_CH1 - Neg - 1.25VDub_CH2 - Neg - 1.25VDub_CH3 - Neg - 1.25VDub_CH4 - Neg - 1.25VDub_CH5 - Neg - 1.25VBer_CH1 - Neg - 1.25VBer_CH2 - Neg - 1.25VBer_CH3 - Neg - 1.25VBer_CH4 - Neg - 1.25VBer_CH5 - Neg - 1.25VOrsay_CH2 Neg - _ _Orsay_CH3 Neg - _ _Orsay_CH4 Neg - _ _Orsay_CH5 Neg - _ _18.5pF
20mV/fC (Neg)
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TPCShapingtimemeasurement
6/23to6/24/2016 AnnualBTUTCSMReview 11
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12
SAMPAMPW2
6/23to6/24/2016 AnnualBTUTCSMReview
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SAMPAMPW2consistsofseveralASICs• Includesthefull32channelASIC• Testchip01– Fullshaper– SLVSTX/RX– Bias
• Testchip02– 32channelCSA/Shaper/buffer
• Testchip03– ADC
13
Diesize- 9533.6umx8943.6umPincount– 311,Ballcount- 372
6/23to6/24/2016 AnnualBTUTCSMReview
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Testchip01
146/23to6/24/2016 AnnualBTUTCSMReview
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Testchip02
156/23to6/24/2016 AnnualBTUTCSMReview
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Testchip03
166/23to6/24/2016 AnnualBTUTCSMReview
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SAMPASimulation• Afullsuiteof simulationsweredone invariousdomains• Duetocomputing limitations, theentirechipwasnotsimulatedasasingleentity• TheMPW2analogsectionhadextensiveoversightandrigorwithreviewand
monitoring byALICE,CERN,andORNLreviewers.– Appropriateduediligenceexercisedfordesign.– Extensive,superiorsimulationswereperformed.– Multipletestbenches usedtocheckdigitalcontrolfunctionality.
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Front-endplusADCsimulations(cont.)(Neg pol.,20mV/fC,160ns)
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Top-leveldigitaloutput.Fitincluded.
Mixed-signalSimulation.
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Front-endplusADCsimulations(Neg pol.,30mV/fC,160ns)
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Top-leveldigitaloutput.Fitincluded.
Mixed-signalSimulation.
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NoiseSimulations
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Thepreampnoisecanbeoptimizedatasingledetectorcapacitance
21
Iin
M1
M2
Cd
ToCascode
Improvesnoiseduetobothdrain-biastransistorandpower-supply
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NoiseSimulation(cont.)
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PSRRSimulations
23
TPCFECfilteringsimulation
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Linearitysimulations(postlayout)
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Crosstalksimulations
25
• Signalduetocrosstalkinadjacentchannellessthan~0.25%
• Nocrosstalkappearsinsecondchannels
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FECDesign
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TPCFECFinalReadoutArchitecture
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TheexistingTPCboardisoursizetemplate
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TheBeast
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Theinterconnectblockdiagramisrelativelystraightforward
• Allclocks,resets,sync,controlcomefromGBTx0
• GBTx1isonlyareceiverofdata
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Boardlayoutisproceeding• SAMPAlayoutand
connectorplacementhasbeentheprimaryfocus
• Thehigh-speedlineroutingispresentlyunderway
• An8-layersystemisourcurrentplan
• Mountingholesandcoolingtubeissameascurrentsystem
• Depthofboardwillincreaseby~0.6”
• Samepowerconnectorascurrent system
• Rev0willhavedetachable inputcables
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PrototypingStages• Rev0– Theinitialdesign– Schematiccapture
• DoneinCadenceAllegro/Orcad 16.6• Designwasreviewedpriortolayout
– Layout• DannySimpson,OutsidelayoutengineerusedbyORNL.• UsingCadenceAllegrolayout• Layoutwillbereviewedbythecollaborationandrevised.• Rev.0rigid-onlyPCBhasthesebenefits:
– domesticonly(nocustoms)– fastestpossible turn-around– lowestcostfabforprototyping
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Technicalapproach/challenges
• Rev0(cont.)– Layout(cont.)
• Wehadplannedtoutilizeflexcable forthedetectorinputsbutthecostandturnaroundwastoohigh
• WeareusingdetachablecableswithERNIconnectorsforthedetectorconnection
– Fabricate• Wewillfabricateupto20oftheboards• 15willbeusedfordetectortest• Thesewillbedistributedtocollaboratorsfortesting
• Rev1willrepeatthecycleaftertestresultshavebeenreceivedandreviewed
• Rev1awillbethefinalpre-productiondesign
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Technicalapproach
• CERNrequiresHalogen-Freematerialfortheboards
• Ourregularassemblyhousecansupplythis
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ProductionPlan&QA/QC(consistentwithtestingrequirementsandacceptance)
• AcceptancetestsoutlinedinALICEBarrelTrackingUpgradeProjectManagementPlan(DocumentBTU.1.v4)
• TeststandsusingCRUwillbedeveloped• Vendorevaluationhasstarted• Fiverunswillbeusedtoaccomplishtheproduction
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36
• BTU.9HazardAnalysisDocument:• Describespotentialhazards
andmitigationforTPCFEC• Sealedlowvoltagepower
supplies• Soldering,leadsolder• Workershavetakenrequired
safetytraining (electricalsafety,chemicalsafety,PPE).
• Example:FEClabposting• BTU.8ES&HManagementPlan
• FollowsORNLES&Hpolicies• Periodicon-sitesafety
reviews
HazardAnalysis&Mitigation
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NOTICENOTICENOTICENOTICEAUTHORIZED PERSONNEL ONLYAUTHORIZED PERSONNEL ONLYAUTHORIZED PERSONNEL ONLYAUTHORIZED PERSONNEL ONLY
See Access Requirements for DetailsSee Access Requirements for DetailsSee Access Requirements for DetailsSee Access Requirements for Details
Space Function BLDG/RMLaboratory 1, Dry 6000/211
HAZARD WARNINGS
Access RequirementsUnescorted access to Building 6000 is granted upon completion offacility specific access training.
Obey Radiological Postings.
PPE required for work with chemicals, power tools, soldering, orperforming work on or near electrical work.
Research Support Group Leader Charlie Havener, 574-4704, Bldg 6000Room 250A and Division Director David Dean 576-5229
CONTACTS NAME PHONE OFFICESpace ManagerSpace Group LeaderComplex Facility ManagerFacility Operations Manager
Kenneth Read Jr 574-5347 6000 Room 219Thomas Cormier 574-9998 6000 Room 213Richard Griffey 574-8907 5700 Room J103B Tatum 574-4759 6000 Room 203
LAST REVISION: 9/2/2015 (1)
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Summary
• MPW1testingrevealedmanyissues• Test-campaigndeficienciesforMPW1havebeenwelladdressed
• MPW2appearstohavebeenwellsimulated(butnotcompletechip)
• TheRev0FEChaspresentedseveralchallenges,primarilycost
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Backupslides
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FECTestStation
pulsegenerator
• TestingcriteriasummarizedinAppendixA.2ofBTU.1.v8.• Canpulsedifferentselectedpatternsofinputchannels.• WillinitiallyuseC-RORCFPGAboarduntilCRUbecomesavailableinlater2016.
• FECteststationdevelopedforAugust2016willbeimprovedandusedformassFECtestinginearly2019.
PCwithCRU(initiallyC-RORC)optical
fibers
FECchannelpatternboard
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FECTestingMatrix
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Pulser SAMPA GTBx C-RORC
Link Check - RX/TX PG
Pattern from Ped.Mem (DSP) - TRIGGERED
Alignment Check by Peak-Matching - CONTINOUS
PC
Pulse Analysis - CONTINUOUS with Selection-Window (Pre-/Post-Samples)
Pattern from Ped.Mem (DSP) - TRIGGERED
Alignment Check by Peak-Matching - CONTINOUS
SlowControl Check (SCA)Check Fibre and GBTx
connectivity
Check SAMPA and GBTxconnectivity
Check Raw ADCAlignment
(Reset/Sync)
Full Validation ofCSA & Shaper
& Noise
Purpose