buck regulator architectures
DESCRIPTION
Buck Regulator Architectures. 4.6 Voltage Mode Buck Regulators. Voltage-Mode Regulator. Output Filter. Modulator. Error Amplifier. Advantages and Disadvantages. Advantages Stable modulation/less sensitive to noise Single feedback path Can work over a wide range of duty cycles - PowerPoint PPT PresentationTRANSCRIPT
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Buck Regulator Architectures
4.6 Voltage Mode Buck Regulators
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Voltage-Mode Regulator
2
VIN
COUT
RESR
RLOAD
L
RFB1
RFB2
VOUT
VREF
VFB
VP
ZC
+
-+
-T
VC
Output Filter
Error Amplifier
Modulator
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Advantages and Disadvantages• Advantages
– Stable modulation/less sensitive to noise– Single feedback path– Can work over a wide range of duty cycles
• Disadvantages– Loop gain proportional to VIN
– LC double pole often drives Type III compensation– CCM and DCM differences - a compensation challenge– Slow response to input voltage changes– Current limiting must be done separately
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Modulator Gain
4
VIN
VSW
+
-
T VRAMP
VP
VC
VC
P
INM V
VA
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Output Filter
5
CO
RESR
RLOAD
LVOUTVSW
ZA
ZB
BA
B
SW
OUT
ZZZ
VV
* (Rx, Cy) indicate the components that drive the locations of the pole and the zero, detailed equations are in the notes
-40
-20
0
20
40
10 100 1,000 10,000 100,000 1,000,000
o
ESR
dB
Hz
(L, Co)
(Resr, Co)
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Error Amplifier
The easiest place to compensate the entire loop is to adjust the compensation around the error amplifier. Several different approaches are possible.
6
RFB2VREF
VFB
ZF
+
-
VOUT
VC
ZI
I
F
OUT
C
ZZ
VV
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Type II Compensation
7
RFB2
RFB1VREF
VFB
+
-
VOUT
VC
RCCC1
CC2ZF ZI
I
F
OUT
C
ZZ
VV
* (Rx, Cy) indicate the components that drive the locations of the pole and the zero (and k), detailed equations are in the notes
-20
0
20
40
60
10 100 1,000 10,000 100,000 1,000,000
pz k
ZF - ZI
dB
Hz
(Rc, Cc1) (Rc, Cc2)(Rc, RFB2)
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Design Guidelines for Type II Compensation• Choose a large value for RFB2, between 2-200 kW• Set the mid-band gain k to give desired bandwidth• Set P equal to half the switching frequency:
P = 2p*Fsw/2
• Set z equal to the output filter double pole O
• Use the following equations to solve for the remaining variables
8
CPC2 Rω
1C Cz
C1 Rω1C FB2C kRR
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Type III Compensation
9
RFB2
RFB1VREF
VFB
+
-
VOUT
VC
RC1CC1
CC2
CC3
RC2
ZFZI
I
F
OUT
C
ZZ
VV
* (Rx, Cy) indicate the components that drive the locations of the poles and zeros, detailed equations are in the notes
-20
0
20
40
60
10 100 1,000 10,000 100,000 1,000,000
1P1z
k
2P
2z
dB
Hz
(Rc1, Cc1)
(RFB2, Cc3)
(Rc1, Cc2) (Rc2, Cc3)
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Design Guidelines for Type III Compensation• Choose a large value for RFB2, between 2-200 kW• Set the mid-band gain k to shift the open-loop gain up to give desired
bandwidth• Set P1 equal to half the switching frequency:
P1 = 2p * Fsw/2
• Set P2 equal to the output filter zero, ESR
• Set Z1 and Z2 equal to cancel out the output filter double pole
• Use the following equations to solve for the remaining variables
10
FB2Z2C3 Rω
1C C3P2
C2 Cω1R
FB2C1 kRR
3
C1Z1
FB2Z2C1 Rω
RωC cC
C1P1C2 Rω
1C
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Internal Type III Voltage Mode Compensation (LM367x)
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Typical Application CircuitInternal Block Diagram
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Internal Type III Voltage Mode Compensation (LM285x)
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PVINAVINENSSSGND PGND
SNS
SW
LM2852/3
+
Lo
Co
VIN = 3.3V
CIN VOUT = 2.5 V
Ramp and Clock
Generator
EN
PVIN
Gate Drive SW
PGND
Error Amp
PWM Comp
OscillatorReference
UVLO DAC
Zc2
400 kW
200
kW
200
kW
20 pF
Current Limit
+
-
+
-
Zc1
SNS
SS
Internally Compensated
Typical Application CircuitInternal Block Diagram
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Thank you!