Sampler for Neutrino Telescope

By: Uriel BarronMatan Schlanger

Supervisor: Mony Orbach

Final Review

March 2015

Large Neutrino detector at the South Pole

A collaboration of 11 universities worldwide

Detection of short, extremely weak RF pulsesover an area of 100km2

ARA- Askaryan Radio Array

ARA- Askaryan Radio Array

High Bandwidth (~850 MHz), rare (once every few months) and short (~100 ns) pulses

Strong price sensitivity – At least 37 stations, high frequency samplers cost thousands of dollars per channel

Power consumption requirements (~2W)– limited power at the South Pole

Sample 4 channels with one board

The Problem

The Problem

LABRADOR – basic digitizing board for the ARA test bed, only 1 GSPS

IRS (Ice Radio Sampler) – series of ASICs created for the DDA

Best so far – IRS2, which can sample in 4 GSPS, but has a long dead time

Previous Attempts

Design and simulate a low-cost sampler for high frequency short pulses, with low power consumption

Design will include BOM, electronic schematics, layers design and Gerber files

Our Goal

Input: 4 stabilized, analog signals, via SMA connectors. Bandwidth:

Output: 4 12-bit digitized signals, via QSE connectors

Programmable sampling speed, supports1.7 GSPS to 3.2 GSPS sampling

Maximum power consumption – 2W Fully operational in Voltage Supply – 3.3V

Main Specifications

Dead time < 1ms Build-in EEPROM and temperature sensor Standby power consumption < 1W Low cost (exact price isn’t specified)

Secondary Specifications

Using a DRS4 Domino Wave Circuit to quickly save analogously ~2000 sample per channel

Instead of continuous high-frequency sampling, using regular ADCs

All components are on-the-shelf and significantly cheaper than high-frequency samplers.

The Solution

Block Diagram

Using the domino effect to save analog high-frequency signals, and later digitize them slowly

Contains 8 channels, each channel can save up to 1024 samples

Supports cascading of channels

Sample speed is up to 5 GSPS

The DRS4

The DRS4

DRS4 analog input requirements: 1. common mode2. Differential mode of 3. Absolute voltage of Problem: We have common mode with Solution: We will add offset and attenuate

the signal The input of the DRS4 will be constant at

the positive input’s offset

Input Circuit

Input Circuit

Input Circuit

We have a little distortion, but…

Input Circuit

In passband, maximum distortion is .We will deal with it together with the DRS4’s frequency response

Input Circuit

The input circuit works well, and consumes 7.5mW per channel, which yield 30mW total power consumption.

The DRS4’s clock has an internal x2048 frequency multiplier

We need a programmable clock around

Two approaches: A built-in programmable clock or a voltage-controlled oscillator with a DAC

Programmable Clock

Output can be varied from 1KHz to 68 MHz Near the wanted frequency, it has a

resolution of 1.1KHz, which means 2.2 MHz sampling speed resolution

Simple to use ( interface) and low power (few mW)

3.3V output, so we use a voltage divider to get output voltage of

Programmable Clock – LTC6904

Recommended in the DRS4’s datasheet, because the DRS4’s output can be connected directly to the AD9222 inputs

8 channels, can shut down each channels to reduce the power dissipation to virtually 0 with short waking-up time

12-bit, serial outputs

ADC – AD9222

Used 24LC32A EEPROM and TMP-100EP temperature sensor

Same as in the DDA boards Both use interface and 3.3V power supply

Peripheral Components

3 Supply voltages:1. 3.3V – Clock and peripheral components2. 2.5V – DRS43. 1.8V – ADCWe will use regulators to get 2.5V and 1.8V Total power dissipation of 300mW when

idle, about 720mW during sampling bursts

Components Summary

Backward compatibility – QSE connectors location is fixed, SMA connectors on the other side

DRS4 and ADC – according to design flow Clock – near the DRS4’s clock input Peripheral components and regulators –

wherever convenient

Placement

Placement

Filters Regulators

Clock

EEPROMTemperature

Sensor

Main goal – shield the vulnerable analog signals from any external noises or crosstalk with digital signals

We will use 8 layers, since there’s no strict limit over the cost, and we can get better performances

This makes much room for shielding using fully conductive layers (power and ground)

Layers Order

1. Top – 1.8V and some wires near components

2. Analog Data3. Analog Ground4. Mixed data – general use5. 2.5V – both analog and digital6. Digital Ground7. Digital Data8. Bottom – mostly connectors

Layers Order

Layers Order

Most important – isolating analog signals from any noise

This means using mixed data for analog signals only when there is no other option

Another consideration – length of analog signals, differential pairs and clock-data pairs should be the same

Routing

Routing

Top, Analog, Mixed, Digital

Routing - Top

Routing - Analog

Routing - Mixed

Routing - Digital

We managed to make an almost complete separation between analog and digital layers.

Therefore, we can change the layers order to get an even better isolation

No crosstalk between analog and digital signals

Differences in analog lines’ length is completely negligible

Routing

We used only reliable on-the-shelf products 900 MSPS to 5 GSPS sampling speed Approximate power consumption of 300mW

when idle, 720mW during sampling bursts Strong shielding of analog signals Approximate cost of 216$, instead of 8000$ Dead time: 66μs

Summary

Better input circuit with op-amps Reduce to 6 layers board Use advanced readout modes to reduce

dead time Integrate 2 DRS4s Adapt the DRS5

Further Development

Any Questions?