ca the memory system

8/3/2019 CA The Memory System

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Fundamental of Computer Architecture

By Panyayot Chaikan [email protected]

240-208

November 01, 2003


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Chapter 4 - The Memory System 2240-208 Fundamental of Computer Architecture

Chapter 4

The Memory System


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Connection of the memory to the CPU

MAR

MDR

Memory

Up to 2 addressablelocations

k

word length= n bitsCU

k-bit address bus

n-bit data bus

Control lines

Processor


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Organization of bit cells in a memory chip

From Figure 5.2 Page 296 of Computer Organization, Carl Hamacher, 5th

edition, McGraw Hill pub.


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Organization of a 1Kx1 memory chip

From Figure 5.3 Page 297 of Computer Organization, Carl Hamacher, 5th edition, McGraw Hill pub.


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Semiconductor Memories

Nonvolatile memory

ROM

PROM

EPROM

EEPROM

Flash memory

Volatile memory

SRAM

DRAM

Asynchronous

DRAM

FPM DRAM

Synchronous

SDRAM

DDR SDRAM

RDRAM


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ROM

ROM : Read Only Memory

Programmed when manufacturing is in process.

PROM : Programmable Read Only Memory

Programmable by user only once

Flexible and convenient compared to ROM

Programmed by burning the fuse using high current

pulse


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A simple 4-word ROM

From Figure 11-12 Page 298 of Microprocessors: principles and applications, Charles M.Gilmore, McGraw Hill pub.


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A simple 4-word ROM using MOS

From Figure 11-13 Page 299 of Microprocessors: principles and applications, Charles M.Gilmore, McGraw Hill pub.


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EEPROM

Electrically Erasable PROM

No requirement of physically removed from the

circuit for reprogramming

Use special voltage level to erase data

Any cell contents can be delete selectively


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EPROM

Reprogrammable

Erased by UV light

Example EPROM chips

27C64 : 8KB

27C128 : 16KB

27C256 : 32KB

27C512 : 64KB


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EPROM 2764, 27128, 27256

From Figure 11-15, Page 301 of Microprocessor : Principle and Application, Charles M. Gilmore, McGraw Hill pub.


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Flash Memory

Electrically erasable

Single cell can be read but can be written only an

entire block of cells.

Prior to writing, the previous of the block are

erased.

Suitable for used as solid state disk such as

CompactFlash, MemoryStick, SD, MD etc.


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SRAM cell

Vsupply

word line

bit line

b'

bit line

b


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DRAM cell

word line

bit line


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SRAM VS DRAM

SRAM

Very fast

Very Expensive

Used in Cache memory

and CPU register

DRAM

Slower than SRAM

Cheaper than SRAM

Used in most computer

as main memory

Need to be refreshed

periodically


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DRAM: Multiplexed Row-Column addressing



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Reducing Address pins of IC chip

RAS = Row Address Strobe

CAS = Column Address Strobe

DRAM: Multiplexed Row-Column addressing


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Static RAM

2Kx8 8Kx8



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Dynamic RAMchip: Example



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Memory Module

From www.oamao.com/Matos/ ordi/guide.htm


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3 Types of RAM modules

FROM http://www.buycomputermemory.com/computer-memory-types-and-memory-technology.html


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Internal organization of a 2Mx8 DRAM




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SDRAM

Synchronous DRAM

Need clock signal for synchronize operation

Can be used with clock speed 100 and 133 MHz

Built in refresh circuitry


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Structure of Synchronous DRAM




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Burst read of length 4 in an SDRAM



Row

Col

D0


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The use of Memory controller

Memory

Memory

Controller

Row/ColumnaddressAddress

data

Processor

Clock

R/W

CS

CAS

RASR/W

Request

Clock


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The role of Memory controller

Is the North-bridge chip in typical PC

Activate/Deactivate signal RAS and CAS timing

for DRAM

Interposed between Processor and Memory

Refresh DRAM if required


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Memory organization in typical PC

From http://www.via.com.tw/en/p4-series/pt800.jsp


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Memory organization in typical PC

From http://www.via.com.tw/en/p4-series/pt880.jsp


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Memory hierarchy

Processor

Registers

Cache L1

Cache L2

Mainmemory

secondarystoragememory

increasingsize

increasingspeed

increasingcost per bit

ca the memory system

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