cad for vlsi circuits 2.pdf

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Reg. No. : M.E. DEGREE EXAMINATION, JUNE 2010 Second Semester VLSI Design VL9221 – CAD FOR VLSI CIRCUITS (Common to M.E. Applied Electronics) (Regulation 2009) Time : Three hours Maximum : 100 Marks Answer ALL Questions PART A — (10 × 2 = 20 Marks) 1. When is a problem said to be NP-complete? 2. Distinguish between behavioral and structural design domains. 3. What is meant by layout compaction? 4. Compare standard cell placement and building block placement problems. 5. What are the objectives of floor planning? 6. Distinguish between local and global routing. 7. State the importance of Binary decision diagram. 8. What is the role of logic synthesis in VLSI design? 9. Give the differences between assignment and allocation. 10. Define high level synthesis. Question Paper Code: J7795

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Page 1: CAD FOR VLSI CIRCUITS 2.pdf

Reg. No. :

M.E. DEGREE EXAMINATION, JUNE 2010

Second Semester

VLSI Design

VL9221 – CAD FOR VLSI CIRCUITS

(Common to M.E. Applied Electronics)

(Regulation 2009)

Time : Three hours Maximum : 100 Marks

Answer ALL Questions

PART A — (10 × 2 = 20 Marks)

1. When is a problem said to be NP-complete?

2. Distinguish between behavioral and structural design domains.

3. What is meant by layout compaction?

4. Compare standard cell placement and building block placement problems.

5. What are the objectives of floor planning?

6. Distinguish between local and global routing.

7. State the importance of Binary decision diagram.

8. What is the role of logic synthesis in VLSI design?

9. Give the differences between assignment and allocation.

10. Define high level synthesis.

Question Paper Code: J7795

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Page 2: CAD FOR VLSI CIRCUITS 2.pdf

J7795 2

PART B — (5 × 16 = 80 Marks)

11. (a) (i) Explain the Prim’s algorithm for spanning trees with necessary

pseudocode. (8)

(ii) Write down the pseudocode and discuss briefly the principle of Tabu

search. (8)

Or

(b) (i) Explain the concepts of linear programming with suitable

expressions. (10)

(ii) Describe simulated annealing with a pseudocode. (6)

12. (a) (i) Explain the Bellman Ford algorithm for constraint graph

compaction. (8)

(ii) Discuss the applications of Genetic algorithm in VLSI placement. (8)

Or

(b) (i) Describe the Kernighan-Lin partitioning algorithm with pseudocode

and necessary diagrams. (10)

(ii) Draw the bipartite and tripartite graph models of RS latch and

explain briefly. Explain them. (6)

13. (a) Write short notes on :

(i) Shape functions and floor plan sizing. (8)

(ii) Area routing. (8)

Or

(b) (i) Discuss the construction of rectilinear Steiner trees. (8)

(ii) Give a brief account on channel routing (8)

14. (a) (i) Explain event driven simulation and its applications. (8)

(ii) Explain briefly switch level simulation. (8)

Or

(b) (i) Explain the principle and implementation of ROBDD. (8)

(ii) Give a brief note on two level logic syntheses. (8)

15. (a) Explain any two scheduling algorithms in detail. (16)

Or

(b) (i) Write a brief note on high level transformations. (8)

(ii) Discuss the different sub problems of assignment problem. (8)

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