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PART A1. When is a problem said to be NP-complete?2. Distinguish between behavioral and structural design domains.3. What is meant by layout compaction?4. Compare standard cell placement and building block placement problems.

5. What are the objectives of floor planning?6. Distinguish between local and global routing.7. State the importance of Binary decision diagram.8. What is the role of logic synthesis in VLSI design?9. Give the differences between assignment and allocation.10. Define high level synthesis.

1. What are the entities to be considered for optimisation in VLSI Design?2. Differentiate sea of gates design and field programmable gate array design.3. What is the need for layout design rules?4. What are the objectives of partitioning?5. Draw the wheel floor plan diagram.6. What are the different metrics used to estimate wirelength?

7. Draw the ROBDD for the function F m(0,1,4,5,6) .8. How a signal is modeled during gate level simulation?9. List any two scheduling algorithms used in high level synthesis.10. What are assignments and allocations in high level synthesis.

PART B

11. (a) (i) Explain the Prims algorithm for spanning trees with necessary pseudocode. (8)(ii) Write down the pseudocode and discuss briefly the principle of Tabu search. (8)Or(b) (i) Explain the concepts of linear programming with suitable expressions. (10)(ii) Describe simulated annealing with a pseudocode. (6)

12. (a) (i) Explain the Bellman Ford algorithm for constraint graph compaction. (8)(ii) Discuss the applications of Genetic algorithm in VLSI placement. (8)Or(b) (i) Describe the Kernighan-Lin partitioning algorithm with pseudocode and necessary diagrams.(10)(ii) Draw the bipartite and tripartite graph models of RS latch and explain briefly. Explain them. (6)13. (a) Write short notes on :(i) Shape functions and floor plan sizing. (8)(ii) Area routing. (8)Or(b) (i) Discuss the construction of rectilinear Steiner trees. (8)(ii) Give a brief account on channel routing (8)14. (a) (i) Explain event driven simulation and its applications. (8)(ii) Explain briefly switch level simulation. (8)Or(b) (i) Explain the principle and implementation of ROBDD. (8)(ii) Give a brief note on two level logic syntheses. (8)15. (a) Explain any two scheduling algorithms in detail. (16)Or(b) (i) Write a brief note on high level transformations. (8)(ii) Discuss the different sub problems of assignment problem. (8)

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11. (a) (i) Explain depth-first search algorithm with an example and alsowrite the pseudocode of it. (10)(ii) Discuss on the three domains in Gajski's Y Chart. (6)Or

(b) (i) Discuss on the VLSI design automation tools. (10)(ii) Explain Breadth first search with an example. (6)12. (a) (i) How partitioning is done using Kernighan-Lin algorithm? (8)(ii) Using KL algorithm find two way partitioning for the graph shownin Fig. 1 (initially take nodes 1,2,3 in set A and 4,5,6 in set B). (8)

Or(b) What are the constraints in placement problem and explain theplacement algorithm based on partitioning with an example. (16)13. (a) What is the used of shape functions in floor planning and explain various optimisationproblems in floor planning? (16)Or(b) (i) What is area routing? How does it differ from channel routing? (6)(ii) Explain left edge algorithm and show how it is used in channel routing with an example. (10)14. (a) (i) Explain compiler driven simulation with an example. (8)(ii) Discuss the date structure used to describe switch level simulation algorithm. (8)Or(b) (i) List and explain the steps used in two level logic optimisation. (8)(ii) With Shannon's expansion theorem expand the given function with respect to A. Z= AB + A' + AC. (8)15. (a) What is data flow diagram? Explain the various units of data flow diagram with examples.(16)Or(b) Describe the ASAP scheduling algorithm and explain the role of it in high level synthesis. 16)