calvin college - engineering department analog design spring 2002 engineering 332
DESCRIPTION
Calvin College - Engineering Department Analog Design Spring 2002 Engineering 332. Professor: Paulo F. Ribeiro, SB130 X6407, [email protected] Textbook: Sedra / Smith, Microelectronic Circuits, Fourth Edition Lectures: 12:30-1:20PM (MWF) SB203 - PowerPoint PPT PresentationTRANSCRIPT
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Calvin College - Engineering DepartmentAnalog Design
Spring 2002
Engineering 332
Professor: Paulo F. Ribeiro, SB130 X6407, [email protected]
Textbook: Sedra / Smith, Microelectronic Circuits, Fourth Edition
Lectures: 12:30-1:20PM (MWF) SB203
Laboratory (Wednesdays 1:30-4:20 PM) SB 136 and SB28
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Course objectives To focus on the design of amplifiers, filters, oscillators, and converters with an emphasis on design.
Topics covered Differential and Multistage Amplifiers, Frequency Response, Feedback, Output Stages, Analog Integrated Circuits (741), Filters and Tuned Amplifiers, Signal Generators.
Class/laboratory schedule 2-3 lectures per week plus 3-hour laboratory.Contribution of course to meeting the professional component This course contributes primarily to the students' knowledge of engineering topics, and does provide design experience.
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Relationship of course to undergraduate degree program objectives
This course primarily serves students in the department. The information below describes how the course contributes to the undergraduate program objectives. Mastery of specific technical design skills which are key to a wide range of electrical engineering applications. Mastery and critical evaluation of the use of computer aided simulation tools (SPICE) as an engineering design aid.
Assessment of student progress toward course objectives Student's design skills is assessed primarily on detailed homework and design problems that involve the use of analytical and simulation tools such as PSPICE.
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Schedule
Topics Chapter # of classes
Differential and Multistage Amplifiers 6 6
Frequency Response 7 6
Feedback 8 6
Output Stages 9 6
Analog Integrated Circuits (741) 10 3
Filters and Tuned Amplifiers 11 3
Signal Generators 12 3
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Design Part I: Chapters 6, 7
Design Part II: Chapters 8, 9, 10
Final Design: Chapter 11, 12
Spring Break March 9-18
Reading Recess April 16-17 GradingDesign Part I 20% Design Part II 20% Labs 15%Homework and Assignments 15% Participation 10%Final Design 20% 100%
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Lab Schedule:
Lab 1 – The BJT Differential Pair and Amplifications
Lab 2 – Single-BJT Amplifiers at Low and High Frequencies
Lab 3 – Principles of Feedback Using and Op-AMP Building Block
Lab 4 – Basic Output-Stage Topologies
Lab 5 – OP-AMP-RC Filter Topologies
Lab 6 – Waveform Generators
Extra Lab – Power Supply
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Basic Homework Assignments (Minimum List)Students are recommended to work out most of the problems in the back of each assigned chapter.Additional Interactive Examples from accompanying CD and design problems will also be required to becompleted.
Chapter Problems Observations6 6.1, 6.5, 6.15, 6.19, 6.33, 6.42, 6.50, 6.70, 6.77, 6.87, 6.97, 6.113 Choose 107 7.1, 7.7, 7.11, 7.26, 7.28, 7.38, 7.57, 7.67, 7.73, 7.85 Choose 88 8.1, 8.8, 8.16, 8.20, 8.32, 8.48, 8.52, 8.719 9.4, 9.14, 9.18, 9.22, 9.32, 9.37, 9.45, 9.5110 Detailed Analysis of the 741 OP-AMP11 Analysis of A Second Order Active Filter12 Analysis of the Wien Bridge Oscillator
All laboratory and homework exercises must be turned in on time for full credit. Late assignments will beassigned a penalty. Assignments more than one week late may be assigned a 50% penalty.Homework and lab assignments should be prepared electronically (Word, MathCAD,PSpice, MATLAB / Simulink, PSCAD, etc.). No handwritten assignments will beaccepted.
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Differential and Multistage Amplifiers
The most widely used circuit building block in analog integrated circuits.
Use BJTs, MOSFETS and MESFETs (metal semiconductor FET – read 5.12 – Gallium Arsenide-GaAs Device).
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The BJT Differential Pair
Use CD
Implemented by a transistor circuit
Connection to RC not essential to the operation
Essential that Q1 and Q2 never enter saturation
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Different Modes of Operation
Differential pair with a common-mode input
Common voltage
I/2
vE = vCM-VBE
vC1 = VCC – ( ½) I RC
vC2 = VCC – ( ½) I RC
vC1 – vC2 = ?
Vary vCM (what happens?)
Rejects common-mode
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Differential pair with a large differential input
Different Modes of Operation
vB1 = +1
Q1
Q2
vE = 0.3
Keeps Q2 off
vC1 = VCC - I RC
vC2 = VCC
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Differential pair with a large differential input o opposite polarityTo that of (b)
Different Modes of Operation
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Differential pair with a small differential input
Different Modes of Operation
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Exercise 6.1
5 0.71
4.3 vE 0.7
vC2 5 4.3 1 vC2 0.7
vC1 5
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Large-Signal Operation of the BJT Differential Pair
Equations
iE1IS
e
vB1 vE( )
VT
iE2IS
e
vB2 vE( )
VT
iE1
iE2e
vB1 vB2( )
VT
iE1
iE1 iE21
1 e
vB2 vB1( )
VT
iE2
iE1 iE21
1 e
vB1 vB2( )
VT
iE11
1 e
vB2 vB1( )
VT
iE21
1 e
vB1 vB2( )
VT
Which can be manipulated to yield
iE1 iE2 I
I
I
The collector currentscan be obtained by multiplying the emitter currents by Alfa, which is ver close to unity
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Large-Signal Operation of the BJT Differential Pair
Relatively small difference voltage vB1 – vB2 will cause the current I to flow almost entirely in one of the two transistors.
4.VT (~100mV) is sufficient to switch the current to one side of the pair.
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Small-Signal OperationThe Collector Currents When vd is applied
vd vB1 vB2
iC1 I
1 e
vd
VT
iC2 I
1 e
vd
VT iC1 I e
vd
2 VT
e
vd
2 VTe
vd
2 VT
vd
2 VT
iC1
I 1vd
2 VT
1vd
2 VT 1
vd
2 VT
iC1
I 1vd
2 VT
1vd
2 VT 1
vd
2 VT
~
iC2 I2
I2 VT
vd
2 iC1
I2
I2 VT
vd
2
vBQ1 VBEvd
2 vBQ2 VBE
vd
2 gm
IC
VT
I
2
VT
ic
Multiplying by
Assuming vd<<2VT
Interpretation: IC1 increases by ic and iC2 decreases by ic
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An Alternative Viewpoint
reVT
IE
VT
I
2
ievd
2 re
Assume I to be ideal – its incremental resistance will be infinite and vd appears across a total resistance 2.re.
ic ie vd2 re
gmvd
2
A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal vd; dc quantities are not
shown.
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If emitter resistors are included
ievd
2 re 2 RE
A differential amplifier with emitter resistances. Only signal quantities are shown (on color).
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Input Differential Resistance
ibie
1
vd
2 re
1
Ridvd
ib 1 2 re 2 r
This is the resistance-reflection rule; the resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by the beta+1
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Input Differential Resistance
Rid 1 2 re 2 RE( )
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Differential Voltage Gain
iC1 IC gmvd
2 iC2 IC gm
vd
2 IC
I2
vC1 VCC IC RC( ) gm RCvd
2
vC2 VCC IC RC( ) gm RCvd
2
Advc1 vc2
vdgm RC
Ad 2RC( )
2 re 2 RE( )
RCre RE
Ad 2RC( )
2 re 2 RE( )
RCre RE
The voltage gain is equal to the ratio of the total resistance in the collector circuit (2RC) to the total resistance in the emitter circuit (2re+2RE)
~
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Equivalence of the differential amplifier (a) to the two common-emitter amplifiers in (b). This equivalence applies only for differential input signals. Either of the two common-emitter amplifiers in (b) can be used to evaluate the differential gain, input differential resistance, frequency response, and so on, of the differential amplifier.
Equivalence of the Differential Amp. To a Common-Emitter Amp.
Differential amplifier fed in a complementary manner (push-pull or balanced)
Base of Q1 raisedBased of Q2 lowered
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Equivalent Circuit Model of a Differential Half-Circuit
Ad gmRC ro
RC ro
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Common-Mode Gain
vc1 vCM RC
2 R re vCM
RC2 R
vc2 vCM RC2 R
Acm RC2 R
Ad1
2gm RC
CMRRAd
Acm
Assuming symmetry
AcmRC
2 RRC
RC vCM
v1 v22
vo Ad v1 v2( ) Acmv1 v2
2
If output is taken single-endedlyAcm and the differential gain AdWe can define CMRR
CMRR gm R 1
Common-mode half-circuits
Assuming non-symmetry
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Input Common-Mode Resistance
vCM ro
r
Ricm =
Ricm
2 . Ricm
vCM
Equivalent common-mode half-circuitSince the input common-mode resistance is usually very large, its value will be affected by the transistor resistancesR0 and r
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Nehemiah (Chief-Engineer of Wall Reconstruction)
God Calls Us to be agents:
Of Peace and ReconciliationFor JusticeFor the Flourishing of the Natural CreationFor BeautyFor KnowledgeFor the Growth of other people
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Example 6.1 – Class Discussion
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Example 6.3
I 1 VCC 15 RC 10 1
vB1 t( ) 5 0.005sin 2 1000 t
vB2 t( ) 5 0.005sin 2 1000 t vBE 0.7 at 1mA
a) vE b) gm c) iC d) vC e) vc1-vc2 f) gain at 1000Hz
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a )
VBE 0.7 0.025ln0.5
1
VBE 0.683
vE 5 VBE vE 4.317
b )
gmIC
VT gm 20
c )
iC1 t( ) 0.5 gm 0.005sin 2 1000 t iC2 t( ) 0.5 gm 0.005sin 2 1000 t
0 0.001 0.002 0.003 0.004 0.0050.3
0.4
0.5
0.6
iC1 t( )
iC2 t( )
t
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d )
vC1 t( ) VCC IC RC( ) 0.1 RC sin 2 1000 t
vC2 t( ) VCC IC RC( ) 0.1 RC sin 2 1000 t
0 0.001 0.002 0.003 0.004 0.0059
10
11
vC1 t( )
vC2 t( )
t
e )
0 0.001 0.002 0.003 0.004 0.0052
0
2
vC2 t( ) vC1 t( )
t
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Example 6.4
100
Delta_RC 0.02 Delta_IS 0.1 Delta_ 0.1 I 100 A
From Eq. 6.55
VOS VTDelta_RC
RC
2Delta_IS
IS
2
VOS 25 0.02( )2
0.12 VOS 2.55
IBI
2 1 IB 0.495 A
IOS IBDelta_
IOS 4.95 104 50nA
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Finally, brothers, whatever is true, wherever is noble, whatever is right, what ever is pure, whatever is lovely, whatever is admirable – if anything is excellent or praiseworthy – think about such things.Phil. 4:8
I gladly admit that we number among us men and women whose modesty, courtesy, fair-mindedness, patience in disputation and readiness to see an antagonist's point of view, are wholly admirable. I am fortunate to have known them. But we must also admit that we show as high percentage as any group whatever of bullies, paranoiacs, backbiters, mopes, milksops, etc.. The loutishness that turns every argument into a quarrel is really no rarer among us than among the sub-literate; the restless inferiority-complex (“stern to inflict” but not “stubborn to endure”) which bleeds at a touch but scratches like a wildcat is almost as common among us as among schoolgirls. CS Lewis.
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Biasing In BJT Integrated Circuits
Many resistors, transistors and capacitors makes impossible to use conventional biasing methods
Biasing in IC is based on the use of constant-current sources
The Diode-Connected Transistor
i
i
1
1i
Shorting the base and the collector of a BJT results in a two-terminal device having an I-v characteristic identical ot the iE-vBE of the BJT.
Since the BJT is still in active mode (vCB=0 results in an active mode operation) the current I divides between base and collector according to the value of the BJT Beta.
Thus, the BJT still operates as a transistor in the active mode. This is the reason the I-v characteristics of the resulting diode is identical to the iE-vBE relationship of the BJT
i
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Exercise 6.5
R incremental = r // (1/gm) // ro
Rinc
r1
gm
r1
gm
ro
r1
gm
r1
gm
ro
r
1ro
r
1ro
re rore ro
re Rinc25
0.5
Rinc 50
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The Current Mirror
Io
IO
1IE IREF
2
1 IE
IO
IREF
2
1
12
I O
I REF
12
1V O V EE V BE
VA
Finite Beta and Early Effect
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Exercise 6.6
IO5 1.073 103IO5 IO
5 4.3( )Rout
VO 5at
IO 9.804 104IO
IREF
12
VO 4.3VO VEE VBEVO VBat
Rout 1 105Rout
100
IREF
Rout roVA
IREF
IREF 0.001 100VBE 0.7VEE 5
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A Simple Current Source
I REF
VCC VBE
R
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Exercise 6.7
IO IREF IREF 0.001 VCC 5 VBE 0.7
neglect the effects ro and finite Beta 100 VA 50
roVA
IREF ro 5 10
4R
VCC VBE
IREF R 4.3 10
3
at VO 3 IO
IREF
12
VO VBE
ro IO 1.026 10
3
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However, this impulse to pursue the intellectual life must be kept "pure and disinterested," for the alternative is to "come to love knowledge-our knowing-more than the thing known: to delight not in the exercise of our talents but in the fact that they are ours, or even in the reputation they bring us".
Get wisdom, get understanding; do not forget my words or swerve from them. Do not forsake wisdom, and she will protect you; love her, and she will watch over you. Wisdom is supreme; therefore get wisdom. Though it cost all you have, get understanding. Esteem her, and she will exalt you; embrace her, and she will honor you. She will set a garland of grace on your head and present you with a crown of splendor. Prov. 4:4-8
We must not think Pride is something God forbids because He is offended at it, or that Humility is something He demands as due to His own dignity -- as if God Himself was proud. He is not in the least worried about His dignity. The point is, He wants you to know Him: wants to give you Himself. And He and you are two things of such a kind that if you really get into any kind of touch with Him you will, in fact, be humble -- delightedly humble, feeling the infinite relief of having for once got rid of all the silly nonsense about your own dignity which has made you restless and unhappy all your life. He is trying to make you humble in order to make this moment possible: trying to take off a lot of silly, ugly, fancy-dress in which we have all got ourselves up and are strutting about like the little idiots we are.
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Current-Steering Circuits
Generation of a number of cross currents.
I REF
VCC VEE VEB1 VBE2
R
IC Circuits2 power suppliesIREF is generated in the branch of the diode-connected transistor Q1, resistor R, and the diode-connected transistor Q2.
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Exercise 6.9
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Comparison With MOS Circuits
1 - The MOS mirror does not suffer from the finite Beta2 – Ability to operate close to the power supply is an important issue on IC design3 - Current Transfer: BJTs ~ relative areas; MOS ~ W/L4 - VA lower for MOS
Improved Current-Source Circuits IREF
1
2
1 2
IE
IO
1IE
IO
IREF
1
12
2
1
12
2
IREF
VCC VEB1 VBE3
R
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The Wilson Current Mirror
Output resistance equal
A factor greater the then simple
Current source
Disadvantage: reduced output swing.Observe that the voltage at the collector at Q3 has to be greater than the negative supply voltage by(vBB1 = VCEsat-3), which is about a volt.
ro2
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Exercise 6.10
I EI E
I E
1
I E
1
2 I E
1
I E
1 I E
1
2
1I E
2
1 2I E
2
1 2I E
~
IREF
1
2
1 2
IE
IO 2
1 2IE
IO
IREF
2 2 2
IO
IREF
1
12
2
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Widlar Current SourceIt differs from the basic current mirror in an important way: a resistor RE is included in the emitter lead of Q2. Neglecting the base current we can write:
VB1 VT lnIREF
IS
VB2 VT lnIO
IS
VB1 VB2 VT lnIREF
IO
VB1 VB2 IO RE
IO RE VT lnIREF
IO
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Example 6.2
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Example 6.3
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Current sources for biasing amplifying stages
Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 1st stage gain
-- Assuming
Model Eqs. on Pg. 263
er
In the same manor
k
rRi
05.5)25101(2
)1(22
542 rrRi
krrRid 2.2021
krrr e
1.10100*101))(1(21
10025.25
21 E
T
IV
ee rr
)()()( 1
E
T
C
T
m I
V
I
V
gr
By Justin Jansen
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Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 1st stage gain
VV
kk
rrRRR
RI
RI
vv
ee
i
RTotalEE
RTotalCC
id
oA
4.22200
40||05.5
)||(
1
21
212
__
__1
1Ri2
Total emitter resistance
Total collector resistance
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Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 2nd stage gain
VVkk
rrRR
ee
iA 2.59508.234||3||
2 54
33
Ri3
re4 and re5 calc. before
Potential gain is halved b/c converting to single-ended output
))(1( 743 ei rRR
25125
7 C
T
IV
er
k
kRi
8.234
)253.2(1013
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Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 3rd stage gain
Purpose is to allow amplified signal to swing negatively
Ri4
5525
8er
k
RrR ei
5.303)30005(101
))(1( 684
VV
kkk
RrRR
vv
e
i
o
oA 24.6325.25.303||7.15||
3 47
45
2
3
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Multistage Amplifiers – Example 6.4 – pg. 552
Calculating 3rd stage gain
VV
RrR
vv
eo
oA
998.30053000
4 68
6
3
Overall Gain
VV
vv AAAAAid
o 85134321
152)(|| 1865
R
eo rRROutput Resistance
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"The only people who achieve much are those who want knowledge so badly that they seek it while the conditions are unfavorable. Favorable conditions never come."
1 Samuel 7:7-12 When the Philistines heard that Israel had assembled at Mizpah, the rulers of the Philistines came up to attack them. And when the Israelites heard of it, they were afraid because of the Philistines. [8] They said to Samuel, "Do not stop crying out to the Lord our God for us, that he may rescue us from the hand of the Philistines." [9] Then Samuel took a suckling lamb and offered it up as a whole burnt offering to the Lord. He cried out to the Lord on Israel's behalf, and the Lord answered him. [10] While Samuel was sacrificing the burnt offering, the Philistines drew near to engage Israel in battle. But that day the Lord thundered with loud thunder against the Philistines and threw them into such a panic that they were routed before the Israelites.
[12] THEN SAMUEL TOOK A STONE AND SET IT UP BETWEEN MIZPAH AND SHEN. HE NAMED IT EBENEZER, SAYING, "THUS FAR HAS THE LORD HELPED US."
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The BJT Differential Amplifier With Active Load
vo gm vd Ro
Ro
ro2 ro4
ro2 ro4ro2 ro4 ro
Ro
ro
2vo gm vd
ro
2
vo
vd
gm ro
2
gm
IC
VTro
VA
ICIC
I
2
gm roVA
VT
constant for a given transitor
Ri 2 r Gm gm
I
2
VT
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The Cascode Configuration
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The Cascode Configuration
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How shall a young man be faultless in his way?By keeping to your words.With all my heart I seek you;let me not stray from your commands.Within my heart I treasure your promise,that I may not sin against you.Blessed are you, O Lord;teach me your statutes.With my lips I declareall the ordinances of your mouth.In the way of your decrees I rejoice,as much as in all riches.Ps 119: 9-14
Experience, the most brutal of teachers; but you learn, my God do you learn. C.S. Lewis
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BJT Single Stage Common-Emitter Amplifier
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MOS Differential Amplifiers – MOS Differential Pair
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MOS Differential Amplifiers – Offset Voltage
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MOS Differential Amplifiers – Current Mirrors
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Problem 6.1
RC 3000 vBE 0.7 iC 0.001 vCM 2 VCC 5 100
at iC 0.0005 vBE 0.7 0.025ln0.5
1
vBE 0.683
vE vCM vBE vE 2.683
iC1
1iC iC1 4.95 10
4
vC1 VCC iC1RC vC1 3.515
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Problem 6.15
Ad 40Advc2 vc1
vd
vc2 2vc2 ie RCvc1 2vc1 ie RC
iE2 6 104iE2 IE ie
iE1 1.4 103iE1 IE ie
ie 4 104ie
vd
2 re RE( )
RC 5000IE 0.001RE 100re 25vd 0.1
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BJT Differential Amplifier Laboratory
PurposeThe purpose of this lab is to investigate the behavior of a BJT difference amplifier. The circuit’s behavior needs to be modeled with theoretical equations and a computer simulation. Comparison of laboratory results with theoretical and simulated results is required for the relative validity of the models. This lab also investigates the variation of differential and common mode gains using a Monte Carlo analysis.
ProcedureConstruct the circuit in Figure 1 on PSpice and a Jameco JE26 Breadboard using a Hewlett-Packard 6205 Dual DC Power Supply as the voltage sources and an MPQ2222 Bipolar Junction Transistor (Q2N2222).
Using a Keithley 169 Digital Multi-Meter measure the voltages across the resistors to determine the transistor base current and collector current. From these current values calculate .
Figure 1) Circuit for testing transistor value
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Next construct the amplifier circuit shown in Figure 2. All transistors are MPQ2222 Bipolar Junction Transistors. Use PSpice to construct the circuit.
Measure the DC values at the collector of Q1 and Q2. Do the measured values agree with theoretical ones.
Measure the DC value at the emitter of Q1 and Q2. Do the measured value agree with the theoretical one.
Indicate the inverting and non-inverting output.
Input an AC signal into Q1 of your circuit at frequencies . What is the single voltage gain of your circuit?
Figure 2
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Both inputs (Vin1 and Vin2) should be then grounded in order to determine the DC operating point of the amplifier. Bias point voltages are measured and then compared to the bias points produced by the PSpice simulation. Record DC bias point data. Use a Wavetek 190 Function Generator with a sinusoidal input voltage of amplitude 0.031 V and apply to one of the input terminals and the other terminal remained grounded, as shown in figure 2. Use a Tektronix TDS 360 Digital Oscilloscope and a Fluke 1900A Multi-Meter the output of the amplifier to observe input signal frequencies. Determine the corner frequency (3-dB point) of the output and compared with the corner frequency generated with an AC sweep in PSpice. Plot the PSpice AC sweep simulation. Next calculate the differential mode voltage gain, AV-dm, from the laboratory data and
compare to the AV-dm predicted by the PSpice simulation and theoretical equations. Both
inputs are tied together to create a common mode signal on the input terminals. The output voltage is then used to calculate the common mode voltage gain, AV-cm, and then
compared to the AV-cm predicted by the PSpice simulation and theoretical equations. From
these values the common mode rejection ratio (CMRR) should be calculated for each case. Finally, PSpice should be used to perform a Monte Carlo analysis of the circuit. The resistors were all given standard unbridged values and were allowed to vary uniformly within 5% of the nominal resistor value. The transistors should be given a nominal value (say 175) and allowed to vary uniformly to +/- 100. The variations of differential and common mode gains should be graphed on two histograms.
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Analysis / Questions What are the values of for the first transistor? (typical values of range from approximately 125 to 225) With the exception of the Monte Carlo analysis, all transistors were assumed to have this value in the PSpice simulations. All four transistors were contained within one integrated circuit so that hopefully there would be little change in values from one transistor to the next, making the previous assumption reasonably valid. How close are the measured DC bias points of the circuit to those predicted by the PSpice simulation? What is the reason for the small differences between measured and predicted voltages?
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• Can a truly thinking person be a Christian?• Does the Gospel conflict with scientific knowledgeand modern discoveries in other fields?• How can Christians achieve intellectual / scientific integrity?
Independence / obedience, honesty, humility, fairness…
The supreme end of education is expert discernment in all things - - the power to tell the good from the bad, the genuine from the counterfeit, and to prefer the good and the genuine to the bad and the counterfeit.Samuel Johnson
Found in Faith-Lost in Matters of Learning and Intellectual Integrity.
Let integrity and uprightness preserve me. Psalms, 25,21
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Exercises 6.17
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An Active-Loaded CMOS Amplifier
Exercise 6.19
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Example 6.5 SPICE Simulation of a Multistage Amplifier
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Frequency Response
S-Domain Analysis Poles and Zeros
M
jj 1N 40 z1 7 3 jj z2 0
i 0 N p1 3 3 jj p3 7
j 0 N p2 3 p4 0 2 jj
ei
10.1 i 0.4 j 10.1 j 0.4
f e w( )e z1 w jj( ) e z2 w jj( )[ ]
e w jj p1( ) e w jj p2( ) p3 w jj e( ) e w jj p4( )
Mi j f e
i j
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Bode Plots
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Example 7.2
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Teach me your way, O Lord,and I will walk in your truth;give me an undivided heart,that I may fear your name.Ps. 86:11
"As for you, my son Solomon, know the God of your father, and serve Him with a whole heart and a willing mind; for the LORD searches all hearts, and understands every intent of the thoughts. (1 Chr. 28:9)
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Positive interdependence. Team members are obliged to rely on one another to achieve the goal.
Individual accountability. All students in a group are held accountable for doing their share of the work and for mastery of all of the material to be learned.
Face-to-face interaction. Although some of the group work may be parcelled out and done individually, some must be done interactively, with group members providing one another with feedback, challenging one another's conclusions and reasoning.
Appropriate use of collaborative skills. Students are encouraged and helped to develop and practice trust-building, leadership, decision-making, communication, and conflict management skills.
Group processing. Team members set group goals, periodically assess what they are doing well as a team, and identify changes they will make to function more effectively in the future.
COOPERATIVE LEARNING
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"What is the main idea of...?""What if...?""How does...affect...?" "What is the meaning of...?""Why is...important?" "What is a new example of...?""Explain why...." "Explain how...." "How does...relate to what I've learned before?" "What conclusions can I draw about...?"What is the difference between ... and ...?""How are ... and ... similar?""How would I use ... to ...?""What are the strengths and weaknesses of...?"
COOPERATIVE LEARNING
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Frequency Response
Exercise 7.1
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The Amplifier Transfer Function
The Three Frequency Bands (AM, wl, wh, BW, GB)
The Gain Function A(s) and the Low-Frequency Response
A s( ) AM FL s( ) FH s( )
A s( ) AM L H
AL s( ) AM FL s( )
AH s( ) AM FH s( )
L P12
P22
2 Z12
2 Z22
this relationship can be extended to any number of poles and zerosone of the poles can be dominant and the expression is simplied
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Low-Frequency Response
H1
1
P12
1
P12
2
Z12
2
Z12
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Becoming An Engineer
CompetenceResponsibilityIntegrity
WritingSpeaking
Pr. 1:7
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Writing
General Suggestions
1. Learn All You Can (Furnish Your Mind)
2. Think Hard About The Subject (Exercise Your Mind)
(Interesting, Creative Ideas)
3. Avoid Distractions (Quiet Your Mind)
4. Take A Break (Refresh Your Mind)
5. Save Time For Reflection (Free Your Mind)
6. Associate With Creative People (Stimulate Your Mind)
7. Keep Writing In Your Log Book (Tune In To Your Mind)
8. Notice Your “Crazy” Ideas (Respect Your Mind)
9. Be Quick To Question Authority/Professor (Alert Your Mind)
10. Trust God (Surrender Your Mind)
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Creation, Fall and Redemption:A Controls Systems Perspective
Creation CosmosHuman LifeHistory, Culture
Providence
Redemption Consummation
Cultural Mandate
FALL
Word ofGod(Laws,Commands,Structure)
RedeemedCreation
CREATION REDEMPTION
-+ ++
+UnfoldingRedeemingCreation
Language exists to communicate whatever it can communicate. Some things it communicates so badly that we never attempt to communicate them by words if any other medium is available.C.S. Lewis
Graphics
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( ) ( )
( ) . . ( )
( ' ... ) ( )
( ) ( )
( ' ... ) ( )
( ' ... ...&...Re ) ( )
( ) ( ... )
0 God Universe
Universe dx dy dz Good
God s Will Evil
d
dtEvil Sin
Man s Sins Death
Jesus Suffereing surection Death
Death Eternal Life
Creation
Fall
Redemption
MathematicsCreation, Fall and Redemption:
A Mathematical Perspective
The reason that some intuitive minds are not mathematical is that they cannot at all turn their attention to the principles of mathematics. But the reason that mathematicians are not intuitive is that they do not see what is before them …since they are accustomed to the exact principles of mathematics… and are lost in matters of intuition where the principles do not allow of such arrangement. Blaise Pascal
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Using Short-Circuit and Open Circuit Times ConstantsFor the Approximate Determination of L and H
Open Circuit time Constants
H1
i
Ci Rio
Short Circuit time Constants
L
i
1
Ci Ris
Dominant Pole Exists
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Example 7.5 - Study
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Low-Frequency Response of the Common-Source Amplifier
Vg s( )
Vi s( )
Rin
Rin Rss
1
CC1 Rin R
highpass function Cc1 introduces a zero at zero frequency and a real pole at p1
P11
CC1 Rin R
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Low-Frequency Response of the Common-Source AmplifierNext
Id s( ) I s( )Vg s( )
1
gmZs
Id s( ) gm Vg s( )YS
gm YS
YS1
ZS
1
RSs CS
Id s( ) gm Vg s( )
s1
CS RS
s
gm1
RS
CS
Z1
CS RS P2
gm1
RS
CS
1
CS
Rs1
gm
RS1
gm
CSintroduces a zero at ZS
at infinite, which means Vo zero
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Low-Frequency Response of the Common-Source Amplifier
ro RD approximation is valid
after Thevenin's theorem and some manipulation
Vo s( ) Id s( ) Parallel RD ro RL s
s1
CC2RL
RD ro
RD ro
P31
CC2 RL
RD ro
RD ro
CC2introduces a zero at zero freq.and a real pole a
WP3
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AL s( )Vo s( )
Vi s( )AM
s
s P1
s Z
s P2
s
s P3
AM
Rin
Rin Rgm Parallel RD ro RL
Low-Frequency Response of the Common-Source Amplifier
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Low-Frequency Response of the Common-Source Amplifier
Design of the Coupling Cc1 and Cc2
and Bypass Capacitors Cs
To place the lower 3-db frequency wl at the specified value.
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Exercise 7.7
The frequency of the zero is given by eq. 7.37
Z1
CS RS
CS
The frequency of the pole is given by eq. 7.38
p
gm1
RS
CS
gm
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Analysis of the Common-Emitter Amplifier
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Analysis of the Common-Emitter Amplifier
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A MOSFET common-source amplifier (a), and a BJT common-emitter amplifier (b). here, Vs and Rs represent the
Thévenin equivalent of the circuit at the input side, including the output circuit of the preceding amplifier stage (if any) and the bias network of the transistor Q (if any). Similarly, RL represents the total resistance between the drain
(the collector) and signal ground. Although signal ground at the source (emitter) is shown established by a large capacitor, this is not necessary, and the circuits can be used to represent, for instance, the differential half-circuit of a differential pair.
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(a) Equivalent circuit for analyzing the high-frequency response of the amplifier circuit of Fig. 7.15(a). Note that the MOSFET is replaced with its high-frequency equivalent-circuit. (b) A slightly simplified version of (a) by combining RL and ro into a single resistance R’L = RL//ro.
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Chapter 8 - Feedback
1 - Desensitize The Gain
2 - Reduce Nonlinear Distortions
3 - Reduce The Effect of Noise
4 – Control The Input And Output Impedances
5 – Extend The Bandwidth Of The Amplifier
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Chapter 8 – Feedback
The General Feedback Structure
xs xi xf xo
A
xo A xi
xi xs xf
xf xo
Af
xo
xs
A
1 A
A 1 A
feedabck factor loop gain amount of feedabck
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The General Feedback Structure
Exercise 8.1
Af 10 A 104
a ) R1
R1 R2
b ) AfA
1 A
1
given
AfA
1 A
Find 0.1
R1
R1 R20.1
R2
R19
Amount_Feedback 20 log 1 A c )
Amount_Feedback 60
Vs 1 Vo Af Vs Vo 10d )
Vf Vo Vf 0.999
Vi Vs Vf Vi 10 104
e ) A 0.8 104
AfA
1 A Af 9.998
10 9.99810
100 0.02
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The General Feedback Structure
Exercise 8.1
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Some Properties of Negative Feedback
Gain Desensitivity
AfA
1 A
deriving
dAfdA
1 A ( )2
dividing by AfA
1 A
dAf
Af
1
1 A ( )
dA
A
The percentage change in Af (due to variations in some circuit parameter) is smaller than the pecentage cahnge in A by the amount of feedback. For this reason the amount of feedback
1 A
is also known as the desensitivity factor.
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Some Properties of Negative Feedback
Bandwidth Extension
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Some Properties of Negative Feedback
Noise Reduction, Reduction of Nonlinear Distortion
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The Four Basic Feedback Topologies
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The four basic feedback topologies: (a) voltage-sampling series-mixing (series-shunt) topology; (b) current-sampling shunt-mixing (shunt-series) topology; (c) current-sampling series-mixing (series-series) topology; (d) voltage-sampling shunt-mixing (shunt-shunt) topology.