PROCESS CAPABILITY AND QUALITY

by

Timothy A. Estes

Conductor Analysis Technologies, Inc.

Albuquerque, New Mexico

and

Ronald J. Rhodes

Conductor Analysis Technologies, Inc.

Green Brook, New Jersey

INTRODUCTION

Pressures to reduce package sizes and increase electrical performance have mandated technological developments in the design and manufacture of printed circuit boards. Development efforts have been focused primarily on smaller feature sizes such as

conductors, spaces, via hole diameters, and via land diameters. As feature sizes become smaller, they are inherently more difficult to manufacture, and a greater number of vias and a greater length of conductors and spaces fit within a printed circuit boardmanufacturing format. Therefore, smaller features must be fabricated at even lower defect densities than larger features to achieve equivalent yields.

The increased defect densities associated with smaller features, and the demands for greater electrical performance typically increase the price of the circuit boards. When manufacturing yields are lower than expected, delivery schedules are impacted,

delaying product introduction or even missing market windows completely. Additionally,

quality issues with printed circuits can result in a variety of problems during assembly,

cause poor circuit performance, and ultimately result in product failure once delivered to

the end user.

The technology used to manufacture a printed circuit board is often determined early in the design process. The circuit designer works within the constraints of overall size,

thickness, weight, electrical performance, and thermal demands, but may have discretion on parameters such as layer count, feature sizes, and material properties to achieve the design objectives. The interconnect technology and feature sizes selected by the designer impacts the manufacturability, quality, performance, reliability, and cost of the final product.

SUPPLIER CAPABILITY AND QUALITY

Purchasers of printed circuit boards must manage the complexities of technology,

quantity, delivery, and price of boards they are responsible of procuring, while keepingin mind the capability of each of their suppliers and the quality of the boards they

produce. Quantitative statistical measures that distinguish one supplier or process from

another can assist procurement staff in decisions regarding supplier capability and

quality. Capability implies the ability to successfully form features such as conductors,

spaces, and vias. Given that the features were formed successfully, quality asserts the

degree to which they conform to specifications. By utilizing measures of capability and

quality, purchasers of printed circuits can minimize the potential of shipment delays

caused by lower-than-expected manufacturing yields while ensuring the highest

possible product quality.

Capability and quality data collected from suppliers can be used to optimize designs for manufacturability. By minimizing or eliminating features that are difficult to manufacture, the suppliers will be able to manufacture designs at higher yields, lower costs, improved quality, and with minimal risk of shipment delays. When designers follow predefined design rules based on supplier capability and quality, both the purchaser and suppliers will find themselves in a win-win situation.

MEASURING CAPABILITY AND QUALITY

The approach to measure capability and quality relies on three key elements:

Specialized test patterns, referred to as process capability panels, designed to

reproduce the features present in printed circuit boards

Methods of testing the completed capability panels to extract raw capability and

quality data

Data analysis techniques to generate relevant statistics

The printed circuit board manufacturing process can be represented by a transfer

function (Figure 1a). The input to the transfer function is the circuit board design data,

typically Gerber data that contains design features, and the output is the actual printed

circuit boards. As with most transfer functions, the output does not exactly equal the

input but is blurred by the transfer function, the printed circuit manufacturing process.

When applied to process capability panels (Figure 1b), the input contains a range of

known design features, and the output is the capability and quality data that are

collected from the process capability panels.

The printed circuit board manufacturing process is blurred by defects and variations in

the design features caused by process limitations, processing conditions, and process

non-uniformities.

Figure 1. (a) PCB Manufacturing Transfer Function, (b) Capability Transfer Function.

The test patterns used to collect data from printed circuit board manufacturing process

should be designed conceptually as close as possible to the product they are intended

to model. This includes conductor and space sizes, via hole and land sizes, registration

and impedance requirements, the number of layers, stack-up, board thickness, and

materials.

A set of test patterns that have been specially designed to collect detailed process

capability and quality data on a range of feature sizes is shown in Figure 2. When

distributed over the area of the manufacturing panel format and manufactured in

sufficient numbers, they provide the basis for relevant statistics on the capability and

quality of the process that was used in their manufacture. Table 1 details the

information that that can be obtained from each of these patterns.

DATA ANALYSIS TECHNIQUES

Defect Density

The calculation of defect density from capability data normalizes the probability of

having defects, and can be used to predict product yields. Defect density may be

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calculated for conductors, spaces, and vias. Equation 1 is used to calculate conductor

defect density from process capability panel capability data.

where:

Y = conductor yield from test pattern, in defects/millions of inches

l = length of individual conductors in inches

lamdaC = conductor defect density

Similar equations are used to calculate defect density for spaces and vias.

Predicted Yields

The fraction yield on product due to opens in conductors is calculated by:

Similarly, the fraction yield on product due to shorts between conductors is calculated

by:

The product of the fraction yield due to opens and the fraction yield due to shorts

provides an estimate of yield on product due to opens and shorts:

Yp = 100 Yfo Yfs (4)

Capability Potential Index

Control indices provide a numerical result that is indicative of the quality of the process

used to manufacture conductors. The capability potential index, Cp, (Equation 5) is the

ratio of the difference between the upper specification limit (USL) and lower specification

limit (LSL) to six times the standard deviation (). Larger capability potential indices

indicate that the manufacturing process has greater potential to provide features that fall

within the specification limits. Page 4

Capability Performance Index

The capability performance index, Cpk, relates the mean and standard deviation to the

specification limits by the relationship in Equation 6. The capability performance index

is always less than or equal to the capability potential index. If the mean () is centered

between the lower and upper specification limits, then the capability performance index

equals the capability potential index; otherwise, it is less than the capability potential

index. Larger capability performance indices indicate a greater probability of the data

falling within the specification limits.

Coefficient of Variation

The coefficient of variation is defined as 100 multiplied by the standard deviation,

divided by the mean (Equation 7). This expression normalizes the spread in the data to

the mean, and is sometimes called the relative standard deviation. For a given mean,

smaller standard deviations characterize improved performance so that the smaller the

CoV, the better.

Probability of Breakout

Probability of breakout is a measure of the chance of a via hole being misregistered

from its land by greater than the annular ring of the via. The probability of breakout is

calculated for each designed clearance by Equation 8.

CONDUCTOR AND SPACE CAPABILITY AND QUALITY

The ability to successfully manufacture conductors and spaces, as measured by defect

density, provides a convenient means to estimate expected yield on product, and

illustrates the impact of defects on yield. Figure 3 shows predicted product yield due to

opens plotted versus feature length for 2-, 3-, 4-, and 5-mil conductors formed on

outerlayers. The curves show that for a fixed defect density, yield falls off with

increased conductor length on product. At 156 defects per million inches of 4-mil

conductor, predicted product yields (due to opens) for 100, 1000, and 10000 inches of

conductor are 98.5, 85.6, and 21.0 percent, respectively. When defect levels increase

to 598 defects per million inches, as shown for the 3-mil conductor in the figure,

predicted yields drop to 94.2, 55.0, and 0.3 percent for 100, 1000, and 10000 inches of

conductor, respectively.

Figure 3. Predicted Product Yield vs. Conductor Length. The curves correspond to

defect densities for 2- (3468), 3- (598), 4- (156), and 5-mil (21) outerlayer conductors.

Figure 4 shows predicted product yield due to shorts between conductors versus space

length on product. Defect densities in this example are higher for spaces than for

conductors. The 4-mil space recorded a defect density of 644 defects per million inches

of spaces. Once again, predicted yield falls off with increased space length on product

for a fixed defect density.

To estimate the combined effects of opens and shorts on product yield, the fraction yield

due to opens is multiplied by the fraction yield due to shorts, and converted back to

percent by multiplying by 100. As an example, if there were 1000 inches of 4-mil

conductors and 500 inches of 4-mil spaces on product, the predicted yield would be

0.856 * 0.725 * 100 = 62.0 percent.

Figure 4. Predicted Product Yield vs. Space Length. The curves correspond to defect

densities for 2- (8551), 3- (2312), and 4-mil (644) outerlayer spaces.

Given that conductors were successfully fabricated, their quality may be characterized

by examining the accuracy and precision with which they were formed. Figure 5

displays the distributions of calculated conductor width, plotted versus target conductor

width for 2-, 3-, 4-, and 5-mil outerlayer conductors. The distributions are portrayed by

notched box plots with the dotted lines showing the upper and lower specification limits:

20 percent in this example. When the conductors are formed accurately, the notched

box plots will be centered between the upper and lower specification limits. When the

conductors are formed precisely, the distribution of widths indicated by the notched box

plot will be tightly clustered.

The shaded bars in the figure show the control indices for each of the four conductors.

In all cases, the capability potential index was much greater than the capability

performance index, because the conductors were not formed with high accuracy. The

median widths were approximately 0.4 mils narrower than the target conductor widths.

Figure 5. Conductor Width vs. Target Conductor Width with Control Indices. The

dashed lines correspond to 20 percent specification limits.

The quality of conductors is also affected by the accuracy and precision of their height.

Figure 6 shows calculated conductor height plotted versus target conductor height for

the outerlayer conductors. While the height was more accurately controlled than the

width (the notched box plots are more closely centered between the upper and lower

specification limits), the precision (indicated by the extent of the notched box plot and

the lower value of capability potential index) was much worse than that of the widths.

Figure 6. Conductor Height vs. Target Conductor Height with Control Indices. The

dashed lines correspond to 20 percent specification limits.

VIA CAPABILITY AND QUALITY

The capability to form and interconnect vias, and the quality and reliability of the

interconnection depend upon many steps, including the registration, drilling, cleaning,

metallization, and patterning processes. Misregistration of the via with respect to the

land(s) can lead to marginal interconnections that exhibit increased resistance, and

perhaps lead to reliability problems.

Registration capability of blind microvias is shown in Figure 7, which displays probability

of breakout plotted versus annular ring. The smallest clearance (negative one mil),

included to verify that the proper hole size was drilled, is intentionally designed to fail.

Probability of breakout decreases from 98 percent for the 2-mil designed clearance to

zero for the 6- and 7-mil clearances. If breakout is not allowed then designs fabricated

by the supplier in this example would require annular rings of 6 mils or larger for the

microvias. By designing to 5-mil annular rings, the data estimates that 5 percent of the

microvias would exhibit breakout.

Figure 7. Probability of Breakout vs. Annular Ring for microvias.

The capability to form microvias is summarized in Figure 8, which displays predicted

product yield due to opens in vias plotted versus the number of vias. Similar to

predicted product yield for conductors and spaces, the estimated yield for a given defect

density drops off with an increased number of vias in the design. For example the 5-mil

microvias recorded a defect density of 106 defects per million vias. At this defect level,

the estimated yield drops from 89.9 percent to 34.7 percent by increasing the number of

vias from 1000 to 10000.

Figure 8. Predicted Product Yield vs. Number of Vias. The curves correspond to

defect densities for 4- (394), 5- (106), 6- (26), and 7-mil (5) microvias.

The quality of vias may be investigated by examining the distribution of resistance

measurements made from daisy chain patterns. Figure 9 shows the distributions for 4-,

5-, 6-, and 7-mil microvias. The results indicate that 6- and 7-mil diameter microvias

were fabricated with high quality, but the 5-mil and especially the 4-mil diameter

microvias exhibited very poor quality, indicated by the broad distributions and numerous

outside values.

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Figure 9. Via Net Resistance vs. Net Number. The distributions correspond to 4-, 5-,

6-, and 7-mil microvias, respectively.

SOLDERMASK REGISTRATION AND CONTROLLED IMPEDANCE CAPABILITIES

Similar methodologies to those presented are used to determine the capability of

soldermask registration and of a process to produce controlled impedance structures.

STANDARDIZATION

The IPC D-36 Printed Board Process Capability, Quality, and Relative Reliability

(PCQR2) Benchmark Test Standard Subcommittee was formed to establish and

maintain a family of benchmark process capability panel designs, develop and maintain

an anonymous database of printed circuit board suppliers' capabilities, and develop a

companion standard within the IPC-2XXX family of design documents.

The PCQR2 Design Library includes 6-, 12-, 18-, and 24-layer designs, each with

medium and high technology design rules. The designs incorporate conductor and

space, via registration, via daisy-chain, control-depth-drill overshoot, soldermask

registration, and single-ended and differential impedance features.

Data from the test panels is compiled into an anonymous database that details the

process capability, quality, and relative reliability demonstrated by PCB suppliers. The

cost of developing and maintaining the database is shared among suppliers, Original

Equipment Manufacturers (OEMs), and Contract Electronic Manufacturers (CEMs).

Suppliers produce the process capability panels and pay for a portion of the testing and

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analysis services. Suppliers receive a report detailing the capability and quality of the

panels submitted, and access to the database for six months following the posting of

their data. This allows suppliers to compare their capability and quality to others.

OEMs and CEMs use the database to find, screen, and select PCB suppliers based on

technology requirements, and access the database through an annual subscription.

While the database is anonymous, OEMs and CEMs can request the identity of the

suppliers in the database. Requests are forwarded to the appropriate supplier, who can

then contact the OEM/CEM directly.

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