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IMPLEMENTATION OF DIRECT DIGITAL

SYNTHESIZER AD9850 USING ARDUINO

UNO

B.Tech. Project Report

V.Mounika

G.Ravali

K.SindhuraV.Sindu

DEPARTMENT OF ELECTRONICS ANDCOMMUNICATION ENGINEERING

GOKARAJU RANGARAJU INSTITUTEOF ENGINEERING AND TECHNOLOGY

(Affiliated to Jawaharlal Nehru Technological University)

HYDERABAD 500 090

2013

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IMPLEMENTATION OF DIRECT DIGITAL

SYNTHESIZER AD9850 USING ARDUINO

UNO

Project Report Submitted in Partial Fulfillmentof the Requirements for the Degree of

Bachelor of Technology

In

Electronics and Communication Engineering

By

V.Mounika (09241A0484)

G.Ravali (09241A0495)

K.Sindhura (09241A04A3)

V.Sindu (09241A04A4)

DEPARTMENT OF ELECTRONICS ANDCOMMUNICATION ENGINEERING

GOKARAJU RANGARAJU INSTITUTE OFENGINEERING AND TECHNOLOGY


HYDERABAD 500 090

2013

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Department of Electronics and Communication Engineering

Gokaraju Rangaraju Institute of Engineering and Technology


Hyderabad 500 090

2013

Certificate

This is to certify that this project report entitled ―Implementation of directdigital synthesizer AD9850 using arduino Uno‖ by V.Mounika (Roll

No.09241A0484), G.Ravali (Roll No.09241A0495),K.Sindhura (Roll No.09241A04A3) and V.Sindu (Roll No. 09241A04A4), submitted in partialfulfillment of the requirements for the degree of Bachelor of Technology inElectronics and Communication Engineering of the Jawaharlal Nehru TechnologicalUniversity, Hyderabad, during the academic year 2009-13, is a bonafide record ofwork carried out under our guidance and supervision.

The results embodied in this report have not been submitted to any otherUniversity or Institution for the award of any degree or diploma.

(Guide) (External Examiner) (Head of Department)

N.Ome Ravi Billa

Assistant Professor

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ACKNOWLEDGMENT

It is a pleasure to express thanks to Prof. N.Ome for the encouragement and guidance

throughout the course of this project.

We also express our sincere thanks to prof. Ravi Billa Head of the Department,

G.R.I.E.T for extending his help.

We wish to thank Mr. K.N.B. Kumar, Mr. Anantha Radhanand and Mr. V.H. Raju for

their valuable suggestions during the course of our project.

We wish to express our profound sense of gratitude to Prof. P.S.Raju, Director

,G.R.I.E.T for his encouragement and for all facilities to complete this project.

Finally we express our sincere gratitude to all the members of faculty and my friends

who contributed their valuable advice and helped to complete the project successfully.

V.Mounika ________________________

G.Ravali ________________________

K.Sindhura ________________________

V.Sindu ________________________

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Abstract

Our project deals with the implementation of direct digital synthesizer AD9850 using

Arduino. A digitally-controlled method of generating multiple frequencies from a

reference frequency source is called Direct Digital Synthesis (DDS).The AD9850 is a

highly integrated device that uses advanced DDS technology coupled with an internal

high speed, high performance D/A converter and comparator to form a complete,

digitally programmable frequency synthesizer and clock generator function. When

referenced to an accurate clock source, the AD9850 generates a spectrally pure,

frequency/phase programmable, analog output sine wave. This sine wave can be used

directly as a frequency source, or it can be converted to a square wave for agile-clock

generator applications. The AD9850‘s innovative high speed DDS core provides a 32- bit frequency tuning word, which results in an output tuning resolution of 0.0291 Hz

for a 125 MHz reference clock input. The AD9850‘s circuit architecture allows the

generation of output frequencies which can be digitally changed (asynchronously) at a

rate of up to 23 million new frequencies per second.

Block Diagram

Hardware Required: ARDUINO UNO,DDS module,Protoshield

Software Required: Arduino

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CONTENTS

LIST OF FIGURES

CHAPTER-1:INTRODUCTION………………………………………………………….……...…1

1.1 MOTIVATION…………..………………………………………………………...……1

1.2 METHODOLOGY…………………...……….……………………………………....…1

1.3 SIGNIFICANCE …………………………………...………………….…………..……1

1.4 OVERVIEW……………………………………..…………………………..………….1

1.5 CONCLUSION…………………………………..……………………………...………2

CHAPTER-2:DIRECT DIGITAL SYNTHESIZE………………………………………..……………3

2.1 FUNDEMENTALS OF DIGITAL TECHNOLOGY……………………….……………3

2.1.1 OVERVIEW…………………..………………………………………….....…3

2.1.2 DDS DISADVANTAGES…………………………………………….………3

2.1.3 THEORY OF OPERATION…………………………………………..………3

2.1.4 PHASE ACCUMULATOR ………………………………………….….…….7

2.2 UNDERSTANDING THE SAMPLE OUTPUT OF DDS DEVICE……………………7

2.3 FREQUENCY/HOPPING CAPABILITY OF DDS…………………………………………..9

2.3.1 THE DDS CONTROL INTERFACE………………………..……………….10

2.3.2 PROFILE REGISTERS………………………………………..……………..10

2.3.3 THE EFFECT OF TRUNCATING THE PHASE

ACCUMULATOR ON SPURIOUS PERFORMANCE…………………..…10

2.4 REFERENCE CLOCK CONSIDERATIONS………………………………………………….12

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2.5 CONCLUSION………………............................................................................... 13

CHAPTER-3:AD9850…………………………………………………………………………………………………………………14

3.1 GENERAL DESCRIPTION………………………………………………………………………………..14

3.2 PIN DESCRIPTION..................................................................................................15

3.3 THEORY OF OPERATION AND APPLICATION………………..………………………17

3.4 PROGRAMMING THE AD9850………………………………….……………….……19

3.5 PCB LAYOUT INFORMATION…………………………...…………………..………23

3.6 EVALUATION BOARDS..…………………………………………………………….24

3.7 AB9850 EVALUATION BOARDS INSTRUCTION...………………………….…….24

3.7.1 REQUIRED HARDWARE/SOFTWAR E…………………………….…….…..….24

3.7.2 SETUP……………………………………………………...………………………25

3.7.3 OPERATION……………………………………………………………………….25

3.8 CONCLUSION...………………………..…….…………………………………………25

CHAPTER4:ARDUINO………………………………………………………………………...….26

4.1 ARDUINO PIN DESCRIPTION…………………………………………………………………………..26

4.1.1 CHARACTERISTICS……………………………………………………………………………………..28

4.1.2 SCHEMATIC & REFERENCE DESIGN………………………………………………………..28

4.1.3 COMMUNICATION……………………………………………………………30

4.1.4 PROGRAMMING…………………………………………………………….....30



































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APPENDIX-B…………………………………………………………………………………………42

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LIST OF FIGURES

Figure 2.1:Simple direct digital synthesizer…………………………………………........................…4

Figure 2.2:Frequency-tunable DDS system……………………………………………..................…...4

Figure 2.3:Signal flow through the DDS architecture…………………………………………….....…6

Figure 2.4:Computation of the Phase register…………………………………......................................7

Figure 2.5:Spectral analysis of Sampled output………………………………………………………...8

Figure 2.6:Phase truncation Error and the phase wheel……………………………………..................11

Figure 2.7:Reference clock edge uncertainty adversely effects DDS output signal quality…………...12

Figure 3.1:Pin discription………………………………………………………………........................15

Figure 3.2:Basic block diagram of DDS and Signal flow of AD9850…………………………………18

Figure 3.3:Output spectrum of a sampled signal………………………………………………….........18

Figure 3.4:Parallel Load Frequency/Control word functional assignment……...................…………...20

Figure 3.5:Master Reset Timing Sequence……………………………………………………………..21

Figure 3.6:Parallel load power-Down sequence/Internal operation…………..................................……21

Figure 3.7:Parallel load power-Up sequence/Internal operation…………………………………..........21

Figure 3.8:Serial Load enable sequence………………………………................................................ ...22

Figure 3.9:Pins 2 to 4 connections for Default Serial Mode Operation………………………………….22

Figure 3.10:Serial Load Frequency/Phase Update Sequence…………………………….......................22

Figure 3.11:Serial Load Power-Down Sequence…………………..........................................................23

Figure 3.12:AD9850 I/O Equivalent Circuits…………………………........................................……...23

Figure 4.1:ARDUINO UNO Pin Description...........................................................................................27

Figure 6.1:DDS Module…………………………………………………………………………………35

Figure 6.2:Protoshield………………………………………………………………………………… ...35

Figure 6.3:ARDUINO UNO Board…………………………………………………….……………….36

Figure 6.4:Interfacing of modules……………………………………………………………………….36

Figure 6.5:Final Output waveform………………………………………………………………………37





















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Chapter 1

INTRODUCTION

1.1 Motivation

A major advantage of a Direct Digital Synthesizer (DDS) is that its output frequency, phase

and amplitude can be precisely and rapidly manipulated under digital processor control.

Other inherent attributes include the ability to tune with extremely fine frequency and phase

resolution and to rapidly hop between frequencies. These combined characteristics have

made the technology popular in various military radar and communication systems.

Previously, DDS technology was used only in high-end applications as it was costly,

difficult to implement, and required a discrete high speed D/A converter. Due to improved

Integrated Circuit (IC) technologies, they now present a viable alternative to analog based

Phase Locked Loop (PLL) based technology for generating agile analog output frequency in

consumer synthesizer applications.

1.2 Methodology

We implemented this project using Arduino Uno, protoshield a DDS module with the code

written on arduino software.

1.3 Significance A direct digital synthesizer (DDS) provides many significant advantages over the PLLapproaches.

Fast settling time, sub-Hertz frequency resolution, continuous-phase switching

response and low phase noise are features easily obtainable in the DDS systems.

By programming the DDS, adaptive channel bandwidths, modulation formats,

frequency hopping and data rates are easily achieved. This is an important step towards a "software-radio" which can be used in various

systems. The DDS could be applied in the modulator or demodulator in the communicationsystems.

1.4 Overview

In chapter two, we discuss the fundamentals to understand DDS technology i.e., the basic

theory of operation involved. In chapter three, we describe the

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signal flow, programming the AD9850 and other necessary information related to its

operation. Arduino, the easy-to-use hardware and software is discussed in chapter four. The

implementation of the project and the results are discussed in chapter five and six

respectively. Finally, we end up with chapter seven, where several applications and futurescope of this project are discussed.

1.5 Conclusion

The motivation, methodology used in the implementing the project, significance and theoverview is discussed in this chapter

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Chapter 2

DIRECT DIGITAL SYNTHESIZER

2.1. Fundamentals of DDS Technology

2.1.1 Overview

Direct Digital Synthesis (DDS) is a technique for using digital data processing blocks as ameans to generate a frequency- and phase-tunable output signal referenced to a fixed-

frequency precision clock source. In essence, the reference clock frequency is ―divided

down‖ in DDS architecture by the scaling factor set forth in a programmable binary tuning

word. The tuning word is typically 24-48 bits long which enables a DDS implementation to provide superior output frequency tuning resolution. Today‘s cost-competitive, high-

performance, functionally-integrated, and small package-sized DDS products are fast

becoming an alternative to traditional frequency-agile analog synthesizer solutions. Theintegration of a high-speed, high-performance, D/A converter and DDS architecture onto a

single chip (forming what is commonly known as a Complete-DDS solution) enabled this

technology to target a wider range of applications and provide, in many cases, an attractivealternative to analog-based PLL synthesizers. For many applications, the DDS solution holds

some distinct advantages over the equivalent agile analog frequency synthesizer employing

PLL circuitry.

2.1.2 DDS advantages

Micro-Hertz tuning resolution of the output frequency and sub-degree phase

tuning capability, all under complete digital control. Extremely fast ―hopping speed‖ in tuning output frequency (or phase), phase-

Continuous frequency hops with no over/undershoot or analog-related loop

setting time anomalies The DDS digital architecture eliminates the need for the manual system tuning

and tweaking associated with component aging and temperature drift in analog

synthesizer solutions. The digital control interface of the DDS architecture facilitates an environment

where systems can be remotely controlled, and minutely optimized, under

processor control. When utilized as a quadrature synthesizer, DDS afford unparalleled matching

and control of I and Q synthesized outputs.

2.1.3Theory of Operation

In its simplest form, a direct digital synthesizer can be implemented from a precision

reference clock, an address counter, a programmable read only memory (PROM), and a D/a

converter.

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Fig 2.1 Simple Direct Digital Synthesizer

In this case, the digital amplitude information that corresponds to a complete cycle of a sine

wave is stored in the PROM. The PROM is therefore functioning as a sine lookup table. Theaddress counter steps through and accesses each of the PROM‘s memory locations and the

contents (the equivalent sine amplitude words) are presented to a high-speed D/A converter.

The D/A converter generate an analog sine wave in response to the digital input words from

the PROM. The output frequency of this DDS implementation is dependent on 1.) Thefrequency of the

reference clock, and 2.) the sine wave step size that is programmed into the PROM. While the

analog output fidelity, jitter, and AC performance of this simplistic architecture can be quite

good, it lacks tuning flexibility. The output frequency can only be changed by changing thefrequency of the reference clock or by reprogramming the PROM. Neither of these options

supports high-speed output frequency hopping. With the introduction of a phase accumulator

function into the digital signal chain, this architecture becomes a numerically-controlledoscillator which is the core of a highly-flexible DDS device. As figure 1-2 shows, an N-bit

variable-modulus counter and phase

Fig 2.2 Frequency-tunable DDS System

register are implemented in the circuit before the sine lookup table, as a replacement for the

address counter. The carry function allows this function as a ―phase wheel‖ in the DDSarchitecture. To understand this basic function, visualize the sine wave oscillation as a vector

rotating around a phase circle. Each designated point on the phase wheel corresponds to the

equivalent point on a phase wheel.

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cycle of a sine waveform. As the vector rotates around the wheel, visualize that a

corresponding output sine wave is being generated. One revolution of the vector around the

phase wheel, at a constant speed, results in one complete cycle of the output sine wave. The phase accumulator is utilized to provide the equivalent of the vector‘s linear rotation around

the phase wheel. The contents of the phase accumulator correspond to the points on the cycle

of the output sine wave. The number of discrete phase points contained in the ―wheel‖ isdetermined by the resolution, N, of the phase accumulator. The output of the phase

accumulator is linear and cannot directly be used to generate a sine wave or any other

waveform except a ramp. Therefore, a phase-to amplitude lookup table is used to convert a

truncated version of the phase accumulator‘s instantaneous output value into the sine waveamplitude information that is presented to the D/A converter. Most DDS architectures exploit

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the symmetrical nature of a sine wave and utilize mapping logic to synthesize a complete sine

wave cycle from ¼ cycles of data from the phase accumulator. The phase-to-amplitude

lookup table generates all the necessary data by reading forward then back through the

lookup table.

Fig 2.3 Signal flow through the DDS architecture

The phase accumulator is actually a modulus M counter that increments its stored numbereach time it receives a clock pulse. The magnitude of the increment is determined by a digital

word M contained in a ―delta phase register‖ that is summed with the overflow of the

counter. The word in the delta phase register forms the phase step size between reference

clock updates; it effectively sets how many points to skip around the phase wheel. The largerthe jump size, the faster the phase accumulator overflows and completes it‘s equivalent of a

sine wave cycle. For an N=32-bit phase accumulator, an M value of 0000…0001(one) would

result in the phase accumulator overflowing after 232 reference clock cycles (increments). If

the M value is changedto 0111…1111, the phase accumulator will overflow after only 21 clock cycles, or two

reference clock cycles. This control of the jump size constitutes the frequency tuning

resolution of the DDS architecture.The relationship of the phase accumulator and delta phase accumulator form the basic tuning

equation for DDS architecture:FOUT = (M (REFCLK)) /2N

Where: FOUT = the output frequency of the DDSM = the binary tuning word

REFCLK = the internal reference clock frequency (system clock)

N = the length in bits of the phase accumulator

Changes to the value of M in the DDS architecture result in immediate and phase-continuouschanges in the output frequency. In practical application, the M value, or frequency tuning

word, is loaded into an internal serial or byte-loaded register which precedes the parallel-

output delta phase register. This is generally done to minimize the package pin count of the

DDS device. Once the buffer register is loaded, the parallel-output delta phase register is

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clocked and the DDS output frequency changes. Generally, the only speed limitation to

changing the output frequency of a DDS is the maximum rate at which the buffer register can

be loaded and executed. Obviously, a parallel byte load control interface enhances frequency

hopping capability.

2.1.4 Phase Accumulator

The phase accumulator uses simple arithmetic operations to calculate the lookup table

address for each generated sample. It does this by dividing the desired frequency by thesample clock and multiplying the result by 2

48. This number is based on the bit resolution of

the phase register. For NI signal generators, a 48-bit phase register is used for maximum

precision. Of these, 34 bits are used to store the remainder phase, and 14 bits are used tochoose a sample from the lookup table.

Thus, the phase accumulator produces a 14-bit address that corresponds to the exact phase ofthe signal. For example, an address of ‗00000000000000‘ corresponds to 0°. On the other

hand, an address of ‗11111111111111‘ corresponds to 359.978°. Thus, the signal generator

can use this address to control the phase of the signal at any point in time. This is shown

below:

Fig 2.4 Computation of the Phase Register

As the diagram suggests, the phase accumulator is able to represent the phase of the

generated signal with 248

points of precision. However, because we only have 214

available

points in our waveform, only the 14 most significant bits of the phase register are used in thelookup table. The remaining 34 bits are used to store the remainder of the phase increment.

This remainder enables the DDS precision by ensuring that the lookup table will return the

appropriate phase information after the phase register rolls over (once per period of thewaveform).

2.2 Understanding the Sampled Output of a DDS Device

An understanding of sampling theory is necessary when analyzing the sampled output of a

DDSbased signal synthesis solution. The spectrum of a sampled output is illustrated in Figure2-1. In this example, the sampling clock (fCLOCK) is 300 MHz and the fundamental output

frequency (fOUT) is 80 MHz

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The Nyquist Theorem dictates that there is a minimum of two samples per cycle required to

reconstruct the desired output waveform. Images responses are created in the sampled output

spectrum at fCLOCK ± fOUT. The 1st image response occurs in this example at fCLOCK –

fOUT or 220 MHz. The 3rd, 4th, and 5th images appear at 380 MHz, 520 MHz, 680 MHz,and 820 MHz (respectively). Notice that nulls appear at multiples of the sampling frequency.

In the case of the fOUT frequency exceeding the fCLOCK frequency, the 1st image response

will appear within the Nyquist bandwidth (DC - ½ fCLOCK) as an aliased image. The aliasedimage

cannot be filtered from the output with the traditional Nyquist anti-aliasing filter.In typical DDS applications, a low pass filter is utilized to suppress the effects of the image

responses in the output spectrum. In order to keep the cutoff requirements on the low passfilter reasonable, it is an accepted rule to limit the fOUT bandwidth to approximately 40% of

the fCLOCK frequency. This facilitates using an economical low pass filter implementation

on the output. As can be seen in Figure, the amplitude of the FOUT and the image responsesfollows a sin(X)/X roll off response. This is due to the quantized nature of the sampled

output. The amplitude of the fundamental and any given image response can be calculated

using the sin(X)/X formula. Per the roll off response function, the amplitude of the

fundamental output will decreaseinversely to increases in its tuned frequency. The amplitude roll off due to sin(X)/X in a DDS

system is – 3.92 dB over its DC to Nyquist bandwidth. As was previously shown in Figure2.5, DDS architectures can include an inverse SINC filtering which pre-compensates for thesin(X)/X roll off and maintains a flat output amplitude (± .1 dB) from the D/A converter over

a bandwidth of up to 45% of the clock rate or 80% of Nyquist.

Fig 2.5 Spectral Analysis of Sampled Output

It is important to note in the sin(X)/X response curve shown in Figure 2-1 that the amplitudeof the 1st image is substantial: it is within 3dB of the amplitude of the fundamental at fOUT

= .33 fCLOCK. It is important to generate a frequency plan in DDS applications and analyze

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the spectral considerations of the image response and the sin(X)/X amplitude response at the

desired fOUT and fCLOCK frequencies.

The other anomalies in the output spectrum, such as integral and differential linearity errors

of the D/A converter, glitch energy associated with the D/A converter, and clock feed-through noise, will not follow the sin(X)/X roll-off response. These anomalies will appear as

harmonics and spurious energy in the output spectrum and will generally be much lower in

amplitude than the image responses. The general noise floor of a DDS device is determined by the cumulative combination of substrate noise, thermal noise effects, ground coupling, and

a variety of other sources of low-level signal corruption. The noise floor, spurs performance,and jitter performance

of a DDS device is greatly influenced by circuit board layout, the quality of its powersupplies, and the quality of the input reference clock.

2.3 Frequency/phase-hopping Capability of DDS

Calculating the Frequency Tuning Word

The output frequency of a DDS device is determined by the formula:

FOUT = (M (REFCLK)) /2NWhere: FOUT = the output frequency of the DDS

M = the binary tuning wordREFCLK = the internal reference clock frequency N = the length in bits of the phase accumulator

The length of the phase accumulator (N) is the length of the tuning word which determines

the degree of frequency tuning resolution of the DDS implementation. Let‘s find thefrequency tuning word for an output frequency of 41 MHz where REFCLK is 122.88 MHz

and the tuning word length is 32 bits (binary). The resulting equation would be:

41 MHz = (M (122.8 MHz)) /232

Solving for M… M = (41 MHz (232))/122.8 MHz

M= 556AAAAB hex

Loading this value of M into the frequency control register would result in frequency outputof 41 MHz, given a reference clock frequency of 122.8 MHz

Determining Maximum Tuning Speed

The maximum tuning speed of a DDS implementation is determined by the loading

configuration selected, parallel byte or serial word, and the speed of the control interface. Insome DDS applications, maximum output frequency tuning speed is desired. Applications

such as GMSK and ramped-FSK modulation require maximum frequency tuning speeds to

support spectrally-shaped transitions between modulation frequencies. When the tuning wordis loaded by the control interface, the constraint to frequency update is in the speed of the

interface port. Typically a DDS device will provide a parallel byte load which facilitates

getting data into the control registers at a higher rate. Control data clocking rates of 100 MHz

are typically supportedfor a byte-load parallel control interface. This means that a new tuning word can be present

on the output of a DDS device every 10 nS. The phase-continuous output of DDS frequency

transitions is well-suited for high-speed frequency-hopping applications. DDS devices also

usually provide a set of registers that can be pre-programmed with tuning words. Thecontents of these registers are executed with an external pin on the device package. This

provides for the maximum output frequency hopping speed between pre-programmed

frequency values. This arrangement is especially suitable for FSK modulation applicationswhere the ―mark‖ and ―space‖ frequencies can be readily pre-programmed. programmed

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registers, DDS output frequency hopping speeds of up to 250 MHz can be achieved with the

latest technology devices.

2.3.1 The DDS Control Interface

All of the functions, features, and configurations of a DDS device are generally programmedthrough the device‘s control interface port. The control interface for DDS devices is available

in a variety of configurations. The common configurations are serial interface and byte-load parallel interface. The interface conventions range from a single 40-bit register that stores all

of the functional control words, to a microprocessor-compatible a synchronous serialcommunications port. Control interface functionality and timing diagrams are detailed in the

data sheets for the individual DDS devices.

2.3.2 Profile Registers

Pre-programmed registers are typically available in a DDS device that allow enhanced

frequency or phase hopping of the output signal. The data contained in these registers areexecuted via a dedicated pin on the package and allow the use to change an operating

parameter without going through the control interface instruction cycle. Examples of thetypes of functions that can be pre-programmed are: Output frequency tuning word – this allows the user to achieve the maximum

frequency hopping capability with a DDS device. The availability of frequency

select registers also facilitates using the DDS device as an FSK modulatorwhere the input data directly steers the output to the desired mark and space

frequencies. Phase of the output frequency – this function allows the user to execute pre-

programmed increments of phase delay to the output signal. The amount of

delay resolution ranges from 11.5increments (5-bits) to .02increments (14- bits). Phase-shift keying modulation (PSK) can readily be accomplished with

the use of pre-programmed phase registers. In digital modulator and quadrature up converter implementations of DDS

architectures additional functions can be pre-programmed in profile registers.

These functions include FIR filter response, interpolation (up sampling) rates ,

and output spectral inversion enable/disable.

2.3.3 The Effect of Truncating the Phase Accumulator on Spurious Performance

Phase truncation is an important aspect of DDS architectures. Consider a DDS with a 32-bit phase accumulator. To directly convert 32 bits of phase to corresponding amplitude would

require 232

entries in a lookup table. That‘s 4,294,967,296 entries! If each entry is stored with

8-bit accuracy, then 4-gigabytes of lookup table memory would be required. Clearly, it would be impractical to implement such a design.The solution is to use a fraction of the most significant bits of the accumulator output to

provide phase information. For example, in a 32-bit DDS design, only the upper most 12 bits

might be used for phase information. The lower 20 bits would be ignored (truncated) in thiscase. To understand the implications of truncating the phase accumulator output it is helpful

to use the concept of the ―digital phase wheel‖. Consider a simple DDS architecture that uses

an 8-bit accumulator of which only the upper 5 bits are used for resolving phase. The phasewheel depiction of this particular model is shown in Figure. With an 8-bit accumulator, the

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phase resolution associated with the accumulator is 1/256th of a full circle, or1.41 (360/28).In Figure 2.6, the accumulator phase resolution is identified by the outer circle of tic marks. If

only the most significant 5 bits of the accumulator are used to convey phase information, then

the resolution becomes 1/32nd of a full circle, or 11.25 (360/25). These are identified by the

inner circle of tic marks. Now let us assume that a tuning word value of 6 is used. That is, theaccumulator is to count by increments of 6. The first four phase angles corresponding to 6-

count steps of the accumulator are depicted in Figure 2.6. Note that the first phase step (6

counts on the outer circle) falls short of the first inner tic mark. Thus, a discrepancy arises

between the phase of the accumulator (theouter circle) and the phase as determined by 5-bit resolution (the inner circle). This

discrepancy results in a phase error of 8.46 (6 x 1.41), as depicted by arc E1 in the figure.On the second phase step of the accumulator (6 more counts on the outer circle) the phase ofthe accumulator resides between the 1st and 2nd tic marks on the inner circle. Again, there is

a discrepancy between the phase of the accumulator and the phase as determined by 5 bits of

resolution. The result is an error of 5.64 (4 x 1.41) as depicted by arc E2 in the figure.

Similarly, at the 3rd phase step of the accumulator an error of 2.82 (2 x 1.41) results. Onthe 4

th phase step, however, the accumulator phase and the 5-bit resolution phase coincide

resulting in no phase error. This pattern continues as the accumulator increments by 6 counts

on the outer

circle each time.

Fig 2.6 Phase Truncation Error and the Phase Wheel

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Obviously, the phase errors introduced by truncating the accumulator will result in errors in

amplitude during the phase-to-amplitude conversion process inherent in the DDS. It turns out

that these errors are periodic. They are periodic because, regardless of the tuning word

chosen, after a sufficient number of revolutions of the phase wheel, the accumulator phaseand truncated phase will coincide. Since these amplitude errors are periodic in the time

domain, they appear as line spectra (spurs) in the frequency domain and are what is known as

phase truncation spurs.It turns out that the magnitude and distribution of phase truncation spurs is dependent on

three factors :1. Accumulator size (A bits)

2. Phase word size (P bits); i.e., the number of bits of phase after truncation

3. Tuning word (T)

2.4 Reference Clock Considerations

Direct Clocking of a DDS

The output signal quality of a direct digital synthesizer is dependent upon the signal quality

of the reference clock that is driving the DDS. Important quality aspects of the clock source,such as frequency stability (in PPM), edge jitter (in ps or ns), and phase noise (in dBc/Hz)

will be reflected in the DDS output. One quality, phase noise, is actually reduced according

to: 20 LOG (Fout/Fclk). This means that a 10 MHz output signal will have 20 dB less phasenoise than the 100 MHz reference clock that ―created‖ it. The figure below illustrates how

DDS processing is affected by phase noise and jitter of the input clock.

Fig 2.7 Reference clock edge uncertainty adversely affects DDS output signal quality

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Figure 2.7 shows how phase noise, expressed in the time domain as period jitter with units of

percent, is relative to the period of the waveform, and that absolute edge jitter is unaffected

by changes in frequency or period. The ―DDS Reference Clock‖ signals in Figure 5-1 showsthat edge jitter is a much higher percentage of the total period than the same edge jitter in the

―Squared-up Clock Output‖. This accounts for phase noise improvement through frequency

division even though the same amount of edge jitter is present on both clock periods.Reference clock edge jitter has nothing to do with the accuracy of the phase increment steps

taken by the phase accumulator. These step sizes are fixed by the frequency ―tuning‖ wordand are mathematically manipulated with excellent precision regardless of the quality of the

clock. In order for the digital phase step to be properly positioned in the analog domain, twocriteria

must be met: Appropriate amplitude (this is the DAC‘s job) Appropriate time (the clock‘s job)

The Complete-DDS IC‘s from Analog Devices provide an appropriately accurate DAC to

translate the digital phase steps to an analog voltage or current. But that is only half of the

job. The remaining half involves accurate timing of these amplitude steps that constitute theoutput sine wave. This is where minimum clock edge jitter and low phase noise are required

to support the precise capabilities of DDS. The phase noise improvement of the DDS outputrelative to the input clock becomes more apparent in the frequency domain. showing the phase noise of two different DDS reference clocks. The phase noise/jitter of 100MHz DDS

clock source 1 is much

more pronounced than that of clock source 2.Figure shows the 10 MHz DDS output responseto the two clock sources. Output 1 shows a 20 dB (10X improvement) in phase noise relative

to clock 1. Output 2 shows less phase noise than clock 2, although 20 dB is not apparent

since the noise floor of the instrument is limiting the measurement. Notice the presence of

low level output ―spurs‖ on the skirt of output 2. These spurious signals are due to thenecessary truncation of phase bits in the DDS phase-to-amplitude stage and the algorithm

used to perform the transformation. These spurious signals are also present in output 1 but the

signal‘s excessive phase noise is masking their presence. This demonstrates why phase noiseis important in maintaining good signal-to-noise ratio in radio and other noise-sensitive

systems.

2.5 Conclusion

The fundamentals to understand DDS technology i.e., the basic theory of operation involved is

discussed in this chapter.

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Chapter 3

AD9850

3.1 General Description

The AD9850 is a highly integrated device that uses advanced DDS technology coupled with aninternal high speed, high performance D/A converter and comparator to form a complete,digitally programmable frequency synthesizer and clock generator function. When referenced to

an accurate clock source, the AD9850 generates a spectrally pure, frequency/phase

programmable, analog output sine wave. This sine wave can be used directly as a frequency

source, or it can be converted to a square wave for agile-clock generator applications. The

AD9850‘s innovative high speed DDS core provides a 32-bit frequency tuning word, which

results in an output tuning resolution of 0.0291 Hz for a 125 MHz reference clock input. The

AD9850‘s circuit architecture allows the generation of output frequencies of up to one-half thereference clock frequency (or 62.5 MHz), and the output frequency can be digitally changed

(asynchronously) at a rate of up to 23 million frequencies per second. The device also providesfive bits of digitally controlled phase modulation, which enables phase shifting of its output inincrements of 180°, 90°, 45°, 22.5°, 11.25°, and any combination thereof. The AD9850 alsocontains a high speed comparator that can be configured to accept the (externally) filtered

output of the DAC to generate a low jitter square wave output. This facilitates the device‘s use

as an agile clock generator function. The frequency tuning, control, and phase modulation wordsare loaded into the AD9850 via a parallel byte or serial loading format. The parallel load format

consists of five iterative loads of an 8-bit control word (byte). The first byte controls phase modulation, power-down enable, and loading format; Bytes 2 to 5 comprise the 32-bit frequency

tuning word. Serial loading is accomplished via a 40-bit serial data stream on a single pin. The AD9850 Complete DDS uses advanced CMOS technology to provide this breakthrough level of

functionality and performance on just 155 mW of power dissipation (3.3 V supply). TheAD9850 is available in a space-saving 28-lead SSOP, surface-mount package. It is specified tooperate over the extended industrial temperature range of – 40°C to +85°C.

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3.2 Pin Description

PIN FUNCTION DESCRIPTION

Pin

No. Mnem

onic Function

4 to1,

D0 toD7

8-Bit Data Input. This is the 8-bit data port for iteratively

loading the 32-bit frequency and the 8-bit phase/

28

to25

control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves

as the input pin for the 40-bit serial data-word.

5,

24 DGND

Digital Ground. These are the ground return leads for the

digital circuitry.

6,23 DVDD

Supply Voltage Leadsfor Digital Circuitry.

7

W_CL

K

Word Load Clock. This clock is used to load the parallel

or serial frequency/phase/control words.

8 FQ_UD

Frequency Update. On the rising edge of this clock, the

DDS updates to the frequency (or phase)

loaded in the data input register; it then resets the pointer

to Word 0.

9 CLKINReference Clock Input. This may be a continuousCMOS-level pulse train or sine input biased at

1/2 V supply. The rising edge of this clock initiatesoperation.

10,

19 AGND

Analog Ground. These leads are the ground return for the

analog circuitry (DAC and comparator).11,

18 AVDD

Supply Voltage for the Analog Circuitry (DAC and

Comparator).

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12 R SET

DAC‘s External R SET Connection. This resistor value

sets the DAC full-scale output current. For Normal applications ( F S I out = 10 mA), the value for R SET is3.9 k Ω connected to ground. The R SET/IOUT Relationship is I OUT =

32 (1.248V/ RSET ).

13

QOUT

B

Output Complement. This is the comparator‘s

complement output.

14 QOUT Output True. This is the comparator‘s true output.

15 VINN

Inverting Voltage Input. This is the comparator‘s negative

input.

16 VINP

Noninverting Voltage Input. This is the comparator‘s

positive input.

17

DACB

L (NC)

DAC Baseline. This is the DAC baseline voltage reference;

this lead is internally bypassed and should

Normally be considered a no connect for optimum performance.

20 IOUTB

Complementary Analog

Output of the DAC.

21 IOUTAnalog Current Outputof the DAC.

22 RESET

Reset. This is the master reset function; when set high, it clears

all registers (except the input register), and The DAC output goes to cosine 0 after additional clock

cycles.

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3.3 Theory of operation and application

The AD9850 uses Direct Digital Synthesis (DDS) technology, in the form of a numerically controlled

oscillator, to generate a frequency phase-agile sine wave. The digital sine wave is converted to analog form via an internal 10-bit high speed D/A converter, and an on-board high speed comparator is

provided to translate the analog sine wave into a low jitter TTL/CMOS compatible output square

wave. DDS technology is an innovative circuit architecture that allows fast and precise manipulation ofits output frequency under full digital control. DDS also enables very high resolution in the

incremental selection of output frequency; the AD9850 allows an output frequency resolution of

0.0291 Hz with a 125 MHz refer ence clock applied. The AD9850‘s output waveform is phase

continuous when changed. The basic functional block diagram and signal flow of the AD9850

configured as a clock generator.

The DDS circuitry is basically a digital frequency divider function whose incremental resolution is

determined by the frequency of the reference clock divided by the 2 N number of bits in the

tuning word. The phase accumulator is a variable-modulus counter that increments the number

stored in it each time it receives a clock pulse. When the counter overflows, it wraps around,making the phase accumulator‘s output contiguous.

The frequency tuning word sets the modulus of the counter, which effectively determines the

size of the increment (Δ Phase) that is added to the value in the phase accumulator on the next

clock pulse. The larger the added increment, the faster the accumulator overflows, which

results in a higher output frequency.

The AD9850 uses an innovative and proprietary algorithm that mathematically converts the

14-bit truncated value of the phase accumulator to the appropriate COS value. This unique

algorithm uses a much reduced ROM look-up table and DSP techniques to perform this

function, which contributes to the small size and low power dissipation of the AD9850. Therelationship of the output frequency, reference clock, and tuning word of the AD9850 is

determined by the formula fOUT = (Δ Phase × CLKIN )/232

where:

Δ Phase is the value of the 32-bit tuning word.

CLKIN is the input reference clock frequency in MHz

fOUT is the frequency of the output signal in MHz

The digital sine wave output of the DDS block drives the internal high speed 10-bit D/A

converter that reconstructs the sine wave in analog form. This DAC has been optimized for

dynamic performance and low glitch energy as manifested in the low jitter performance of the

AD9850.

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Fig 3.2 Basic DDS Block Diagram and Signal Flow of AD9850

AD9850 is a sampled signal; its output spectrum follows the Nyquist sampling theorem.

Specifically, its output spectrum contains the fundamental plus aliased signals (images) that

occur at multiples of the reference clock frequency the selected output frequency. A

graphical representation of the sampled spectrum, with aliased images, is shown in Figure 3.3.

Fig 3.3 Output Spectrum of a Sampled Signal

In this example, the reference clock is 100 MHz and the output frequency is set to 20 MHz As

can be seen, the aliased images are very prominent and of a relatively high energy level as

determined by the sin(x)/x roll-off of the quantized D/A converter output. In fact, dependingon the reference clock relationship, the first aliased image can be on the order of – 3 dB belowthe fundamental. A low-pass filter is generally placed between the output of the D/A

converter and the input of the comparator to further suppress the effects of aliased images.

Obviously, consideration must be given to the relationship of the selected output frequency

and the reference clock frequency to avoid unwanted (and unexpected) output anomalies. To

apply the AD9850 as a clock generator, limit the selected output frequency to <33% of

reference clock frequency, and thereby avoid generating aliased signals that fall within, or

close to, the output band of interest (generally dc-selected output frequency). This practice

eases the complexity (and cost) of the external filter requirement for the clock generator

application. The reference clock frequency of the AD9850 has a minimum limitation of 1

MHz The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded and automatically places itself in the power-down mode. When in this state, if

the clock frequency again exceeds the threshold, the device resumes normal operation. This

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shutdown mode prevents excessive current leakage in the dynamic registers of the device. The

D/A converter output and comparator inputs are available as differential signals that can be

flexibly configured in any manner desired to achieve the objectives of the end system. The

typical application of the AD9850 is with single-ended output/ input analog signals, a single

low-pass filter, and the generation of the comparator reference midpoint from the differential

DAC output.

3.4 Programming the AD9850

The AD9850 contains a 40-bit register that is used to program the 32-bit frequency control

word, the 5-bit phase modulation word, and the power-down function. This register can be

loaded in a parallel or serial mode. In the parallel load mode, the register is loaded via an 8-bit

bus; the full 40-bit word requires five iterations of the 8-bit word. The W_CLK and FQ_UD

signals are used to address and load the registers. The rising edge of FQ_UD loads the (up to)

40-bit control data-word into the device and resets the address pointer to the first register.

Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to

the next register. After five loads, W_CLK edges are ignored until either a reset or an FQ_UD

rising edge resets the address pointer to the first register. In serial load mode, subsequentrising edges of W_CLK shift the 1-bit data on Pin 25 (D7) through the 40 bits of

programming information. After 40 bits are shifted through, an FQ_UD pulse is required to

update the output frequency (or phase). The function assignments of the data and control

words are shown in Table III; the detailed timing sequence for updating the output frequency

and/or phase, resetting the device, and powering up/down, are shown in the timing diagrams

of Figures 3.4 through 3.10.

Note: There are specific control codes, used for factory test purposes that render the AD9850

temporarily inoperable. The user must take deliberate precaution to avoid inputting the codes

listed in Table II.

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Fig 3.4 Parallel Load Frequency/Phase Update Timing Sequence

Table III. 8-Bit Parallel Load Data/Control Word Functional Assignment

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Note: the timing diagram above shows the minimal amount of reset time needed before

writing to the device. However, the master reset does not have to be synchronous with the clk

in if the minimal time is not required.

Results of reset:

– frequency/phase register set to 0

– address pointer reset to w0

– power-down bit reset to 0

– data input register unaffected

Fig 3.5 Master Reset Timing Sequence

Figure 3.6 Parallel Load Power-Down Sequence/Internal Operation

Fig 3.7 Parallel Load Power-Up Sequence/Internal Operation

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Figure 3.11 Serial Load Power-Down Sequence

Figure 3.12 AD9850 I/O Equivalent Circuits

3.5 PCB layout information

The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 15 through 18)

represent typical implementations of the AD9850 and exemplify the use of high

frequency/high resolution design and layout practices. The printed circuit board that contains

the AD9850 should be a multilayer board that allows dedicated power and ground planes. The

power and ground planes should be free of etched traces that cause discontinuities in the

planes. It is recommended that the top layer of the multilayer board also contain an

interspatial ground plane, which makes ground available for surface-mount devices. If

separate analog and digital system ground planes exist, they should be connected together at

the AD9850 for optimum results. Avoid running digital lines under the device because these

couple noise onto the die. The power supply lines to the AD9850 should use as large a track

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as possible to provide a low impedance path and reduce the effects of glitches on the power

supply line. Fast switching signals like clocks should be shielded with ground to avoid

radiating noise to other sections of the board. Avoid crossover of digital and analog signal

paths. Traces on opposite sides of the board should run at right angles to each other. This

reduces the effects of feed through through the circuit board. Use micro strip techniques

where possible. Good decoupling is also an important consideration. The analog (AVDD) and

digital (DVDD) supplies to the AD9850 are independent and separately pinned out to

minimize coupling between analog and digital sections of the device. All analog and digital

supplies should be decoupled to AGND and DGND, respectively, with high quality ceramic

capacitors. To achieve best performance from the decoupling capacitors, they should be

placed as close as possible to the device, ideally right up against the device. In systems where

a common supply is used to drive both the AVDD and DVDD supplies of the AD9850, it is

recommended that the system‘s AVDD supply be used. Analog Devices, Inc. applications

engineering support is available to answer additional questions on grounding and PCB layout.

3.6 Evaluation Boards

Two versions of evaluation boards are available for the AD9850, which facilitate theimplementation of the device for bench top analysis and serve as a reference for PCB layout.

The AD9850/FSPCB is used in applications where the device is used primarily as a frequency

synthesizer. This version facilitates

connection of the AD9850‘s internal D/A converter output to a 50 Ω spectrum analyzer input;the internal comparator on the AD9850 DUT is not enabled (see Figure 15 for an electrical

schematic of AD9850/FSPCB). The AD9850/CGPCB is used in applications using the device

in the clock generator mode. It connects the AD9850‘s DAC output to the internal comparator

input via a single-ended, 42 MHz low-pass, 5-pole elliptical filter. This model facilitates the

access of the AD9850‘s comparator output for evaluation of the device as a frequency- and

phase-agile clock source (see Figure 17 for an electrical schematic of AD9850/CGPCB). Both

versions of the AD9850 evaluation board are designed to interface to the parallel printer portof a PC. The operating software runs under Microsoft® Windows® and provides a user

friendly and intuitive format for controlling the functionality and observing the performance

of the device. The 3.5 inch floppy provided with the evaluation board contains an executable

file that loads and displays the AD9850 function-selection screen. The evaluation board can

be operated with 3.3 V or 5 V supplies. The evaluation boards are configured at the factory

for an external reference clock input; if the on-board crystal clock source is used, remove R2.

3.7 AD9850 Evaluation Board Instructions3.7.1 Required Hardware/Software

IBM compatible computer operating in a Windows environment.

Printer port, 3.5 inch floppy drive, and Centronics compatible printer cable.

XTAL clock or signal generator — if using a signal generator, dc offset the signal to

one-half the supply voltage and apply at least 3 V p-p signal across the 50 Ω (R2) input

resistor. Remove R2 for high Z clock input.

AD9850 evaluation board software disk and AD9850/FSPCB or AD9850/CGPCB

evaluation board.

5 V voltage supply.

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3.7.2 Setup

1. Copy the contents of the AD9850 disk onto your hard drive (there are three files).

2. Connect the printer cable from your computer to the AD9850 evaluation board.

3. Apply power to AD9850 evaluation board. The AD9850 is powered separately from the

connector marked DUT +V. The AD9850 may be powered with 3.3 V to 5 V.

4. Connect external 50 Ω clock or remove R2 and apply a high Z input clock such as a crystal

can oscillator.

5. Locate the file called 9850REV2.EXE and execute that program.

6. Monitor should display a control panel to allow operation of the AD9850 evaluation board.

3.7.3 Operation

On the control panel, locate the box called COMPUTER I/O. Point to and click the selection

marked LPT1 and then point to the TEST box and click. A message will appear telling users

if their choice of output ports is correct. Choose other ports as necessary to achieve a correct

setting. If they have trouble getting their computer to recognize any printer port, they shouldtry the following: connect three 2 k Ω pull-up resistors from Pins 9, 8, and 7 of U3 to 5 V. This

will assist weak printer port outputs in driving the heavy capacitance load of the printer cable.

If troubles persist, try a different printer cable. Locate the MASTER RESET button with themouse and click it. This will reset the AD9850 to 0 Hz, 0° phase. The output should be a dc

voltage equal to the full-scale output of the AD9850.Locate the CLOCK box and place the

cursor in the frequency box. Type in the clock frequency (in MHz) that the user will be

applying to the AD9850. Click the LOAD button or press enter on the keyboard. Move the

cursor to the OUTPUT FREQUENCY box and type in the desired output frequency (in

MHz). Click the LOAD button or press the enter key. The BUS MONITOR section of the

control panel will show the 32-bit word that was loaded into the AD9850. Upon completion

of this step, the AD9850 output should be active and outputting the user's frequencyinformation. Changing the output phase is accomplished by clicking on the down arrow in the

OUTPUT PHASE DELAY box to make a selection and then clicking the LOAD button.

Other operational modes (frequency sweeping, sleep, serial input) are available to the user via

keyboard/mouse control. The AD9850/FSPCB provides access into and out of the on-chip

comparator via test point pairs (each pair has an active input and a ground connection). The

two active inputs are labeled TP1 and TP2. The unmarked hole next to each labeled test point

is a ground connection. The two active outputs are labeled TP5 and TP6. Unmarked ground

connections are adjacent to each of these test points. The AD9850/CGPCB provides BNC

inputs and outputs associated with the on-chip comparator and the on-board, fifth-order, 200Ω input/output Z, elliptic, 45 MHz, low-pass filter. Jumpering (soldering a wire) E1 to E2, E3

to E4, and E5 to E6 connects the on-board filter and the midpoint switching voltage to thecomparator. Users may elect to insert their own filter and comparator threshold voltage by

removing the jumpers and inserting a filter between J7 and J6 and then providing a threshold

voltage at E1. If users choose to use the XTAL socket to supply the clock to the AD9850,

they must remove R2 (a 50 Ω chip resistor). The crystal oscillator must be either TTL or

CMOS (preferably) Compatible.

3.8 Conclusion

The signal flow, programming the AD9850 and other necessary information related to its

operation is discussed in this chapter.

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Chapter-4

ARDUINO

Arduino is an open-source electronics prototyping platform based on flexible, easy-to-

use hardware and software. It's intended for artists, designers, hobbyists, and anyoneinterested in creating interactive objects or environments. Arduino can sense the environment

by receiving input from a variety of sensors and can affect its surroundings by controlling

lights, motors, and other actuators. The microcontroller on the board is programmed using the

Arduino programming language (based on Wiring) and the Arduino development

environment (based on Processing).

The boards can be built by hand or purchased preassembled; the software can be

downloaded for free. The hardware reference designs (CAD files) are available under an

open-source license.

4.1 ARDUINO pin description

The Arduino Uno is a microcontroller board based on the ATmega328. It has 14 digital

input/output pins (of which 6 can be used as PWM outputs), 6 analog inputs, a

16 MHz ceramic resonator, a USB connection, a power jack, an ICSP header, and a reset

button. It contains everything needed to support the microcontroller; simply connect it to a

computer with a USB cable or power it with an AC-to-DC adapter or battery to get started.

The Uno differs from all preceding boards in that it does not use the FTDI USB-to-serial

driver chip. Instead, it features the Atmega16U2 (Atmega8U2 up to version R2) programmed

as aUSB-to-serial converter.

http://arduino.cc/en/Reference/HomePage

http://wiring.org.co/

http://www.processing.org/

http://arduino.cc/en/Main/ArduinoBoardSerialSingleSided3

http://arduino.cc/en/Main/Buy

http://arduino.cc/en/Main/Software

http://arduino.cc/en/Main/Products

http://arduino.cc/en/Main/Products


http://arduino.cc/en/Main/Buy

http://arduino.cc/en/Main/ArduinoBoardSerialSingleSided3

http://www.processing.org/

http://wiring.org.co/

http://arduino.cc/en/Reference/HomePage

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Figure 4.1ARDUINO UNO Description

Revision 2 of the Uno board has a resistor pulling the 8U2 HWB line to ground, making it

easier to put into DFU mode.

Revision 3 of the board has the following new features:

1.0 pin out: added SDA and SCL pins that are near to the AREF pin and two other new

pins placed near to the RESET pin, the IOREF that allow the shields to adapt to the voltage

provided from the board. In future, shields will be compatible both with the board that usesthe AVR, which operate with 5V and with the Arduino Due that operate with 3.3V. The

second one is a not connected pin that is reserved for future purposes.

Stronger RESET circuit.

At mega 16U2 replace the 8U2.

"Uno" means one in Italian and is named to mark the upcoming release of Arduino 1.0.

The Uno and version 1.0 will be the reference versions of Arduino, moving forward. The Uno

is the latest in a series of USB Arduino boards, and the reference model for the Arduino

platform; for a comparison with previous versions, see the index of Arduino boards.

http://arduino.cc/en/Hacking/DFUProgramming8U2

http://arduino.cc/en/Main/Boards

http://arduino.cc/en/Main/Boards

http://arduino.cc/en/Hacking/DFUProgramming8U2

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of the board (7-12V). Supplying voltage via the 5V or 3.3V pins bypasses the regulator, and

can damage your board. We don't advise it.

3.3V.

A 3.3 volt supply generated by the on-board regulator. Maximum current draw is 50 mA.

GND.

Ground pins.

IOREF

This pin on the Arduino board provides the voltage reference with which the microcontroller

operates. A properly configured shield can read the IOREF pin voltage and select the

appropriate power source or enable voltage translators on the outputs for working with the 5V

or 3.3V.

Memory

The ATmega328 has 32 KB (with 0.5 KB used for the boot loader). It also has 2 KB of

SRAM and 1 KB of EEPROM (which can be read and written with the EEPROM library).

Input and Output

Each of the 14 digital pins on the Uno can be used as an input or output,

using pinMode(), digitalWrite(), and digitalRead()f unctions. They operate at 5 volts. Each pin

can provide or receive a maximum of 40 mA and has an internal pull-up resistor

(disconnected by default) of 20-50 ohms. In addition, some pins have specialized functions:

Serial: 0 (RX) and 1 (TX). Used to receive (RX) and transmit (TX) TTL serial data.

These pins are connected to the corresponding pins of the ATmega8U2 USB-to-TTL Serial

chip.

External Interrupts: 2 and 3. These pins can be configured to trigger an interrupt on a

low value, a rising or falling edge, or a change in value. See the attachInterrupt () function for

details.

PWM: 3, 5, 6, 9, 10, and 11. Provide 8-bit PWM output with

the analogWrite() function.

SPI: 10 (SS), 11 (MOSI), 12 (MISO), 13 (SCK). These pins support SPI

communication using the SPI library.

LED: 13. There is a built-in LED connected to digital pin 13. When the pin is HIGHvalue, the LED is on, when the pin is LOW, it's off.

The Uno has 6 analog inputs, labeled A0 through A5, each of which provide 10 bits of

resolution (i.e. 1024 different values). By default they measure from ground to 5 volts, though

is it possible to change the upper end of their range using the AREF pin and

the analogReference() function. Additionally, some pins have specialized functionality:

TWI: A4 or SDA pin and A5 or SCL pin. Support TWI communication using

the Wire library.

There are a couple of other pins on the board:

AREF. Reference voltage for the analog inputs. Used with analogReference(). Reset. Bring this line LOW to reset the microcontroller. Typically used to add a reset

button to shields which block the one on the board.

http://www.arduino.cc/en/Reference/EEPROM

http://arduino.cc/en/Reference/PinMode

http://arduino.cc/en/Reference/DigitalWrite

http://arduino.cc/en/Reference/DigitalRead

http://arduino.cc/en/Reference/AttachInterrupt

http://arduino.cc/en/Reference/AnalogWrite

http://arduino.cc/en/Reference/SPI

http://arduino.cc/en/Reference/AnalogReference

http://arduino.cc/en/Reference/Wire






http://arduino.cc/en/Reference/AnalogWrite

http://arduino.cc/en/Reference/AttachInterrupt

http://arduino.cc/en/Reference/DigitalRead

http://arduino.cc/en/Reference/DigitalWrite

http://arduino.cc/en/Reference/PinMode

http://www.arduino.cc/en/Reference/EEPROM

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4.1.3 Communication

The Arduino Uno has a number of facilities for communicating with a computer, anotherArduino, or other microcontrollers. The ATmega328 provides UART TTL (5V) serial communication,which is available on digital pins 0 (RX) and 1 (TX). An ATmega16U2 on the board channels thisserial communication over USB and appears as

a virtual com port to software on the computer. The '16U2 firmware uses the standard USBCOM drivers, and no external driver is needed. However, on Windows, an .inf file is required.

The Arduino software includes a serial monitor which allows simple textual data to be sent to

and from the Arduino board. The RX and TX LEDs on the board will flash when data is being

transmitted via the USB-to-serial chip and USB connection to the computer (but not for serial

communication on pins 0 and 1).

A Software Serial library allows for serial communication on any of the Uno's digital

pins. The ATmega328 also supports I2C (TWI) and SPI communication. The Arduino

software includes a Wire library to simplify use of the I2C bus; see the documentation for

details. For SPI communication, use the SPI library.

4.1.4 Programming

The Arduino Uno can be programmed with the Arduino software (download). Select

"Arduino Uno from the Tools > Board menu (according to the microcontroller on your

board).

The ATmega328 on the Arduino Uno comes preburned with a boot loader that allows

you to upload new code to it without the use of an external hardware programmer. It

communicates using the original STK500 protocol (reference, C header files).

The ATmega16U2 (or 8U2 in the rev1 and rev2 boards) firmware source code is

available . The ATmega16U2/8U2 is loaded with a DFU boot loader, which can be activated

by:

On Rev1 boards: connecting the solder jumper on the back of the board (near the mapof Italy) and then resetting the 8U2.

On Rev2 or later boards: there is a resistor that pulling the 8U2/16U2 HWB line to

ground, making it easier to put into DFU mode.

4.1.5 Automatic (software) RESET

Rather than requiring a low), the reset line drops long enough to reset the chip. The Arduinosoftware uses this capability to allow you to upload code by simply pressing the upload button in the

Arduino environment. This means physical press of the reset button before an upload, the ArduinoUno is designed in a way that allows it to be reset by software running on a connected computer. One

of the Hardware flow control lines (DTR) of theATmega8U2/16U2 is connected to the reset line ofthe ATmega328 via a 100 nanofarad capacitor. When this line is asserted (taken that the boot loadercan have a shorter timeout, as the lowering of DTR can be well-coordinated with the start of the

upload.

This setup has other implications. When the Uno is connected to either a computer

running Mac OS X or Linux, it resets each time a connection is made to it from software (via

USB). For the following half-second or so, the boot loader is running on the Uno. While it is

programmed to ignore malformed data (i.e. anything besides an upload of new code), it will

intercept the first few bytes of data sent to the board after a connection is opened. If a sketch

running on the board receives one-time configuration or other data when it first starts, make

sure that the software with which it communicates waits a second after opening the

connection and before sending this data.The Uno contains a trace that can be cut to disable the auto-reset. The pads on either

side of the trace can be soldered together to re-enable it. It's labeled "RESET-EN". You may

http://arduino.cc/en/Guide/Windows#toc4

http://www.arduino.cc/en/Reference/SoftwareSerial




http://arduino.cc/en/Tutorial/Bootloader

http://www.atmel.com/dyn/resources/prod_documents/doc2525.pdf

http://www.atmel.com/dyn/resources/prod_documents/avr061.zip

http://www.atmel.com/dyn/resources/prod_documents/avr061.zip

http://www.atmel.com/dyn/resources/prod_documents/doc2525.pdf

http://arduino.cc/en/Tutorial/Bootloader




http://www.arduino.cc/en/Reference/SoftwareSerial

http://arduino.cc/en/Guide/Windows#toc4

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also be able to disable the auto-reset by connecting a 110 ohm resistor from 5V to the reset

line; see this forum thread for details.

4.1.6 USB over connection protection

The Arduino Uno has a resettable polyfuse that protects your computer's USB ports

from shorts and over current. Although most computers provide their own internal protection,

the fuse provides an extra layer of protection. If more than 500 mA is applied to the USB port,the fuse will automatically break the connection until the short or overload is removed.

4.1.7 Physical characteristics

The maximum length and width of the Uno PCB are 2.7 and 2.1 inches respectively,

with the USB connector and power jack extending beyond the former dimension. Four screw

holes allow the board to be attached to a surface or case. Note that the distance between

digital pins 7 and 8 is 160 mil (0.16"),not an even multiple of the 100 mil spacing of the other

pins.

Arduino programs are written in C or C++. The Arduino IDE comes with a software

library called "Wiring" from the original Wiring project, which makes many commoninput/output operations much easier.

4.2 Conclusion

Pin description and its functioning and programming Arduino are discussed in this chapter.

http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1213719666/all

http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1213719666/all

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Chapter 5

IMPLEMENTATION OF PROJECT

5.1 Block Diagram

5.2 Algorithm

1. Start

2. Configuration of pins

3. Send 32 bit frequency

4. Dividing the given 32bit frequency in to 4bytes

3b.transfering a byte taking 1 bit at a time

4. Frequency update

5. Connect the output to the CRO.

6. Sine of desired frequency is obtained

7. End

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5.4 Program

#define W_CLK 8 // Pin 8 - connect to AD9850 module word load clock pin (CLK)#define FQ_UD 9 // Pin 9 - connect to freq update pin (FQ)

#define DATA 10 // Pin 10 - connect to serial data load pin (DATA)

#define RESET 11 // Pin 11 - connect to reset pin (RST).

#define pulseHigh(pin) digitalWrite(pin, HIGH); digitalWrite(pin, LOW);

// transfers a byte, a bit at a time, LSB first to the 9850 via serial DATA line

void tfr_byte(byte data)

for (int i=0; i<8; i++, data>>=1)

digitalWrite(DATA, data & 0x01);

pulseHigh(W_CLK); //after each bit sent, CLK is pulsed high

// frequency calc from datasheet page 8 = <sys clock> * <frequency tuning word>/2^32

void sendFrequency(double frequency)

int32_t freq = frequency * 4294967295/125000000; // note 125 MHz clock on 9850

for (int b=0; b<4; b++, freq>>=8)

tfr_byte(freq & 0xFF);

tfr_byte(0x000); // Final control byte, all 0 for 9850 chip

pulseHigh(FQ_UD); // Done! Should see output

void setup()

// configure arduino data pins for output

pinMode(FQ_UD, OUTPUT);

pinMode(W_CLK, OUTPUT);

pinMode(DATA, OUTPUT);

pinMode(RESET, OUTPUT);

pulseHigh(RESET);

pulseHigh(W_CLK);

pulseHigh(FQ_UD); // this pulse enables serial mode - Datasheet page 12 figure 10

void loop()

sendFrequency(10.e6); // freq

while(1);

5.5 Conclusion

The algorithm, flow chart and the program used for the implementation of the project are

discussed in this chapter.

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Chapter-6

RESULT

Figure 6.1 DDS Module

Figure 6.2 Protoshield

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Figure 6.5 Final output waveform

6.1 Conclusion

The results obtained finally are discussed in this chapter.

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Chapter 7

APPLICATIONS AND FUTURE SCOPE

7.1 Applications

Frequency/Phase — Agile Sine Wave Synthesis

Clock Recovery and Locking Circuitry for Digital Communications

Digitally Controlled ADC Encode Generator

Agile Local Oscillator Applications

7.2 Future scope

The DDS is better suited to base stations than to mobiles, because power consumption is

high in the wide output bandwidth DDS. The scaling of the IC technologies constantly

reduces power consumption in digital circuitry. The same benefit is however not easily

achieved in analog circuits. Therefore, the DDS might also be suitable for the mobiles inthe future.

7.3 Conclusion

Applications and future scope of this project are clearly discussed in this chapter.

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CHRONOLOGICAL

BIBLIOGRAPHY

[1] Comparative Study of PLL, DDS and DDS-based PLL Synthesis Techniques for

Communication System by Govind Singh Patel & Sanjay Sharma.

[2]GRIET Arduino manual.

[3] DDS Design, By David Brandon, EDN , May 13, 2004.

[4] A Technical Tutorial on Digital Signal Synthesis, Direct Digital 1999, Analog

Devices, Inc. .

[5] David Buchanan, "Choosing DACs for Direct Digital Synthesis," Application Note

AN-237, Analog Devices, Inc.

[6] David Brandon, "Direct Digital Synthesizers in Clocking Applications,"

Application Note AN-823, Analog Devices, 2006.

[7] Richard J. Kerr and Lindsay A. Weaver, "Pseudorandom Dither for Frequency

Synthesis Noise," U.S.

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Appendix A

GLOSSARY OF DIGITAL COMMUNICATIONS SYSTEMS-

RELATED TERMS

A/D Converter (also A/D or ADC) Short for analog-to-digital converter. This device

converts real-world analog signals into a digital format that can be processed by a

computer. Video-speed A/D converters are those able to digitize video bandwidth signals

(greater than

1MHz): some are capable of sampling at rates up to 500 million samples- per-second

(Msps) and beyond. The most common architectures for video-speed A/D converters are"flash" and

"subranging."

AC Linearity A dynamic measurement of how well an A/D performs. In an ideal

A/D converter, a pure sine wave on the analog input appears at the digital output as a pure

(sampled) sine wave. In the real world, however, spurious signals due to nonlinear

distortion within the A/D appear in the digital output. These anomalies are usually

combinations of harmonics of the fundamental and intermodulation products, produced

when the fundamental and its harmonics beat with the sampling frequency. Only thespurious and harmonically-related signals that fall within the A/D's input bandwidth (half

the sampling rate) are generally considered important. AC linearity is usually characterized

in terms of harmonic distortion, signal-to-noise ratio, and intermodulation distortion performance.

Acquisition Time This term relates to sampling A/D's which utilize a track/hold amplifier

on the input to acquire and hold (to a specified tolerance) the analog input signal.

Acquisition time is the time required by the T/H amp to settle to its final value after it is

placed in the track mode. Active Filter An active filter is one that uses active devices such

as operational amplifiers to synthesize the filter response function. This technique has an

advantage at high speeds because the need for inductors (with their poor high-frequency

characteristics) is eliminated. Aliased Imaging This is a technique, commonly applied to

Direct Digital Synthesis (DDS), for using intentional aliasing as a source of high-

frequency signals. The following spectral plot illustrates a DDS output with a clock

frequency of 51MHz and fundamental output of 25.5MHz. Aliased images appear at32MHz, 70MHz, 83MHz, etc., which can be used as signal sources when isolated with a

bandpass filter.

Aliasing In a sampled data system, the analog input must be sampled at a rate of F S>2FA in

order to avoid loss of data (Nyquist Theorem). Adhering to the Nyquist Theorem prevents

in-band "alias" signals, which are beat frequencies between the analog signal and the

sampling clock that inherently occur at FS FA. As the Nyquist limit is exceeded, the

aliased signals move within the band of the analog input (DC - FS/2) and create distortion.

Likewise, high frequency noise can also be aliased into the input signal range which

mandates low-pass filtering, or anti-alias filtering, on the input of a sampled system. See

also Aliased Imaging.

Analog Ground In high-speed data acquisition applications, system ground is generally

physically separated into "analog" and "digital" grounds in an attempt to suppress digital

switching noise and minimize its effect on noise-sensitive analog signal processing

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circuitry. Input signal conditioners, amplifiers, references, and A/D converters are usually

connected to analog ground. Aperture Delay Time This term applies to A/D converters and

Track/hold amplifiers and defines the time elapsed from the application of the "hold" (or

"encode") command until the sampling switch opens fully and the device actually takes the

sample. Aperture delay time is a fixed delay time and is normally not in itself an error

source since the "hold" clock edge can be advanced to compensate for it.

Aperture Jitter Uncertainty, or sample-to-sample of variation, in the aperture delay time.

Aperture jitter is a source of error in a sampling system and it determines the maximum

slew rate limitation of the sampled analog input signal for a given system resolution.

D/A Converter (also D/A or DAC) Short for digital-to-analog converter, this is a device

that changes a digitally-coded word into its "equivalent" quantized analog voltage or

current. Just like the A/D device, there are very high-speed D/A's available, capable of

converting at data rates up to 1GHz.

Direct Digital Synthesis (DDS) A process by which you can digitally generate a

frequency agile, highly-pure sine wave, or arbitrary waveform, from an accurate reference

clock. The digital output waveform is typically tuned by a 32-bit digital word which allows

sub-Hz frequency agility. The DDS's frequency output is normally reconstructed with a

high-speed, high- performance D/A to generate an analog output signal. The ability to addinternal functions such as phase modulation, amplitude modulation, digital filtering, and

I&Q outputs, are making DDS devices attractive for digital communication applications.

They serve in capacities such as modulators, local oscillators, and clock detect/recovery

circuits.

Jitter Unwanted variations in the frequency or phase of a digital or analog signal.

Nyquist Theorem This theorem says that if a continuous bandwidth-limited signal

contains no frequency components higher than f C then the original signal can be recovered

without distortion if it is sampled at a rate of at least 2 f C.. This theorem applies to A/D

converter applications as well as data transmission density over limited bandwidth

channels.

Sin(X)/X The output of a D/A converter is a series of quantized levels that represent an

analog signal whose amplitude is determined by the sin (X)/X response. At higher output

frequencies, a D/A converter application may require a sin(X)/X compensation filter to

normalize its output amplitude.

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Appendix B

JITTER

Jitter Reduction in DDS Clock Generator SystemsOne of the most frequently asked questions regarding DDS clock generator applications is

how to minimize clock edge jitter. Here are some basic steps in assuring best jitter

performance:

1. Use a stable reference clock for the DDS

2. Filter the DDS output to reduce all non-harmonic spurs to at least – 65 dBc.

3. Drive the comparator inputs differentially.

4. Provide plenty of comparator over-drive (at least 1 volt p-p).

5. Provide low Z inputs to the comparator to suppress high Z noise sources.

6. Use an external comparator or divider for very demanding applications.7. Avoid using slow slew rate signals.

8. Use spur reduction techniques.

Using a stable reference clock to the DDS is obvious since jitter in = jitter out. Filtering of

the DDS output requires some elaboration. Bandpass filtering is best since spurs may

reside well below and above the fundamental output. If wideband output is required, then a

low pass filter is the only choice, but jitter performance will be compromised. To make

filtering easier, keep the system clock frequency as high as possible to distance the image

spurs as far as possible from the fundamental. Driving the comparator inputs with a low

impedance, differential, 1 V p- p input signal is ―as good as it gets‖. The low impedance

input discourages extraneous noise and comparator ―kick - back‖. The merits of differential

inputs include common-mode noise rejection and 2X the input slew rate. A passive broadband 1:1 RF transformer is useful in changing from single-ended to differential

configuration; however, it will not pass dc so some means of biasing to the comparator

input range may be needed. Sufficient comparator input overdrive keeps output dispersion

(variation in propagation delay) to a minimum and promotes decisive switching. Use of an

off-chip comparator is recommended since the hostile (noisy) DDS environment degrades

jitter performance. In choosing an external high-speed comparator, look for good PSRR

specifications, proper output logic levels, low dispersion and single supply operation.

5 MHz and above: These are the easiest signals to handle due to their fast slew rates. A

reason able jitter figure for these frequencies is about 75 ps p-p using the above techniques.

Higher frequency signals have higher harmonic distortion. This is not bad until the

harmonic is ―aliased‖ back into the pass band to the comparator where it becomes a non-

harmonically related product that will increase jitter.

Aliased harmonics can be reduced by passing the filtered fundamental and spurs to a

passive frequency mixer, up converting to a much higher frequency and then dividing

down (example VHF divider is a Mitel SP8402) to your desired output frequency. The

frequency division process does two very desirable things:

1. Reduces spurious components by 20LOG(N) – where N is the division ratio.

2. Gives you a square wave output which may eliminate the need for a comparator if the

divider has suitable logic levels.

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Below 5 MHz: Much more difficult to get good jitter performance due to the slow slew

rate of the fundamental.

Best results are obtained by outputting a much higher frequency than needed and then

dividing down to your

Desired output. The same benefits as 1 and 2 above will apply. This method of spur

reduction is especially useful

When extremely low frequencies with low jitter are needed. Depending on external

frequency division ratios, jitter

Levels approaching 75 ps p-p seem obtainable. Without frequency division, a 1 khz sine

wave could produce 10 ns p-p jitter just due to the slow slew to the comparator .

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