Preliminary Product Information This document conCirrus Logic reserv

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Cirrus Logic, Inc.Crystal Semiconductor Products DivisionP.O. Box 17847, Austin, Texas 78760(512) 445 7222 FAX: (512) 445 7581http://www.crystal.com

CDB5180

Evaluation Board for the CS5180

Features

lBuffered Serial Data Outputl Input Signal Conditioning AmplifierslOn-board 3 Volt regulatorlAnalog/Digital Patch AreaslAnalog BNC Input ConnectorlProvision for optional precision voltage

referencelCompatible with CDBCapture+ boardlProvision for evaluation of CS5180 with

internal digital filter enabled or disabled (one-bit mode)

DescriptionThe CDB5180 is an evaluation board that expedites thelaboratory characterization of the CS5180 A/D convert-er. The CS5180 is a 16-bit high speed delta-sigmaconverter with a serial output having an output word rateof up to 400 kHz. The board accepts single-ended or dif-ferential input signals and buffers the serial output of theCS5180 before sending it to a header for off-board use.The output header signals on the evaluation board aredesigned to be compatible with the CDBCapture+board. An on-board 3 Volt regulator allows the CS5180to be evaluated with either 3 or 5 Volt digital supplies.The converter can be operated with it’s internal voltagereference although the layout makes provision for add-ing an external precision reference as a user-suppliedoption.

ORDERING INFORMATIONCDB5180 Evaluation Board

I

CS5180

MCLK

AIN+

AIN-

VREFOUT

VREFIN

SCLK

SDATA

SDATA

FSO

CLOCKGENERATOR

25.6 MHz

ANALOGSIGNAL

CONDITIONING

EXTERNALPRECISION

REFERENCEOPTION

AIN10 POS.SERIAL

OUTPUTHEADER

BUFFERS

+3 VREGULATOR

+5 VD

+3 VD

+5 VA

5 V DIGITAL

5 V ANALOG

+15 V

-15 V

AGND

DGND

RESET andSYNC

CONDITIONING

RESET SYNC

RESET

SYNC

tains information for a new product.es the right to modify this product without notice.

1

ht Cirrus Logic, Inc. 1998All Rights Reserved)

DEC ‘98DS259DB1

CDB5180

POWER SUPPLIES AND VOLTAGE REFERENCE

Figure 1 illustrates the power supply and precisionvoltage reference circuits. The CDB5180 evalua-tion board has inputs for 4 regulated voltages,+5 Volts Digital, +5 Volts Analog, +15 Volts, and-15 Volts. As an option, one 5 Volt power supplymay be used to power both the analog and digitalportions of the converter. This is done by installingHDR17 and connecting the 5 Volt supply to postJ7. An on-board 3 Volt regulator allows for theconverter’s digital circuitry to be powered from ei-ther 5 Volts or 3 Volts. This selection is achievedby setting header HDR13 to either the +5VD or+3VD position. The plus and minus 15 Volts areused to power the analog signal conditioning cir-cuits external to the converter. The analog 5 Voltsupply can be used to power a precision 2.5 Voltreference, an LT1019-2.5 or equivalent, which can

be substituted for the converter’s on-board refer-ence to achieve lower drift. The board is suppliedwith the external reference and it’s passive compo-nents depopulated. If it is desired to use an exter-nal reference, then the following steps must becompleted.

1) Remove zero-ohm resistor R32 and install azero-ohm resistor in the R33 position.

2) Install the following components: U10, C38,C56, R22, C59, and R25.

3) Set the reference voltage to the desired value byadjusting potentiometer R22.

The output of the internal reference is connected tothe operational amplifiers through zero-ohm resis-tor R54. If it is desired to use the external referenceto drive the signal conditioning circuits, then R54must be removed and a zero-ohm resistor installedin position R55.

Z31N6276A

Z21N6276A

.1 µFX7R

.1 µFX7R

C57

C58

C4668 µF

C5268 µF

AGND

+

++15 V

-15 V

+5 VA

C38

10 µF

+

.1 µFX7R

C56

AGND

U10 4

3

7

5

6

GND TEMP

HIR

TRIM

OUTIN

LT1019CN8_2P52

TP12VREF_AMPFIGURE 4

R22

20 K

CW

PRECISION VOLTAGE REFERENCE OPTION

GND

C53

.1 µFX7R C26

68 µF

AGND

+5 VA

+

L1FERRITEBEAD

GND GND GND

AGND

Z11N6276A

.1 µFX7R

C22

C368 µF

+ 2

1HDR17

3VIN VOUT

ADJ

LT317AT

1 R11249

R12392

2

.1 µFX7R

C21

C268 µF

+

+3 VD

HDR13

+5 VD

L2FERRITE

BEAD 1 2HDR14

VCCIO

C5910 µF

+

VDDD

U7

Z4P6KE6V8P

AGND

J8

J7

J3

J4

J5

GNDAGND

JP1

JP2

JP3

R252.1

R550

R330 VREFIN

FIGURE 5

NOT POPULATED

Figure 1. Power Supplies and Voltage Reference

2 DS259DB1

CDB5180

CLOCK OSCILLATOR AND BUFFER

Figure 2 illustrates the circuitry used to generatethe clock signal MCLK that drives the CS5180.The board contains a 25.6 MHz nominal oscillatoras well as a BNC connector for use with an externalclock source. The on-board oscillator is bufferedand inverted to form a complementary clock signal,MCLKB, that is used in the SYNC and RESET cir-cuits. Selection of internal clock or external clockis done by setting header HDR3 to either the OSCor BNC position. Using the on-board oscillatorwill result in an output word rate of 400.0 kHz.

RESET AND SYNC CIRCUITS

Figure 3 illustrates the circuits used for generatingthe chip RESET and SYNC signals. Two manualpushbuttons are provided for generating the RE-SET and SYNC signals, which are synchronized tothe falling edge of the master clock by means of aflip-flop before being sent to the CS5180. HeaderHDR2, not populated, is provided for connecting toexternal SYNC and RESET signals. To use the ex-ternal signals, set headers HDR6 and HDR7 to theEXT position and apply the external signals at theHDR2 thru-holes.

INPUT SIGNAL CONDITIONING

Figure 4 illustrates the circuitry used to conditionthe analog input signal. A single-ended input is fedin via the BNC connector to a pair of operationalamplifiers. The signal is buffered and also invertedto form differential signals. These signals are thenfed to two more op-amps where the voltage refer-ence is added to each of them to bring the commonmode voltage up to the range required by the con-verter. Potentiometer R41 is available to adjust theoffsets on the two op-amp outputs to be equal, sothat with zero volts in at J2, the converter reads ze-ro. The two signals are then passed through an at-tenuating resistor network before being input to theconverter. A 1.0 Volt peak-peak signal input at theBNC connector will result in nominal 0.2849 Voltpeak-peak fully differential signals being appliedbetween the AIN+ and AIN- pins of the converter.If the external signal is not single ended but is al-ready differential, it can be input through connectorJ6 where it is capacitively coupled in and offset tothe proper common mode value before being ap-plied to the converter. The settings of HDR8 andHDR9 select whether the input signal will be inputthrough the BNC connector as a single-ended sig-nal or through J6 as a differential signal. To use the

J1BNC

GND GND

49.9R36*

VCCIOR35 10

C90.1 µF

X7R

GND

14

4

2

VCC

EN

GND

HDR3

8

25.6 MHz Nominal

U1

MCLKFigures 5 and 6

GND

1

2

3GND

U3

NC7SZ04M5

VCC

4

5

C160.1 µFX7R

VCCIO

MCLKBFigure 3

R56

0

111

R57

0

EXTCLK

BNCOSC

CLKOSC

*Not Populated

Figure 2. Clock Oscillator and Buffer

DS259DB1 3

CDB5180

hea-sen If-utorhe

t-on-rialeredbleanockfthuld-o-e

DC-coupled signal from the BNC connector J2, setheaders HDR8 and HDR9 to the BNC position. Tofeed a capacitively coupled signal from J6 to theCS5180, set HDR8 and HDR9 to the XLR position.Alternatively, the differential signals can be ap-plied by feeding them into test points BAL+ andBAL-. Note that connector J6, R20, R21, C40, andC41 do not come installed on the board and must beobtained and soldered in by the user before a bal-anced signal can be applied to the board input. J6,R20, R21, C40, and C41 are not required when asingle-ended signal is being applied to connectorJ2, since the op-amps will convert and apply a bal-anced signal to the CS5180.

CS5180 CONVERTER CIRCUITS

The connections to the CS5180 chip are illustratedin Figure 5. The analog and digital supply voltagesare all decoupled with X7R ceramic capacitorsclose to the device. In addition to the 0.1 µF ceram-ic capacitors, there are 1 and 10 µF electrolytic capson the voltage reference input and output lines tominimize noise on the references. An LED is con-nected to the MFLAG signal and when on, indi-cates that data from the converter may be invaliddue to an input overload. Header plugs are provid-ed to change the MODE pin, allowing for raw 1-bit

modulator data to be output, and for placing tchip in the power-down mode. For normal opertion, header HDR15 should not be installed. To uthe CS5180 internal digital filter, the mode pishould be set high by removing header HDR16.HDR16 is installed, the internal digital filter is disabled and the direct unfiltered modulator outpwill be presented on the serial data pin SDO. Fthis condition, header HDR12 should be set to tMCLK position.

OUTPUT BUFFERS AND HEADER CONNECTIONS

Figure 6 illustrates the circuitry for sending the ouput data off-board and the associated header cnections. The CS5180 outputs data in a seformat only, along with the serial clock and thframe sync signal, FSO. These signals are buffeexternally to the CS5180 and then made availaon the 10-pin header HDR1. Header HDR12 cbe used to select between sending the serial clSCLK or the master clock, MCLK, to pin 8 oHDR1. If the evaluation board is being used withe CDBCapture+ board then the CS5180 shobe operated in Mode 1 (internal digital filter enabled), and HDR12 should be set to the SCLK psition, where SCLK is connected to HDR1. If th

GNDGND

GND

GND

GND

GND

GND

RESET

S2

R4

2 K

SNYC

S1

R13

2 K

VCCIO

VCCIO

C36.1 µFX7R

C36.1 µFX7R

R2849.9 K

R2949.9 K

C80.1 µFX7R

VCCIO

MCLKBFigure 2

4321

10111213

1/PRE1CLK1D1/CLR

2/PRE2CLK2D2/CLR

U11

MC74HC74AD

14

5

6

9

8

7

VCC

1Q

1/Q

2Q

2/Q

GND

VCCIO

SNYCFigure 5

RESETBFigure 5

SWHDR7EXT

SWHDR6EXT

2 EXT_SYNC4 EXT_RESETB

13

HDR2

Figure 3. Reset and Sync Circuits

4 DS259DB1

CDB5180

evaluation board is being used without the CDB-Capture+ board and the CS5180 is operating inMode 0 (raw modulator output), then HDR12should be set to the MCLK position, feeding themaster clock signal to connector HDR1. Nor-gatesU13 and U14 will automatically reconstruct theRTZ data from the modulator bitstream so that itcan be sampled on the rising or falling edge ofMCLK.

USING THE EVALUATION BOARD

Although the evaluation board can be connected di-rectly to a microprocessor that has a serial port andis fast enough to process up to 400K words/second,it can be more convenient to use the evaluationboard in conjunction with the Crystal CDBCap-

ture+ Board, which has been designed specificallyto interface with high speed converters and has a10-pin header that is compatible with the signals onheader HDR1 of the evalboard. Connect the appro-priate power supply voltages to the binding posts ofthe board. Use high quality linear power suppliesthat are low in noise, ripple, and line frequency(50/60 Hz) interference. If both 5 V digital and 5 Vanalog supplies are to be used, make sure thatHDR17 is removed to prevent contention betweenthe supplies. Total 5 Volt current requirements areapproximately 0.2 Amps. The load on the plus andminus 15 Volt supplies will be under 0.1 Ampereeach. The Capture Plus board is then connected toa PC and Crystal’s software is used to configure theboard and to capture data.

10 KR15

-

+

-

+

-

+

-

+

J2BNC

AGND2 K

R5

AGND AGND

-15 V

.1 µFV-4

3

2V+

8 U6

1

LM6172IM

R7

+15 VC17 .1 µF X7R

AGND

2 K

C18X7R

5

6

R6 2 K

U6

7

LM6172IM

R8

2 K

R381 K

AGND

VREF_AMPFigure 1

AGND AGND

R3910 µF

R1810 K

+

R1910 K

5

6

R9 2 K

U9

7

LM6172IM

AGND

-15 V

.1 µFV-4

3

2

LM6172IM

C19X7R

BNCHDR9

XLR

BNCHDR8

XLR

AGNDU9

1

8V+

R10

2 K

AGND AGND

+C4210 µF

R4010 K

+15 VC20 .1 µF X7R

1 K

CW R39 9.53 K VREF_AMPFigure 1

R41

R2110 K

AGND BAL-

10 µFC40 +

R161.0 K

R171.0 K

C4110 µF

R2010 K

R30100

R1301

R2301

BAL+

AGND

AGND

+

J6

2

3

1XLR_F

AIN+

AIN-

VREF_AMPFigure 1

(Not Populated)

TP14Figure 5

TP13Figure 5

*

*

*

**

* NOT POPULATED

Figure 4. Input Signal Conditioning Circuitry

DS259DB1 5

CDB5180

Connect a coaxial cable from the AIN BNC (J2) toa high quality signal source, such as the Krohn-HiteModel 4400A. Note that the performance of theCS5180 A/D converter can exceed the capability ofmany signal generators, especially with respect tonoise and line frequency interference.

COMPONENT LAYOUT

Figures 7, 8, and 9 illustrate the component place-ment and layout of the CDB5180 evaluation board.Digital and analog patch areas have been providedfor experimentation with new components. Notethat all the power supply rails and their grounds aremade available in the respective patch areas.

C25 X7R .1 µF

GND

AGND AGND

GND1 2HDR15

HDR161 2

PWDNB

MODE

R2410 K

R2310 K

R1410 K

MCLKFigure 2

RESETBFigure 3

R690

R440

R450

C35X7R.1 µF

C31X7R.1 µF

VDDD

VDDD

25 24 23 22 21 20 19

PW

DN

B

MO

DE

RE

SE

TB

DG

ND

1

VD

+1

MC

LK

MC

LKB

FSOFigure 6SDOFigure 6SDOBFigure 6SCLKFigure 6

VD+2

FSO

SDO

SDOB

SCLK

SCLKB

AGND318

17

16

15

14

13

12VDDD

C13X7R.1 µF

C32X7R.1 µF

5 6 7 8 9 10 11

VR

EF

IN

VR

EF

CA

P

AG

ND

2

VA

+2

MF

LAG

SY

NC

DG

ND

2

SYNCFigure 3

D1LED_SMT3216

R37499

+5 VA

C4410 µF

C24X7R

.1 µF

R320

+

VREFINFigure 1

C55X7R

.1 µF

AGND

AGND

C33 X7R .1 µF

C14 X7R .1 µF

C7 1 µF

VREFCAP+

C4310 µF

C23X7R

.1 µF+

AGND

AGND

C27X7R.1 µF

+5 VA

VREFOUT

AIN-

VA+1

AGND1

VREF+

VREF-

AIN+26

27

28

1

2

3

4

U8CS5180_BL

AGND

C42200PF

COG

AGND

C12200PFCOG

AIN+Figure 4

AIN-Figure 4

R520

R50

R51

0

0

R540

VREF_AMP

GND

R27 0

R31 0

R34 0

R42 0

R43 0

GND GND

GND

R470

GND

R53 0

Figure 5. CS5180 Converter Circuit

6 DS259DB1

CDB5180

2468

10

13579

GND

HDR5X2HDR1VCCIO

1 VCC

3GND

U13

2

5

4

NC7SZ02M5

GND

1VCC

3GND

U14

2

5

4

NC7SZ02M5

GND

GND

C290.1 µFX7R

VCCIO

GND

C300.1 µFX7R

VCCIO

SDOBFigure 5

SDOFigure 5

1VCC

3GND

U2

2

5

4

NC7SZ08M5

GND

GND

C100.1 µFX7R

VCCIO

SDO_OUTMCLKFigure 2

FSOFigure 5

1VCC

3GND

U4

2

5

4

NC7SZ08M5

GND

GND

C110.1 µFX7R

VCCIO

SCLKFigure 5

SCLKHDR12MCLK

Figure 6. Output Buffers and Header Connections

DS259DB1 7

CDB5180

Figure 7. Component Top Side Layout Silkscreen

8 DS259DB1

CDB5180

Figure 8. Top Side Traces and Groundplane

DS259DB1 9

CDB5180

Figure 9. Bottom Side Traces and Groundplane

10 DS259DB1

• Notes •