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CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

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Page 1: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

CEC 220 Digital Circuit DesignTiming Diagrams, MUXs, and Buffers

Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Page 2: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Lecture Outline

Mon, Oct 5 CEC 220 Digital Circuit Design

• Timing Diagrams• Multiplexers• Tri-State Buffers

Slide 2 of 20

Page 3: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Timing Diagrams

Mon, Oct 5 CEC 220 Digital Circuit Design

• Problem: Real signals do NOT change instantaneously Real hardware (i.e., gates) do not respond immediately

• Resolution: Look at the signals vs time Timing diagrams!!

Slide 3 of 20

Page 4: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Timing DiagramsEffect of Gate Delays

Mon, Oct 5 CEC 220 Digital Circuit Design

• Consider the simple circuit: Assume that all gates have

a 10 ns delay

The outputs may not be defined at the start!!

10 ns

10 ns

Slide 4 of 20

1F = AB+C

Page 5: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

0 50 100 150

Timing DiagramsHazards in Combinational Logic

Mon, Oct 5 CEC 220 Digital Circuit Design

• Glitches: The inverter has a 10 ns delay The AND gate has a 5 ns delay

A

B

C

Ideally, . In the “real world” glitches occur!!

10 ns

5 ns

Slide 5 of 20

What should C=?

Page 6: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Timing DiagramsHazards in Combinational Logic

Mon, Oct 5 CEC 220 Digital Circuit Design

A Static 1-Hazard A Static 0-Hazard

Dynamic Hazards

Slide 6 of 20

Page 7: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

MultiplexersA 2:1 Multiplexer

Mon, Oct 5 CEC 220 Digital Circuit Design

• A Multiplexer (or data selector) uses a control input(s) to select one of multiple inputs.

Z = I0 if is true, or I1 if is true

Z = I0 + I1

Z

I0

I1

=0=1

Slide 7 of 20

Page 8: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Multiplexers4:1 and 8:1 Multiplexers

Mon, Oct 5 CEC 220 Digital Circuit Design

2n inp

ut d

ata

lines

n select lines0 1 2 3Z I AB I AB I AB I AB

4:1 MUX

0

1

2

30S

1S

I0

I1

I2

I3

A B

Z

Dat

a In

puts

Control Inputs

0S1S

2S

Slide 8 of 20

Page 9: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

MultiplexersAn Example

Mon, Oct 5 CEC 220 Digital Circuit Design

• Problem: Use an 8:1 MUX to implement the following truth table.

A B C Z

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Slide 9 of 20

Page 10: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Buffers

Mon, Oct 5 CEC 220 Digital Circuit Design

• Problem: Real world gates have limited output current drive

capability (fan-out)

The OR gate may NOT be able toDrive all of the AND gates

Solution: Use a buffer

Slide 10 of 20

Page 11: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Tri-State Buffers

Mon, Oct 5 CEC 220 Digital Circuit Design

• A Tri-State or Three-State buffer Output can be low, high, or high impedance (High-Z)

B=0B=1

Slide 11 of 20

A - InputB - ControlC - Output

Page 12: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Tri-State Buffers

Mon, Oct 5 CEC 220 Digital Circuit Design

• Four kinds of Tri-State State buffers Output can be low (0), high (1), or high impedance (Z)

Slide 12 of 20

Non-Inverting Inverting Inverted Control Inverted Control & Op

Page 13: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Tri-State Buffers

Mon, Oct 5 CEC 220 Digital Circuit Design

• Can use tri-state buffers to build a MUX:

When B is low select A, orWhen B is high select C

Slide 13 of 20

How would I build a 4:1 MUX?

Page 14: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Tri-State Buffers

Mon, Oct 5 CEC 220 Digital Circuit Design

• Problem: IC’s have a limited number of pins Can use a given pin for either input or output

Slide 14 of 20

Page 15: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Examples

Mon, Oct 5 CEC 220 Digital Circuit Design

• Realize a 4:1 MUX, using an 8:1 MUX.

0S1S

2S

0S1S

Slide 15 of 20

Page 16: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Examples

Mon, Oct 5 CEC 220 Digital Circuit Design

• Make an 8:1 MUX, using four 2:1 & one 4:1 MUX

Slide 16 of 20

Page 17: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Examples

Mon, Oct 5 CEC 220 Digital Circuit Design

• Use an 8:1 MUX to implement the function

f ABC ABC ABC ABC A B C f

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

A B C f

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Slide 17 of 20

Page 18: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Examples

Mon, Oct 5 CEC 220 Digital Circuit Design

• Use an 4:1 MUX to implement the function

A B C f

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

f ABC ABC ABC ABC

C10C

A B

Slide 18 of 20

0f AB AB BC C C CAB A

f

Page 19: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Examples

Mon, Oct 5 CEC 220 Digital Circuit Design

• Use an 2:1 MUX to implement the function

A B C f

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

f ABC ABC ABC ABC

A BC BC BC A BC

A BC B A BC

A C B A BC A BC 0 1

00 1 0

01 0 0

11 1 1

10 1 0

f BC AC

Slide 19 of 20

A

C

B

B

C

f

Page 20: CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

Next Lecture

Mon, Oct 5 CEC 220 Digital Circuit Design

• Decoders and Encoders• Read-Only Memories (ROMs)

Slide 20 of 20