硬體描述語言 verilog hdlaccess.ee.ntu.edu.tw/course/dsd_99second/2011... · rt-level design...
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ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
數位系統設計
901-43500
臺大電機系/電子所
吳安宇教授
代課:趙之昊<[email protected]>
Slide modified from Prof. Wu’s DSD Lecture Note in 2010 Spring
2011/2/23
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
http://access.ee.ntu.edu.tw/
=> course => Digital System Design
課程網頁
Graduate Institute of Electronics Engineering, NTU
pp. 3 An-Yeu Wu
Objective
Digital system design plays an important role
in implementing digital functions in modern
system-on-chip (SOC) design.
In this course, we will focus on developing the
design skills for undergraduate students so
that they can be familiar with state-of-the-art
digital front-end design skills and flow.
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 4 An-Yeu Wu
Course Content (I)
Firstly, we will introduce the Hardware Description Language
(HDL) and general front-end cell-based design flow. The
chosen HDL is Verilog. We will formally cover:
HDL language syntax (basics)
Semantics and coding guideline (how to write elegant codes)
Coding for synthesis (how to write synthesizable codes;
hardware design concept)
Reuse manual methodology (RMM) – How to create “reusable”
codes for IP (Intellectual property) reuse
Front-end cell-based synthesis flow (how to use to state-of-the-
art synthesis tools)
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 5 An-Yeu Wu
Course Content (II)
Secondly, we will ask students to design and implement an
advanced MIPS CPU. It is based on the knowledge of
“Computer Architecture.” The assignment covers:
RT-level design of major blocks such as arithmetic logic unit (ALU),
control unit, register file, cache unit, etc.
HDL coding, simulation, synthesis
Integration of whole design and enabling the execution of MIPS
R32 binary codes
Instruction set architecture (ISA) development and extension
Enhanced RISC-based CPU design with Pipelining, Forwarding,
and Hazard Control
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
Homework
Five homework
1. Practice of Structural Verilog Coding
2. Practice of Behavior-Level Verilog Coding
3. Design of a Single Cycle MIPS Processor
4. Design of a Cache Unit
5. Topic Selected from Cell-Based IC Design
Contest
pp. 6 An-Yeu Wu W1: DSD Course Overview 2011.2.23
Individual
Homework
Team
Homework
Graduate Institute of Electronics Engineering, NTU
Final Project
Design of a Pipelined MIPS Processor with
Cache Unit:
Baseline
Implement specified instruction set (30~40 instructions)
Combine the components built in hw1~hw4
Solve data/control/branch hazards
Execute given binary codes and output correct results
Extension
Implement MUL/DIV/MAC instructions
Pipeline ALU and handle hazards from ALU pipelining
Other selected topics
pp. 7 An-Yeu Wu W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 8 An-Yeu Wu
Course Schedule (1)
週數 日期 課程規劃 講師 課程內容 作業宣佈 作業繳交
W1 2/23 Introduction 趙之昊 Course Overview,
Digital System Design Introduction
W2 3/2 HDL1 陳郁豪 Fundamentals of
Hardware Description Language (Ch1 - 3) HW1
W3 3/9 HDL2 陳郁豪 Logic Design at Register Transfer Level (Ch 4,
7)
W4 3/16 HDL3 蘇冠羽 Logic Design with Behavior Coding,
Design Verification Tool (Ch 8 - 10) HW2 HW1
W5 3/23 HDL4 蘇冠羽 Testbench Writing,
Synthesizable Coding of Verilog
W6 3/30 HDL5 馮紹惟 Complexity Management,
Improving Timing/Area/Power HW3 HW2
W7 4/6 Break
W8 4/13 Synthesis1 張恩瑞 Synthesis Overview and Tool Usage
W9 4/20 Midterm
Exam
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 8
Graduate Institute of Electronics Engineering, NTU
pp. 9 An-Yeu Wu
Course Schedule (2) 週數 日期 課程規劃 講師 課程內容 作業宣佈 作業繳交
W10 4/27 Synthesis2 張恩瑞 Advanced Topics on Synthesis HW4 HW3
W11 5/4 Design Guideline 鍾明翰 Design Guideline: From Spec to Circuit
W12 5/11 Design Issues for
MIPS Processor(1) 陳坤志 MIPS Overview, Memory Hierarchy
Project &
HW5 HW4
W13 5/18 Design Issues for
MIPS Processor (2) 陳坤志 Pipelined Architecture of MIPS
W14 5/25 Speech Invitation Speaker (To-be-defined) HW5
W15 6/1 Break
W16 6/8 Project Check
Point
吳安宇 教授
Oral presentation
W17 6/15 Break
W18 6/22 Project
Presentation
吳安宇 教授
Oral presentation Project
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 9
Graduate Institute of Electronics Engineering, NTU
pp. 10 An-Yeu Wu
Textbooks (Main Verilog coding textbook)
“Verilog HDL: Digital design and modeling,”
Joseph Cavanagh, CRC Press, 2007.
(Reference CPU textbook)
“Computer organization and design: The
hardware/software interface,”
David A. Patterson and John L. Hennessy,
2008, 4th Edition.
(Reference Verilog coding textbook )
“Digital system designs and practices:
Using Verilog HDL and FPGAs,"
Ming-Bo Lin, Wiley, 2008.
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 11 An-Yeu Wu
Course Grading
Homework: 30%
Midterm Exam: 30%
Final Project: 35%
Impression: 5%
(Attendance & Attitude).
Previous results:
W1: DSD Course Overview 2011.2.23
972
Original
972
Final
982
Original
982
Final
Mean 81.15 88.31 85.30 88.26
Stdv. 13.96 9.75 8.39 7.30
0
2
4
6
8
10
12
70-74 75-79 80-84 85-89 90-94 95-99
0
2
4
6
8
10
12
70-74 75-79 80-84 85-89 90-94 95-99
Graduate Institute of Electronics Engineering, NTU
pp. 12 An-Yeu Wu
Suggested Background
Programming Language : Required
Logic Design : Required
Computer Organization and Design: Suggested
VLSI Design and VLSI/EDA tools: Optional
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 13 An-Yeu Wu
Limitation
Limit
39 students, 13 teams
3 students as a team for hw5 and project
Priority:
1. EE3
2. EE4
3. EE2
4. EE1
5. Other departments
6. Graduate students.
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
Major Related Courses
Computer Architecture http://access.ee.ntu.edu.tw/course/CA_992/
Cover domain knowledge of computer organization and the relationship between hardware and software
Textbook: David A. Patterson, and John L. Hennessy, “Computer Organization and Design – The Hardware/Software Interface”, 4th Edition, Morgan Kaufman Publishers, Inc., 2009.
Digital Circuit Design Lab Project oriented practice of design and implementation of real
systems
FPGA-based design flow
Computer-aided VLSI System Design (CVSD) – graduate course of NTUGIEE Cover more topics and back-end flow of cell-based IC design
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 14
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
High-performance Digital
Design in SoC Era
Graduate Institute of Electronics Engineering, NTU
pp. 16 An-Yeu Wu
IC Design and Implementation
Idea
Design
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 17 An-Yeu Wu
Digital IC Design Flow
1. Concept/Application
2. Function/Spec. definition
3. Algorithm exploration
4. Architecture design
1. Divide-and-conquer
2. Sub-module design
3. Design verification
5. System prototyping (need training!!)
1. RTL design
2. Verilog Coding/Schematic Design
3. Cell-based IC design flow / FPGA design flow
4-bit 2's
Complement
Add/Sub
operand_a
mode
operand_b result
4
4 4
FA0FA1FA2FA3
a3 b3 a2 b2 a1 b1 a0 b0
result1 result0result2result3
carry
out
mode
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 18 An-Yeu Wu
System Specification
Partition
IO Spec.
IO Timing Spec.
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 19 An-Yeu Wu
Algorithm Mapping and Architecture Design
RTL Level
Description
of hardware
System/Algorithm Level
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 20 An-Yeu Wu
Cell-Based IC Design Flow
HDL
Logic Synthesis
Floorplanning
Placement
Routing
Tape-out
Circuit Extraction
Pre-Layout
Simulation
Post-Layout
Simulation
Structural
Physical
Functional Design Capture
Desig
n I
tera
tion
W1: DSD Course Overview 2011.2.23
Front
-End
Back
-End
Graduate Institute of Electronics Engineering, NTU
Brief Overview of Digital System
Design
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 21
Graduate Institute of Electronics Engineering, NTU
The First Computer
The Babbage Difference Engine (1832)
25,000 parts
Cost: 17,470 Pounds
in Year 1832
Mechanical, using gears, decimal notation
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 22
Graduate Institute of Electronics Engineering, NTU
ENIAC -The first electronic computer (1946)
Use Vacuum Tubes as Switching Components (Binary)
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 23
Graduate Institute of Electronics Engineering, NTU
Now: Computer Everywhere
pp. 24 An-Yeu Wu W1: DSD Course Overview 2011.2.23
Advances of VLSI Technology Brings Computer Everywhere
Graduate Institute of Electronics Engineering, NTU
pp. 25 An-Yeu Wu
Technologies for building processors and
memories
Vacuum tube
An electronic component, predecessor of the
transistor, that consists of a hollow glass tube about
5 to 10 cm long from which as much air has been
removed as possible and which uses an electron
beam to transfer data
Transistor
An ON/OFF switch controlled by an electric signal
Very large scale integrated (VLSI) circuit
A device containing hundreds of thousands to
millions of transistors
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 26 An-Yeu Wu
Vacuum Tube
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 27 An-Yeu Wu
The Transistor Revolution
First transistor
Bell Labs, 1948
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 28 An-Yeu Wu
Discrete Transistors
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 29 An-Yeu Wu
The MOS Transistor
Polysilicon Aluminum/Cu
Channel length: The distance between Source and Drain 0.18um/0.13um: this year 90nm: next year
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 30 An-Yeu Wu
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 31 An-Yeu Wu
Gate and Circuit Level Design
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
Mapping of Layout to IC Layers
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 32
Graduate Institute of Electronics Engineering, NTU
Layout of an CMOS Inverter
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 33
Graduate Institute of Electronics Engineering, NTU
pp. 34 An-Yeu Wu
Physical Design
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
Physical Layout of your design
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 35
Graduate Institute of Electronics Engineering, NTU
pp. 36 An-Yeu Wu
The “Timing Closure” Problem
Courtesy Synopsys
Iterative Removal of Timing Violations (white lines)
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 37 An-Yeu Wu
The chip manufacturing process
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 38 An-Yeu Wu
Humorous
Analogy between
Chip Fabricating
Process and
Pizza Making
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
Moore’s Law In 1965, Gordon Moore noted that the number of transistors on
a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will
double its effectiveness every 18~24 months
pp. 39 An-Yeu Wu W1: DSD Course Overview 2011.2.23
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Electronics, April 19, 1965.
Graduate Institute of Electronics Engineering, NTU
pp. 40 An-Yeu Wu
Moore’s Law: Driving Technology Advances
Logic capacity doubles per IC at regular intervals (1965).
Logic capacity doubles per IC every 18 months (1975).
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 41 An-Yeu Wu
Technologies for building processors and
memories
Relative performance per unit cost of technologies used in computers over time
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
Engineering Productivity Gap
Engineering
productivity has not
been keeping up with
silicon gate capacity for
several years.
Companies have been
using larger design
teams, making
engineers work longer
hours, etc., but clearly
the limit is being
reached.
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 42
Graduate Institute of Electronics Engineering, NTU
Why must HDL tools & IP Reuse?
Design productivity crisis:
Divergence of potential design complexity
and designer productivity
W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 43
Graduate Institute of Electronics Engineering, NTU
pp. 44 An-Yeu Wu
Design Abstraction Levels
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 45 An-Yeu Wu
HDL and Moore’s Law
HDL – Hardware Description Language
Why use an HDL ?
Hardware is becoming very difficult (and too big!)
to design directly
HDL is easier and cheaper to explore different
design options
Reduce time and cost to verify your digital designs
in VLSI implementations
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 46 An-Yeu Wu
Verilog HDL
Feature
HDL has high-level programming language
constructs and constructs to describe the
connectivity of your circuit.
Ability to mix different levels of abstraction freely
One language for all aspects of design, test, and
verification
Functionality as well as timing
Concurrently simulate behaviors of multiple
hardware blocks in simulator
Support timing simulation for your design
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 47 An-Yeu Wu
Level of Abstraction for Design and
Verification
Transistor Level
Gate Level
Register Transfer Level
Architecture
Algorithm
System
concept
Increasing
behavioral
abstraction
Increasing
detailed
realization &
complexity
W1: DSD Course Overview 2009.2.18 W1: DSD Course Overview 2011.2.23 An-Yeu Wu pp. 47
Graduate Institute of Electronics Engineering, NTU
pp. 48 An-Yeu Wu
Verilog HDL in Different Level
Behavioral
level of
abstraction
Design Model Domain
Abstract Physical Structural
System
Algorithm
RTL
Gate
Switch
Architecture
Design
Structural
Design
Logic
Design
Layout
Design
Verification
Verification
Verification
Architecture
Synthesis
RTL level
Synthesis
Logic level
Synthesis
W1: DSD Course Overview 2011.2.23
Graduate Institute of Electronics Engineering, NTU
pp. 49 An-Yeu Wu
Cell-based IC Design Flow
Design Specification
Design Partition
Design Entry-Verilog
Behavioral Modeling
Simulation/Functional
Verification
Design Integration &
Verification
Pre-Synthesis
Sign-Off
Synthesize and Map
Gate-Level Netlist
Post-Synthesis
Design Validation
Post-Synthesis
Timing Verification
Test Generation &
Fault Simulation
Cell Placement, Scan
Chain & Clock Tree
Insertion, Cell Routing
Verify Physical &
Electrical Design Rules
Extract Parasitics
Post-Layout
Timing Verification
Production-Ready
Masks Front-End Designs
Design Sign-Off
Back-End
W1: DSD Course Overview 2011.2.23