Ceng 450 Project

Pinout of Processor

Interrupt is optional

Processor

in_port[7:0]

out_port[7:0]

clock

rst

interrupt

Instruction Format

Three types of instructionsA-Format

e.g. arithmetic instructions

B-Formate.g. branch instructions

L-Formate.g. load and store instructions

A-Format Instructions

Arithmetic Instructions:

Op-Code

7 4

ra

3 2

rb

1 0

e.g.:

ADD R[2], R[1]

0100 10 01

7 4 3 2 1 0

B-Format Instructions

Branch Instructions:

Op-Code

7 4

brx

3 2

rb

1 0

e.g.:

Br R[3]

1001 00 11

7 4 3 2 1 0

Subroutine

…

…

br.sub

…

…

return

subroutine:

Subroutine

Link Register (LR): a dedicated register for subroutine call&return br.sub: PC+1 is loaded into LR

…

…

br.sub

…

…

return

subroutine:

1CLR:0X1B:

1BPC:PC+1

0X1C:

Subroutine

LR: a dedicated register for br.sub instructions br.sub: PC+1 is loaded into LR return: PC is loaded with LR

…

…

br.sub

…

…

return

subroutine:

1CLR:0X1B:

9BPC:

0X9B:

0X1C:

Subroutine

LR: a dedicated register for br.sub instructions br.sub: PC+1 is loaded into LR return: PC is loaded with LR

…

…

br.sub

…

…

return

subroutine:

1CLR:0X1B:

1CPC:

0X9B:

0X1C:

L-Format

Load/Store Instructions:

Op-Code

7 4

ra

3 2 1 0

e.g.:

load R[2], 0xA2

0001 10 00

7 4 3 2 1 0

ea/imm

First address:

Second address:

A2

Project

A processor that executes every program written in the instruction set

Processor Architecture

1)Datapath Includes components, alu, register file, memory, …

2)Controller Controls flow of instruction and data in datapath

Datapath

Controller

Instruction Memory

Mem

ory

We need a container to hold instructions

Register File

Mem

ory

Reg File

A place for R[0]~R[3]

Alu

ALU

Mem

ory

Reg File

A unit for arithmetic calculations

Data Memory

ALU

Mem

ory

Reg File

Mem

ory

A unit that holds data

Pipeline Architecture

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

To break critical path

5-Stages Datapath

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Up to now, design of main components

5-Stages Datapath

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Up to now, design of main components

Complete the datapath for every instruction gradually

5-Stages Datapath

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Up to now, design of main components

Complete the datapath for every instruction gradually

e.g. ADD instruction

PC

A component that holds address of Inst. Memory (PC)

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

Fetch

Mem

ory

PC

Address Instruction

0

IF/ID RegisterO

p-C

od

e

7

4

ra 32

1rb

ADD

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

Datapath

Decode

Decode

Reg File

0

IF/ID Register

Op

-Co

de

7

4

ra 32

1rb

rd_index1

rd_index22

2

ID/EX

rd_data1

rd_data2

RD

1R

D2

8

8

ADD

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

Datapath

Execution Stage

ALU

ID/EX

RD

1R

D2

EX/MEM

AR

op1

op2

Alu

Result

mode

ADD

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

Memory Access

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

AR

Write Back

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

AR

Write Back

Write

BackID

/EX

MEM/W

BA

R

Reg File

rd_index1

rd_index2

rd_date1

rd_data2

Write Data

Write BackWrite

BackID

/EX

MEM/W

BA

R

Reg File

Register No.1

Register No.2

Data Register 1

Data Register 2

Write Data

Which register

ADD R[2], R[1]

Revising Our Design

Mem

ory

Addre

ss

Address Instruction

0

IF/ID RegisterO

p-C

od

e

7

4

ra 32

1rb

Write Back

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

AR

ra ra

Data

Write Back

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

AR

ra ra ra

Data

Write Back

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

AR

ra ra ra

Data

ra

Write Back

MemoryAccess

Write

Back

InstructionFetch

Decode Execute

ALU

Mem

ory

Reg File

Mem

ory

IF/ID

ID/EX

MEM/W

B

EX/M

EM

Addre

ss

AR

ra ra ra

Register No.

Data

ra

Other Instructions

We should repeat similar steps for other instructions

Controller

0

Op

-Co

de

7

4

ra 321rb

rd_index1

rd_index22

2

rd_date1

rd_data2

DR

1D

R2

Controller

AL

U M

od

e

Register File

Me

m O

pr

WB

Op

r

Execute

ALU

ID/EX

DR

2

EX/MEM

AR

op1

op1

Alu

Result

AL

U M

od

eM

em

Op

rW

B O

pr

Me

m O

pr

WB

Op

r

DR

1

Mem

Data

Memory Access

MemoryAccess

Mem

ory

EX/MEM MEM/WB

Me

m O

pr

WB

Op

r

WB

Op

r

ADD R[2], R[1]Mem Opr:Write_En = 0

Me

m A

dr

Wr_En

Write Back

MemoryAccess

Write

Back

Decode Execute

ALU

Reg File

Mem

ory

ID/EX

EX/M

EM

AR

ra ra ra

Register No.

ra

WB

Op

r

Register Value

wr_en

Controller

Design Controller Base on Control Signals in Data-Path

Control Signals To DataPath Components

Flags

Instruction from IR

State Machine

rst reset=1

decode

Op=add

Op=load

…

Deactivate control signals

wr_enable =1

State Machine Implementationparameter [3:0]

RESET=0,DECODE=1;

always @(negedge clk)if(rst)

beginstate = RESET;//deactivate all control signalsend

elsebegincase(state)

RESET: beginstate=DECODE;

endDECODE: begin

if(opcode=ADD)…

enddefault: state=RESET;

endcaseend

rst reset=1

decode

Op=add

Op=load

Implementation Strategy

First Design Datapath

Design Controller base on Data-Path

Connect Controller and Data-Path

Designing Datapath

Necessary Components Program Counter Instruction/Data Memory ALU Register File ….

Datapath Hierarchy

Data Path

ALU Register FilePC Memory Mux

Start your design from Bottom Modules

Simulate each Component

Post-Route Simulation

ALU

Add

01110111

01000110

111101101

Is it Correct?

Test Vectors

Wiring CPU (Top Module)

Controller

Reg. File

MemoryPC

ALU

Data Signals

Control Signals

Data Path

Debugging

Hazards Because of PipelineData HazardControl Hazard

Simulating Complete CPUImplementation (Pin Assignment)