centre for development of advanced computing software defined radio & cognitive radio:...

Centre for Development of Advanced ComputingCentre for Development of Advanced Computing

Software Defined Radio & Cognitive

Radio: Implementation

Initiatives

KRISHNA KUMAR S.KRISHNA KUMAR S.Centre for Development of Advanced Computing

[email protected]


25 Feb 2012 sdr & cr: implementaion initiatives 2 of 60

C-DAC

A National Centre of Excellence and premier R & D institution

under DIT, MCIT, Govt. of India

involved in the design, development and deployment of Electronics & IT- based

solutions for human advancement



10 Locations

14 Centres 3000

members



TETRA

VoIP

Digital Audio

Software Defined Radio Networking

TETRA-WiMax

MANET

CR

CNM

NG WF SDR

AM/FM Radios & Television

Alpha Numeric Information Displays

CCTV Cameras

Monitors

Direct Reception System

Multifunction mono/stereo Audio Consoles

CD Players

Equalizers

Monitoring Amplifiers

Digital Audio Work Stations

1990 2000 2010 2015

Broadcast & Communications @ C-DAC



2004

2006

2007

2008

2009

2010/11

Study Repor

t

SDR Demos- 2 SCA WFS

C-DAC SDR

proposal

1st SDR Project

SDR PoC

DIT DIT DIT DIT2012

2012

2013

SDR Manpack

HandheldSDR-NC

C-DAC SDR-Demo DIT C-DACNAVY

CR

C-DAC SDR programme road map



recent/current projects in SDR/CR

SDR for Naval Communication (DRDO)

SDR Manpack (DIT)

SDR Handheld (Core funding)

Cognitive Radio Networks (DIT)

jointly with IISc.

Next Generation Waveforms for SDR

Related projects

Mobile Adhoc NETworks (MANET)

Autonomic Network Management Systems (ANMS)



Demonstrated re-configurablity with two SCA compliant waveforms

o TETRA UHF band & Militaryo Legacy FM Radio (VHF band) Clear Mode

the PoC SDR lab model



SDR manpack: product perspective



agenda

introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions



Software Defined Radio

a radio in which some or all of the radio’soperating functions are implemented

through modifiable software or firmware



SDR Platform

Consists ofHardware,Firmware, Operating system Middleware

Takes different personalities, defined by the waveform that is loaded



SDR platform architecture

LNA

IMGFILTER

MXR IFFILTER

AMP

AMP

RFFILTER

MXR

IFFILTER

DUPLEXEROR

T/R SW

ADC

DAC

FPGA

IF to 250MHz

12-16 BITS60-125MSPS

12-16 BITS200-1000MSPS

DSP+

GPP

MEM MEM

MMI

LO

LO

DDSSYNTH

LO

LO

FREQ STD

CLK

CLK

CLKCLK

CLK

CLK

CLK

CLK

ADC

CLK

12 BIT / 250MSPS

MXR IFFILTER



RF transceiver



Hopping Synthesizer



Harmonic Filter Bank



Baseband Boards



agenda




Waveform: Definition

From http://www.wirelessinnovation.org/Introduction_to_SDR

The set of transformations applied to information to be transmitted and the corresponding set of transformations to convert received signals back to their information content.Representation of a signal in spaceThe representation of transmitted RF signal plus optional additional radio functions up to and including all network layers.



Waveform

Can be visualized at different levels

ArchitectureConceptual entityDefines and abstracts the waveform functionsAlmost independent of the platform specifics

ImplementationPhysical realization of architecture Closely related to platform



Waveform Architecture design

What it is?

What it is not?



Technical Specification

s

Candidate Architecture

Architecture design process

SIMULATION

User behavioural

patterns

operational needs

Radio Standards

Final Architectur

e



Waveform Implementation

Physical realization of architecture Closely related to platformImplementer should knowOverall platform architectureAvailability of Computing elements

• GPP, DSP, FPGAOther configurable resources

• clocks, vca, vco, tunable filters etc.



Task Partitioning among CEs

GPP

Signaling and controlHigher layer and MAC functions

PHY Bit level processingSymbol rate processingSoft real-time numerically intensive tasks – e.g. channel estimation

Ideally all hard real time PHY functionsTasks best implemented using parallel architectureSymbol rate processing for wideband systems

DSP FPGA

RULES OF THUMB



What devices in a given SDR?

Device architectures are being upgraded constantlyNew FPGAs realize DSP functions using specific architectures New DSPs use hardware accelerators to implement hard real time tasksGPP performance too scales up Blurred boundaries! Vanishing boundaries?Platform designer priorities do matter



Portability & Re-configurability

Probably the most important features of SDRWaveform should be portable across platforms [a statement to be qualified]Waveform should be able to configure and control platform resourcesEnsured by proper design and implementation of Waveform and PlatformMay result in sub-optimal implementationbut that’s okay! in most cases



Application Program Interfaces

Key enabler in ensuring portability & re-configurability

Abstracts low level functions

Platform provider to facilitate platform abstraction through APIs

Waveform implementer to use APIs to access platform features



GPP & DSP APIs

GPP API calls are typically POSIX calls

DSP API calls are C-function callsAPI implemented as a libraryAPI to be used while building DSP image



RF APIs

To abstract Radio functionsTuning LOConfigure Tx. DACConfigure AGC Etc.

API calls are pre-defined messages

Processed and executed by a dedicated controller



FPGA: Wrapper

Equivalent of API for FPGA Wrapper defines the platform logic Waveform logic defines the (part of) PHY signal processing Waveform logic to be integrated with wrapper



Waveform Logic

Waveform Logic

EMIF GlueEMIF Glue

SPI GlueSPI Glue

McBSP Glue

McBSP Glue

uPP GlueuPP Glue

ADC FIFOADC FIFO

DAC FIFODAC FIFO

UARTGlueUARTGlue

GPIO(Push

Buttons, LEDs, DIP Switches,

GPIO Headers)

GPIO(Push

Buttons, LEDs, DIP Switches,

GPIO Headers)

DSPDSP

ADCADC

DACDAC

RF ControlRF Control

UART PortUART Port

FPGA IO Ring

TOP module

SPI Signals

EMIF

McBSP

uPP

14 bit

16 bit

Interrupt 1Interrupt 2

FPGA: Architecture



FPGA: model based design

To design waveform signal processing

Can be done in a graphical way

Designer need not no low-level architecture of the device

Can be used jointly with Matlab/Simulink or similar simulation environments



FPGA: model based design tools

Xilinx - System GeneratorAltera - DSP BuilderActel - SynplifyLattice - ispLever DSP

Agilent system view – VHDL code generation



FPGA: integration with wrapper

Combine the HDL source level

Combine the wrapper source with waveform netlist Similar to adding a library

Combine at bitmap level Wrapper logic implemented in advanceWaveform logic added using partial reconfiguration



agenda




from SDR to CR

A natural evolution

CR, by nature, has to be an SDRbut,

an SDR with certain specific fetures.



CR additional requirements

A truly wideband radio front end

Support for White/Gray space detectionSpectrum sensing - hardware & softwareGeo-location and Database

• IEEE 802.22

Dynamic Spectrum ManagementChannel & Bandwidth allocationRate adaptation & Tx power control



from SDR to CR: concerns

Algorithm complexities – of course

A truly wideband radio front endTx side RF Power ampsRx side – wide band sensing

AD/DA conversion bottle-necks

Noise, sensitivity, interference protection, SFDR



agenda

introduction SDR architecture SDR waveforms From SDR to CR Spectrum Sensing Engine – design & implementation application scenarios conclusions



Primary Signal Details

Primary: Terrestrial analog TV txn in India

System: CCIR system B,G PAL

Bands: • Band II VHF: 174 to 225 MHz• Band IV UHF: 470 to 582 MHz

Channel BW: 8 MHz



Requirements

Incumbent Detection Threshold: -94 dBm (measured at peak of sync)

Channel Detection Time: <=2 sec per channel

Detection Performance: Probability of Detection >=90% at False

Alarm rate of <= 10%

Guided by IEEE 802.22 WRAN WG interim recommendations



Platform - Lyrtech SFF SDR



From SS Algorithm to SS Engine (from “recipe” to “dish”)

Study of algorithmStudy of hardware architectureDesigning software architectureOptimal partitioning of algorithm Model based design / C-program developmentFixed point considerations

dynamic range, bit growth, over/under-run, truncation error

Defining and realizing interfacesDebugging, testing and optimization



Detection Scheme

Pre-processing/Feature extraction stage Extracts the spectrum around the picture carrier

Energy Detection stage Computes the energy around the pictures carrier



Pre-Processing

Decimating filter stages

5 5 5 2

Digital IF BW: 8MHz125 Msps

14 bits

to sensing algorithm BW: 100kHz

500 Ksps32 bits

DDS @ 30MHz



Implementation

Implemented in the FPGA part (Virtex 4)Design using Simulink / System generator

Model based design approach

Fixed point implementationWord-length selection

bit growth truncation error resource utilization



Energy Detection

N samples x B buffers

Gives the adavntage of averaging

Reduces the FFT implementation complexity



Implementation

Implemented in the DSP (TMS320C64X)

Code developed in C language

Debugged using Code Composer Studio & XDS560 ICE

A fixed point implementation

Word-lengths selection



User Interface


Lab Setup



Test Settings

Picture carrier: 67.25MHz

Channel Bandwidth: 8MHz

Video pattern: White

Sensing duration: 20.4 ms

Sampling rate: 125Msps

Ensemble size: 1e5

SNR values: -30dB, -27dB, -24dB



PAPR for ATV

Courtesy: Martyn J. Horspool, Analog-to-digital Upgradeable Transmitters For the Worldwide Market, Harris Corporation



Results



Results

System meets the false alarm/miss detection performance at -27 dB SNR

Highly encouraging result

Enough margin to accommodate large scale fading

Caveat: This is only a lab measurement



agenda




application areas

MilitaryPMR (public safety, police, paramilitary)Disaster managementCommercial Cellular (Base Stations)Rural broadband accessIEEE 802.22 system adaptaion

Tele-Medicine



acknowledgements

Simon Zachariah

Beena K. T.S. Sagar

Chandra R. Murthy

Shine K. P.Satheesh Kumar S.


…thank you

Questions ??

centre for development of advanced computing software defined radio & cognitive radio:...

Documents

sdr cr

sdrcr sdr

sdr project sdr poc

implementaion initiatives

poc sdr lab model slide

study report sdr demos

firmware slide

sca wfs cdac sdr proposal