www.cei.upm.es

ce

i@u

pm

.es

Universidad Politécnica de Madrid

Centro de

Electrónica Industrial

Power Electronics Modeling Activities

2011 2

Sasp

www.cei.upm.es

2011 3

PTModel

2011 4

Powercad

www.cei.upm.es

2011 5

PowerSim

Bypass

Line

Battery

PFC Boost

Average current control

HBCC

Voltage mode

2011 6

Tramst

www.cei.upm.es

2011 7

Demomag

2011 8

Scope

Automovile

Aeronautics

Aerospace

Data Servers

www.cei.upm.es

2011 9

From the COMPONENT

to the SYSTEM

Virtual Prorotyping

2011 10

Component Level

www.cei.upm.es

2011 11

PExprt Model

Over-Voltage at the Switch because

of the leakage Inductance

Converter Losses: 1.7 W

Saturation & Hysteresis

Virtual Prototyping

2011 12

Virtual Prototyping

www.cei.upm.es

2011 13

But for SYSTEM INTEGRATION,

you need top-down approach

Virtual Prototyping

2011 14

System level

28VDC

12VDC

Intermediate

bus

EMI Filter

Protections

28VDC

28VDC_REG Parallel DC/DC

converters

Multi-Output

Converter

15VDC 5VDC

DC/DC

converter

DC/DC

converter

Distributed power system d

c/d

c c

on

ve

rters

d

c/d

c c

on

ve

rte

rs

www.cei.upm.es

2011 15

Emergency

Emergency

Normal

28VDC

12VDC

Intermediate

bus

EMI Filter

Protections

28VDC

28VDC_REG Parallel DC/DC

converters

Multi-Output

Converter

15VDC 5VDC

DC/DC

converter

DC/DC

converter

System level

Load

Load

Load

18,5V

36V

24V

32V

Power budget

2011 16

28VDC 12VDC

Intermediate

bus

EMI Filter

Protections

28VDC

28VDC_REG Parallel DC/DC

converters

Multi-Output

Converter

15VDC 5VDC

DC/DC

converter

DC/DC

converter

System level

Dynamic analysis

0s 100us 200us 300us 400us 500us

0V

2.0V

4.0V

6.0V

stability?

www.cei.upm.es

2011 17

28VDC

12VDC

Intermediate

bus

EMI Filter

Protections

28VDC

28VDC_REG Parallel DC/DC

converters

Multi-Output

Converter

15VDC 5VDC

DC/DC

converter

DC/DC

converter

System level

Analysis of protections

SSPC

protection?

Inrush current

2011 18

28VDC

12VDC

Intermediate

bus

EMI Filter

Protections

28VDC

28VDC_REG Parallel DC/DC

converters

Multi-Output

Converter

15VDC 5VDC

DC/DC

converter

DC/DC

converter

System level

Large signal stability analysis

SSPC

Input current

-1

0

1

2

3

4

5

6

7

8

9

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01 Large signal stability?

www.cei.upm.es

2011 19

28VDC

12VDC

Intermediate

bus

EMI Filter

Protections

28VDC

28V_REG Parallel DC/DC

converters

Multi-Output

Converter

15VDC 5VDC

DC/DC

converter

DC/DC

converter

Cross regulation

Coupling?

System level

2011 20

28VDC

12VDC

Intermediate

bus

EMI Filter

Protections

28VDC

28V_REG Parallel DC/DC

converters

Multi-Output

Converter

15VDC 5VDC

DC/DC

converter

DC/DC

converter

System level

Paralleling converters

Load sharing?

Stable?

www.cei.upm.es

2011 21

System level

Share

Vinp

Vom

Vop

Vinm

DC/DC

28V/5V

(parallel option)

Share

Vinp

Vom

Vop

Vinm

DC/DC

28V/5V

(parallel option)

A

A

A

R5VP

Imbalance

AM1

AM2

AM3

Vinp

Vom

Vop

Vinm

DC/DC

270V/28V

+

V V28V

Share

Vinp

Vom

Vop

Vinm

DC/DC

28V/5V

(parallel option)

Vinn

Vinp

BatterySubsystem

+

V Vbat

STEP1

A

AM4

A

AM5

Vinp

Vom

Vop

Vinm

DC/DC

28V/12V

MonosalidaRegUnidireccionalConLimitadorRendVariable

Vinp

Vom

Vop

Vinm

270V/48V

DC/DC

MonosalidaRegUnidireccionalResistSalidaVariableRendVariable1

Vinp

Vom

Vop

Vinm

DC/DC

270V/28V

MonosalidaRegUnidireccionalResistSalidaVariableRendVariable2

E270V

R48V R12V

TRAPEZ1 TRAPEZ2

V2on

V2op

Vinp

Vom

Vop

Vinm

DC/DC

28VIn

12Vout no reg

5Vout reg

(without Io limiter)

(with Io limiter)

MultisalidaUnidireccional

R12VM

R5VM

TRAPEZ4

TRAPEZ5

12V carga regulada

12V carga no regulada

5V carga regulada

5V carga regulada de

alta potencia

Parallel converters

Main bus

270V

Secondary bus 24V 48V no regulated

Battery

DC/DC ?

Library

2011 22

Protections

dc/dc converters

Filters

Drivers

Non-linear loads

Validation

SABER sketch

www.cei.upm.es

2011 23

-0,31%

-1,20%

1,15%

0,00%

-2,00%

-1,50%

-1,00%

-0,50%

0,00%

0,50%

1,00%

1,50%

2,00%

20 25,5 28 32

Error at the input current

Input voltage

Input current

2

2,5

3

3,5

4

4,5

20 25 30

Maximum error

1.2%

Validation

Power Consumptions I

Input voltage

measurements

simulation

2011 24

Validation

Power Consumptions II

-0,40%

-0,04%

1,05%

-1,26% -2,00%

-1,50%

-1,00%

-0,50%

0,00%

0,50%

1,00%

1,50%

2,00%

20 25,5 28 32

Input voltage

Error at the input current

Maximum error

1.26%

76

77

78

79

80

81

82

83

84

85

20 22 24 26 28 30 32

Measurements

Simulation

Input power

Input voltage

www.cei.upm.es

2011 25

inrush current (32V)

-2

0

2

4

6

8

10

12

14

0,04 0,05 0,06 0,07 0,08

iin_meas

iin_sim

11.39 A

10.58 A

Vg = 32V Voltage drop at bus 1.5V

simulation

measurements

Inrush current

Transients Validation

power-up 20V

-2

0

2

4

6

8

10

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01

iin_meas

iin_sim

simulation

measurements

Vg = 20V Voltage drop at bus 0.4V

2011 26

Large signal instability

(during start-up)

Caída 0.4V Start-up

Validation

power-up 20V

-2

0

2

4

6

8

10

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01

iin_meas

iin_sim

simulation

measurements

Vg = 20V Voltage drop at bus 0.4V

-1

0

1

2

3

4

5

6

7

8

9

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01

Vg = 20V Caída en bus 1.5V

-1

0

1

2

3

4

5

6

7

8

9

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01

Vg = 20V Voltage drop at bus 1.5V

www.cei.upm.es

2011 27

BR&TE

Li-Ion

Battery

Fuel-Cell

Stacks

Inverter

Motor + Load

Series

Boost Converters

Contactors

Contactors

Non-linear

Loads

co-simulation

Maned Fuel Cell Plane

2011 28

Modeling Power Electronics for Space

LISA Pathfinder

Solid State Power Controllers (SSPCs) Modeling and simulation of solar powered distributed power architectures

http://www.activemedia.com.sg/IMAGES/MATLAB-logo.JPGhttp://crisa.es/index.htm

www.cei.upm.es

2011 29

Fuel Cell powered Power Electronics

•More Electric Aircraft Arquitectures modeling and simulation •High Voltage Distribution Network (270VDC) •Intelligent load management •Auxiliary Power Units based on Fuel Cells

INNOVA “Power distribution and management of High Voltage loads”

CENIT DEIMOS “ Development and Innovation on Polimer Membrane and Solid Oxid Fuel Cells

2011 30

BATTERY MODELING

www.cei.upm.es

2011 31

BATTERY MODEL

INTERNAL PARAMETERS

INPUTS

-INSTANT CURRENT

-INSTANT TEMPERATURE

-NUMBER OF CELLS

OUTPUTS

-STATE OF CHARGE

-CELL VOLTAGE

-BATTERY VOLTAGE

-INSTANT AND GLOBAL

DISCHARGE TIME

2011 32

Simplorer Development

BLOCKS

www.cei.upm.es

2011 33

Validation

LI-IÓN

BATTERY HP 1100mAh 3.7v

Current discharge 0.27C

0 0.5 1 1.5 2 2.5 3 3.5 40

0.5

1

1.5

2

2.5

3

3.5

4

4.5

t(h)

vcel

(v)

modelo

ensayo

ce

i@u

pm

.es

Universidad Politécnica de Madrid

Circuit Breakers

www.cei.upm.es

2011 35

Motivation

Every electric circuit requires protection against shortcircuits and

overloads.

The rest of components need to be protected and isolated from

the source of failure.

There are many kinds of switches available:

Fuses Circuit Breakers SSPCs

2011 36

Model scope

Many types of switches - difficult development of a general model if

trying to reproduce its physical components.

Air Circuit

Breaker

Bimetalic

strip

Magnetic

Circuit Breaker

X-ray

Thermal Circuit

Breaker

www.cei.upm.es

2011 37

Behavioral Model

Main Circuit

Model I – Calculates the Trip time according

to the Tripping-Time Characteristics

Input – I (A) Output – t

(s)

Model II – Data acquisition (Left) and

Simimulation Data Comparator (Right)

Model III – Arc Extinction

The main strength of this model is that

its parameters: R4, R5, C3, C4 can be

readjusted to emulate the behavior of

any switching device tested.

Data acquisition and

Look-up Table Configuration

Values can be reset for any device.

Verifies Delay Time (MI) vs. Delay

Time (Look-up Tables)

Verification Stage

2011 38

Results obtained

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0

100

200

300

400

500

600

i2t

Model

Real Data

1.5 2 2.5 3 3.5 4 0

20

40

60

80

100

120

140

160

180

200

i2t

Model

Real Data

A true i2t used as a tripping control device predicts a wrong behavior for

higher currents.

Correct behavior for the highest currents.

www.cei.upm.es

ce

i@u

pm

.es

Universidad Politécnica de Madrid

Power Distribution

Architectures Design Tool

Leonardo Laguna Ruiz

2011 40

Introduction

Examples of power systems:

Mobile devices

Computers

Airplanes

Automobiles

Critical design factors:

Time to market

Size

Energy efficiency

Cost

www.cei.upm.es

2011 41

Introduction

Main problems when designing a power system:

Many possible solutions

Prototyping is unfeasible

Solution: Simulation

Problems with simulation

Still many possible solutions

Complex models are time

consuming

Our approach: Analyze a LARGE number of solutions with a little less accuracy

After that: Analyze the BETTER solutions with more detail

Option 1) or 2) ???

Which converters in each case ???

1)

2)

2011 42

Design tool description

Characteristics of the design tool:

Analyze a wide range of

possibilities (architectures &

components)

Establish a trade-off among

Efficiency, Cost and Area

Other valuable characteristics

Follows a Top-Down design

methodology

Can interact with other tools

Provides a generic optimization

framework

www.cei.upm.es

2011 43

Example application

Feed 3 loads from a source using 100 converters from a database:

Source → 12 V

Load1 → 1.1 V

Load2 → 3.3 V

Load3 → 5.0 V

Step 1: Architecture Generator

Problem definition Converter database

(Some) Possible architectures

Converters with Losses, area and cost models

Input:

?

Output:

2011 44

Evaluation criteria

Problem specification

16 different architectures: (3-6 converters each)

3 brands, 6 different output power for

each converter

Selection criteria

Cost ≈ cost of components

Area ≈ area of components

Efficiency: depending on the loads

behavior

Step 2: Architecture and component

selection

Total combinations: 44,113,248 But we want only the best 8

%

Cost Area

Losses

www.cei.upm.es

2011 45

Optimization (search) of best solutions

▪ How to find the best 8 among 44,113,248 solutions? Evolutionary algorithms

• Harmony search

• Genetic algorithms

• Tabu search

Using Harmony Search less than 0.05% of solution space is explored to find the optimal solution

- Objective function of the 8th solution

- Objective function of the 1th solution

Searching the best solutions with Harmony Search

ce

i@u

pm

.es

Universidad Politécnica de Madrid

Modeling a Power Delivery

Network (PDN)

www.cei.upm.es

2011 47

Introduction

The power supply cannot be connected directly to the Vdd and Gnd terminals of the IC. It is necessary to use wires, these wires creates both a DC drop and time-varying fluctuation of the voltage. The voltage fluctuation can cause the following problems:

Reduction in voltage across the power supply terminals of the IC that slows down the transistor or prevents the transistor from switching states.

Increase in voltage across the power supply terminals of the IC, which creates reliability problems.

Timing margin errors caused by degraded waveforms at the output of the drivers.

2011 48

PDN elements and the range of operations

frequencies

Nabil, S.M.; El-Rouby, A.B.; Hussin, A.; “A complete solution for the power delivery system (PDS) design for high-speed deigital systems”;Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on; 2009 , Page(s): 179 - 183

www.cei.upm.es

2011 49

VRM

Provides the power to the chip.

The main influence is in low frequency (below of megahertz range).

L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 284-291, Aug. 1999.

2011 50

Decoupling capacitors

The capacitors are surface mount devices (SMDs) attached to pads on the PCB or package. When SMD capacitors supply charge (or current), the current leaves the voltage plane, travels through the voltage via, flows through the capacitor, and returns through the ground via and then to the ground plane. These contributes to increase the ESL.

L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 284-291, Aug. 1999

www.cei.upm.es

2011 51

Modeling the planes

Planes play a very important role at high frequencies by acting as high-frequency capacitors, serving as conduit for the transportation of current, and supporting the return currents of the signal lines referenced to it. Planes are large metal structures separated by a thin dielectric and are invariably used in all high-frequency packages and boards for power delivery and shielding.

Madhavan Swaminathan; A. Ege Engin, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall, 2007.

2011 52

Vias and chip characteristics

Each new technology generation results in a rapid increase in circuit densities and interconnect resistance, faster device switching speeds, and lower operating voltages. These trends lead to microprocessor designs with increased current densities and transition rates and reduced noise margins. The large currents and interconnect resistance cause large, resistiveIR voltage drops, while the fast transition rates cause large inductive LdI/dt voltage drops in on-chip power distribution networks.

M. Swaminathan, J. Kim, I. Novak, and J. P. Libous, “Power distribution networks for system on package: status and challenges,” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 286-300, May 2004

www.cei.upm.es

2011 53

PCB simulated in Q3D Extractor

2011 54

Model in Simplorer

The parameters extracted form the PCB are simulated using a signal in a trace and showing the efects of this parameters in one point of the trace and in an adjacent trace.

www.cei.upm.es

2011 55

Results @ 100 MHz

The signal has a small delay and a voltage drop.

The adjacent trace has a reflected signal.

Signal Signal affected by the parameters Signal reflected in other trace

2011 56

Results @ 1GHz

The signal is afected by the PCBs parameters.

The adjacent trace continues having a reflected signal.

Signal Signal affected by the parameters Signal reflected in other trace

www.cei.upm.es

2011 57

PCB Buck converter simulated in Q3D Extractor

2011 58

Simplorer simulation

The PCB of the typical VRM (Buck converter) is simulated with Q3D Extractor and the parameters are simulated in Simplorer.

www.cei.upm.es

2011 59

Results

The graph shows the output voltage of the VRM before and after the PCB parameters.

It can be noticed that the voltage after the PCB parameters the voltage is lower.

Voltage before the PCB parameters Voltage after the PCB parameters

2011 60