ch 1 h ichapter 1. hspice - yonsei...
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![Page 1: Ch 1 H iChapter 1. Hspice - Yonsei Universitytera.yonsei.ac.kr/class/2010_2_iccad/lecture/ICCAD... · 2012-01-30 · Hspice simulation Example> Inverter 설계및simulation.subckt](https://reader033.vdocuments.net/reader033/viewer/2022041821/5e5dbec452f02f3e3a74ea8b/html5/thumbnails/1.jpg)
Ch 1 H iChapter 1. HspiceIC CAD 실험 Analog partIC CAD 실험 Analog part
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Digital circuit designg g
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Layout?y
MOSFET!
Symbol Layout
Physical structure
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Digital circuit designg g
V il 를이용한Verilog를이용한coding 및 function 확인
Computer 가알아p서해주는 gate level circuit design
Computer 가알아서해주는 Layouty
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![Page 5: Ch 1 H iChapter 1. Hspice - Yonsei Universitytera.yonsei.ac.kr/class/2010_2_iccad/lecture/ICCAD... · 2012-01-30 · Hspice simulation Example> Inverter 설계및simulation.subckt](https://reader033.vdocuments.net/reader033/viewer/2022041821/5e5dbec452f02f3e3a74ea8b/html5/thumbnails/5.jpg)
Analog circuit designg g
TR level circuit design Hspice cadence를이용한 TR levelTR level circuit design
TR l l i l ti
Hspice, cadence 를이용한 TR level circuit design & simulation
Vload
TR level simulation
LayoutClkpi
Clkpi+1 Clkni+1
Clkni
Post layout simulationVcontVbias
Fabrication
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Analog circuit designg g
TR level circuit designCadence layout editor 를이용한손으
TR level circuit design
TR l l i l ti
로하는~layout, Hspice, cadence 를이용한 post layout simulation
TR level simulation
Layout
Post layout simulation
Fabrication
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Hspice simulationp
TR level circuit simulator! – text 기반
Netlist file(Inverter, Simulation
l fil(Inverter, amp..)
Hspice
log fileCosmos Scope
(Si l ti
Test file
Hspicesimulator
(Simulation result
veiwer)Test file(ac, dc,
transient sweep)
Simulation results file
p)
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![Page 8: Ch 1 H iChapter 1. Hspice - Yonsei Universitytera.yonsei.ac.kr/class/2010_2_iccad/lecture/ICCAD... · 2012-01-30 · Hspice simulation Example> Inverter 설계및simulation.subckt](https://reader033.vdocuments.net/reader033/viewer/2022041821/5e5dbec452f02f3e3a74ea8b/html5/thumbnails/8.jpg)
Hspice simulationp
Example> Inverter 설계및 simulation
[ICCAD@train##]/user1/train##/ > mkdir hspice[ICCAD@train##]/user1/train##/ > cd hspice[ @ ] p[ICCAD@train##]/user1/train##/ hspice> cp /user1/master/hspice/netlist.sp .cp /user1/master/hspice/PMOS_VTL.inc .cp /user1/master/hspice/NMOS_VTL.inc .ls
[ICCAD@train##]/user1/train##/ hspice> vi netlist.sp
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Hspice simulationp
Example> Inverter 설계및 simulation
.subckt Inverter out in vdd vssM p out in vdd vdd PMOS VTL w=10u l=0.05u
vddInverter Netlist
_p _M_n out in vss vss NMOS_VTL w=5u l=0.05u.ends
outin.subckt Inverter out in vdd vss
회로만들기회로만들기회로이름 회로바깥에서보이는 port 들
vss
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Hspice simulationp
Example> Inverter 설계및 simulation
.subckt Inverter out in vdd vssM p out in vdd vdd PMOS VTL w=10u l=0.05u
vddInverter Netlist
_p _M_n out in vss vss NMOS_VTL w=5u l=0.05u.ends
M f t D i 의G t 의 S 의 B lk의outin
Mosfet의이름
Drain 의node 명
Gate 의node 명
Source 의node 명
Bulk 의node 명
M_p out in vdd vddPMOS_VTL w=10u l=0.05u
vssMosfet의 type Mosfet의 width 와 length
Inverter 설계끝!
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Hspice simulationp
Example> Inverter 설계및 simulation
[ICCAD@train##]/user1/train##/ hspice> cp /user1/master/hspice/inv_sim.sp .p p _ p
[ICCAD@train##]/user1/train##/ hspice> vi inv_sim.sp@
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Hspice simulationp
Example> Inverter 설계및 simulation
DC simulation.include 'PMOS_VTL.inc'.include 'NMOS_VTL.inc'include 'netlist sp'
Model 및만들어놓은회로불.include netlist.sp
.OPTIONS POST NODE LIST
러오기
V1 vdd 0 1V2 vss 0 0Vin in vss 0.5
Voltage 정의해주기
x_inv out in vdd vss Inverter
Inverter 라는회로불러오기
c_out out vss 1p
.dc Vin 0 1 0.001
Capcitor정의
Vin 이라는 voltage source 를0 001단위로 0에서 1까지변화시
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.END0.001 단위로 0에서 1까지변화시키면서각각의 node 들의값이어떻게되는지 simulation 해라.
![Page 13: Ch 1 H iChapter 1. Hspice - Yonsei Universitytera.yonsei.ac.kr/class/2010_2_iccad/lecture/ICCAD... · 2012-01-30 · Hspice simulation Example> Inverter 설계및simulation.subckt](https://reader033.vdocuments.net/reader033/viewer/2022041821/5e5dbec452f02f3e3a74ea8b/html5/thumbnails/13.jpg)
Hspice simulationp
Example> Inverter 설계및 simulation
[ICCAD@train##]/user1/train##/ hspice> hspice inv_sim.sp > a.lis & p _ p
[ICCAD@train##]/user1/train##/ hspice> >info : @**** hspice jab concluded
[ICCAD@train##]/user1/train##/ hspice> cscope &
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Hspice simulationp
Example> Inverter 설계및 simulation파형확인하기 파형열어보자!파형확인하기 파형열어보자!
Signal Manager click!Signal Manager click!
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Hspice simulationp
Example> Inverter 설계및 simulation파형확인하기 파형열어보자!파형확인하기 파형열어보자!
이거더블클릭!
Signal Manager click! DC 결과 fil 명 0Signal Manager click! DC sweep 결과: file명. sw0AC sweep 결과: file명. ac0Transient sweep 결과: file명. tr0
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Hspice simulationp
Example> Inverter 설계및 simulation
보고싶은파형더블클릭!
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Hspice simulationp
Example> Inverter 설계및 simulation
AC simulation .include 'PMOS_VTL.inc'.include 'NMOS_VTL.inc'.include 'netlist.sp'.include netlist.sp
.OPTIONS POST NODE LIST
V1 vdd 0 1V2 vss 0 0Vin in vss 0.5 ac=1
x_inv out in vdd vss Inverterc_out out vss 1p
.ac dec 1000 100k 10gEND
Ac sweep 을 frequency 축을decade 단위로하여, 각 decade 마다 1000개의 data를찍고
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.END다 1000개의 data 를찍고, 100KHZ 에서부터 10GHz 까지의주파수응답을 simulation 해라
![Page 18: Ch 1 H iChapter 1. Hspice - Yonsei Universitytera.yonsei.ac.kr/class/2010_2_iccad/lecture/ICCAD... · 2012-01-30 · Hspice simulation Example> Inverter 설계및simulation.subckt](https://reader033.vdocuments.net/reader033/viewer/2022041821/5e5dbec452f02f3e3a74ea8b/html5/thumbnails/18.jpg)
Hspice simulationp
Example> Inverter 설계및 simulation파형확인하기 파형열어보자!파형확인하기 파형열어보자!
이거더블클릭!
Signal Manager click! DC 결과 fil 명 0Signal Manager click! DC sweep 결과: file명. sw0AC sweep 결과: file명. ac0Transient sweep 결과: file명. tr0
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Hspice simulationp
Example> Inverter 설계및 simulation
보고싶은파형더블클릭!
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Hspice simulationp
Example> Inverter 설계및 simulation
transient simulation .include ‘PMOS_VTL.inc'.include 'NMOS_VTL.inc'.include 'netlist.sp'.include netlist.sp
.OPTIONS POST NODE LIST
V1 vdd 0 1V2 vss 0 0Vin in vss sin(0.5 0.5 100x)
x_inv out in vdd vss Inverter
0.5 V ± 0.5V 의 swing 을가지는100MHz 의 sin 파신호생성
c_out out vss 1p
.tran 1p 100nEND
Transient sweep 을 1ps 마다 data 를찍어서 100ns까지 simulation
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.END를찍어서 100ns 까지 simulation 해라
![Page 21: Ch 1 H iChapter 1. Hspice - Yonsei Universitytera.yonsei.ac.kr/class/2010_2_iccad/lecture/ICCAD... · 2012-01-30 · Hspice simulation Example> Inverter 설계및simulation.subckt](https://reader033.vdocuments.net/reader033/viewer/2022041821/5e5dbec452f02f3e3a74ea8b/html5/thumbnails/21.jpg)
Hspice simulationp
Example> Inverter 설계및 simulation파형확인하기 파형열어보자!파형확인하기 파형열어보자!
이거더블클릭!이거더블클릭!
Signal Manager click! DC 결과 fil 명 0Signal Manager click! DC sweep 결과: file명. sw0AC sweep 결과: file명. ac0Transient sweep 결과: file명. tr0
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Hspice simulationp
Example> Inverter 설계및 simulation
보고싶은파형더블클릭!
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실습
차동증폭기 (differential amplifier) 의설계및시뮬레이션Vdd VddVdd Vdd
W=1.9uL 0 05
W=1.9uL 0 05
DC, AC, Transient sweep 후파형확인Differential input signal generatori i 1
Outp OutnVss
L=0.05u L=0.05u vin in vss ac=1Voff off vss 0.75Einp inp off in vss 0.5Einn inn off in vss 0 5
INp INn
Vir gnd
W=5uL=0.05u
W=5uL=0.05u
Einn inn off in vss -0.5
Vvbias vbias vss 0.7
Vbias
Vir_gnd
W=10uL=0 3u
.dc vin -0.5 0.5 0.001
.ac dec 1000 100k 10g
.tran 1p 100nVbias L=0.3up
모든 NMOS 의 bulk 는 vss로모든 PMOS 의 bulk 는 vdd로연결!
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Vss
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Appendixpp• Parameter 설정및 parameter sweepHspice netlist에서 parameter 설정은다음과같이한다. 예를들어어떤 dc voltage 값을 cont 라는 parameter (변수) 값으로지정하고싶다면,
Vcont cont vss ‘cont’
와같이 ‘ ‘ 안에변수값을써주면된다. 그리고.param cont=0.6
과같이선언해주면 cont 에는 0.6 이란값이들어가게된다. Cont 값을바꿔가며 parameteric sweep 을하려면, dc vx 0 1 0 001 sweep cont 0 1 0 1.dc vx 0 1 0.001 sweep cont 0 1 0.1과같이설정해준다. 이렇게해주면, cont 값을 0 에서 1 까지 0.1 씩변화시키며 10번반복하여 dc sweep 을하게된다. 이는 ac sweep transient sweep에서도마찬가지로적용할수있다이는 ac sweep, transient sweep 에서도마찬가지로적용할수있다..ac dec 1000 100k 10g sweep cont 0 1 0.1.tran 1p 100n sweep cont 0 1 0.1
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Appendixpp• Cosmos scope measurement tool
Cosmos scope measurement tool
Measurement tool 을잘사용하면파형에대한거의모든정보를얻을수있다. 예를들어파형의주파수혹은swing 폭, rising time, falling time 등을알고싶을땐, 직접재려고하지말고 measurement tool 을이용하라
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