ch02 datapathsaa

8/8/2019 Ch02 datapathsaa

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ECP3116 Digital Computer DesignTrimester III-06/071/40

Chapter 2

Register Transfers and Datapaths

Outline

Datapaths and Operations

Register Transfer OperationsMicrooperations

Multiplexer-based Transfer

Bus-based Transfer

Datapath

The Arithmetic/Logic UnitThe Shifter

Datapath Representation

The Control Word

Pipelined Datapath


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Datapaths & Operations (I)Datapaths & Operations (I)

Most digital systems can be partitioned into two types of modules:DatapathControl unit

Datapath -performs data-processing operations- consists of processing logic and registers

Control unit - determines the sequence of data-processing

operationsThe movement and processing of data in the registers are referredto as register transfer operations. Register transfer operations are specified by the following three

basic components:

- the set of registers in the system- the operations that are performed on the stored data- the control that supervises the sequence of operations


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Provide the interaction betweendatapath and control unit with otherparts of the digital system, such asmemory and I/O

Datapaths & Operations (II)Datapaths & Operations (II)


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Register Transfer Operations (I)Register Transfer Operations (I)

Registers are denoted by uppercase letters that indicate thefunction of the register, Examples:

AR- address registerPC - program counterIR- instruction register

Representation ofRegisters


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Data transfer from one register to another is designatedby a replacement operator ( ).

R2 R1 - transfers the contents of reg. R1 (source) into reg.R2 (destination)

If(K1 =1) then R2 R1 or K1:R2 R1 - transfers R1into R2 only if K1 =1

K1: Control signal generated in control unit

Can be any Boolean function that evaluates to 0 or 1

K3:R2 R1,R1 R2 - simultaneous transfers

More conciserepresentation

Register Transfer Operations (II)Register Transfer Operations (II)


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Register Transfer Operations (III)Register Transfer Operations (III)


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Microoperations (I)Microoperations (I)

A microoperation is an elementary operation performed ondata stored in registers or in memory

There are four types of micro-operations:Transfer:

Transfer binary data from one register to anotherwithout changing the data

Arithmetic: Perform arithmetic on data in registers (add,subtract, increment, decrement, complement)

Logic: Perform bit manipulation on data in registers

Shift Shift data in registers


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Arithmetic microoperation examples:R0n R1 + R2 - the contents ofR2 are to be added tocontents ofR1 and the sum transferred to R0. To implement thisstatement three registers and one adder are requiredR0nR1 + R2 + 1 - the R2 + 1 is the 2complement ofR2,hence R1 + R2 + 1 is equivalent to R1- R2

There is a direct relationship between the statement in registertransfer notation and the registers and the functions required fortheir implementation. This can be observed in the followingexample

X K1: R1nR1 + R2

X K1: R1nR1 + R2 + 1

K1 activates an operation. X selects either addition (X=0) or

subtraction (X=1)

Microoperations (II)Microoperations (II)


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Microoperations (III)Microoperations (III)


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Logic microoperation Useful in manipulating bits stored in a register

Examples: K1 + K2: R2nR1+R3, R4nR5R6 the + between K1 and K2is an ORoperation (+ occurs in a control),the + between R1 and R3 specifies an add microoperation (+ occurs in

a microoperation), denotes ORmicrooperation between R5 and R6 Logic microoperations are used to set (OR), reset (AND), andcomplement (NOT, XOR) bits of a number

Microoperations (IV)Microoperations (IV)


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Shift microoperationUsed for lateral movement of data in registers

Examples:R0n srR0, R1n sl R2R0n srR0 implies a 1-bit shift to the right ofR0R1n sl R2 means transfer the contents ofR2 shifted

one bit to the left into R1

Microoperations (V)Microoperations (V)


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Shift microoperation (cont.)Incoming bit:

Rightmost bit of the destination reg. for a left-shift microoperation

Leftmost bit of the destination reg. for a right-shift microoperation

May have different values depending upon the type of shift

microoperation In this chapter we assume to be zero

Outgoing bit:

The leftmost bit of the source reg. for a left-shift microoperation

The rightmost bit of the source reg. for a right-shift microoperation

Can be treated in different ways depending upon the type of shiftmicrooperation

In this chapter its simply discarded after shift microoperation

Microoperations (VI)Microoperations (VI)


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MultiplexerMultiplexer--based Transfer (I)based Transfer (I)

A

multiplexer (MUX) is used to select the source when a registerreceives data from two or more different sources at different times K1 : R0nR1, K1K2 : R0nR2

When K1 = 1, R1 is loaded into R0When K1 = 0 and K2= 1, R2 is loaded into R0W

hen both K1 and K2= 0 no change in the contents ofR0


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MultiplexerMultiplexer--based Transfer (II)based Transfer (II)


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BusBus--based Transfer (I)based Transfer (I)

A bus is a shared transfer path that minimizes the hardwarecomplexity

Single bus: one MUX is implemented to select one sourceand a control is used to select the destination

One or more destinations can receive at a time fromonly one source

When the bus is compared with the dedicated MUX

(as in the next slide), the number of total gates required bythe bus and the dedicated transfer are 4n and 9nrespectively

Also the number of data input connections to the MUXsis reduced by the bus from 6n to 3n


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BusBus--based Transfer (II)based Transfer (II)


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A three-state bus can be constructed with three statebuffers to replace MUXs

The outputs can be connected together to form a bitline of a bus, using only one level of logic gates

On the other hand, MUXs contain multiple levels ofgates, introducing more logic and increasing delay

Three-state bus is used as a bi-directional bus for

fast transfer, also the number of data connections to theregister blocks is reduced to half (3n) that of the singlebus (as in the next slide)

BusBus--based Transfer (III)based Transfer (III)


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Memory transfer:uses read and write operations

Read operation for transfer of data word from the memoryto the outside, while the write for transfer of new data intothe memory

Read: DRn M[AR] implies a transfer of data word froma memory location (specified by the address in registerAR)into register DR

Write: M[AR]n DR implies a transfer of data from

register DRinto a memory location (specified by the addressin registerAR)

Examples (refer to the next slide):Write: M[A1]n D2Read: D1nM[A2]

BusBus--based Transfer (V)based Transfer (V)


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BusBus--based Transfer (VI)based Transfer (VI)


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Datapath (I)Datapath (I)

A Datapath is the combination of a set of registers (registerfile) with a sharedALU (function unit) and interconnecting paths

Register file contains a group of registers, MUXs,decoders, etc Function unit contains arithmetic logic unit (ALU) andshifter for processing data Example (refer to the next slide): R1n R2 + R3i. A selectplaces R2 onto BusAii. B selectplaces R3onto input 0 of MUX B, which is inturn placed by MB select onto Bus Biii.G selectprovides A + B

iv.MF selectplaces ALU output on MUX F outputv. MD selectplaces MUX F output onto Bus Dvi.Destination select selects R1as destination forBus Dvii.Load enableenables R1to be loaded from Bus D


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Datapath (II)Datapath (II)


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The Arithmetic/Logic Unit (ALU) (I)The Arithmetic/Logic Unit (ALU) (I)


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The parallel adder isthe basic component ofthe arithmetic circuit

The operation is selected

by Cin while the output isgiven by G as in thefollowing table

The Arithmetic/Logic Unit (ALU) (II)The Arithmetic/Logic Unit (ALU) (II)


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The Arithmetic/Logic Unit (ALU) (III)The Arithmetic/Logic Unit (ALU) (III)


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With a logic circuit the common four logic operations(AND, OR, XOR, NOT) can be carried as shown below

The Arithmetic/Logic Unit (ALU) (IV)The Arithmetic/Logic Unit (ALU) (IV)


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With a combined arithmetic/logic unitboth arithmetic and logic operationscan be carried as shown below

S2 selects either arithmeticor logic operation, while S0& S1 select the particularoperation in each

The Arithmetic/Logic Unit (ALU) (V)The Arithmetic/Logic Unit (ALU) (V)


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The Shifter (I)The Shifter (I) The basic shifterperforms one of the two types of transformations on the data (rightshift, left shift) The transfer from a source register to a destination register can be done using only

one clock pulse if the shifter is implemented as a combinational circuit (compareswith the normal shifter which requires three clock pulses to load a source, shift, andtransfer to a destination)Refer to the figure below: S=00 causes B to be passed through the shifter unchanged,S=01 causes rs, s=10 causes ls.Serial inputs IL & IRare used by ls & rs to fill right &left positions, respectively


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A barrel shifter is acombinational circuitthat shifts or rotates theinput data bits by thenumber of bit positionsspecified by a binaryvalue on a set ofselection lines (S0,S1)In a 2nbit barrelshifter, ipositions leftrotation is the same as2n - ibits of right

rotationThe following tableshows the left shifts forthe 4-bit barrel shifter

The Shifter (II)The Shifter (II)


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ECP3116 Digital Computer DesignTrimester III-06/07 30/40

Datapath Representation (I)Datapath Representation (I)

Refer to the block diagram of the datapath in slide no 22, whichincludes 4 registers, selection logic, ALU, shifter, 3 MUXs

A typical datapath (large number of registers) could be reducedto Register file and Function unit as in the diagram (next slide)

ARegister file is a set of registers having commonmicrooperations performed on them. It is a fast memory that

permits one or more words to be read and written simultaneously

AFunction unit combines theALU and the shifter with the

shared MUX F

The select inputs G, H, MF can be combined together to define amicrooperation as in the table (next slide)


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A address & Baddress access wordsto be read onto A data& B data,respectively D address accessesa word to be writteninto from D dataWriteenables theloadAll these accessesoccur in the sameclock cycle

The size of the fileregister is 2m x n, m isthe number of registeraddress bits and n isthe number of bits perregister

Datapath Representation (II)Datapath Representation (II)


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MF is 1 if the leftmost twobits of FS are both 1If MF=0, G codes specifythe output of function unitIf MF=1, H codes specifythe output of function unit

Code Transformations:MF=FS3.FS2 G3G2G1G0 =FS3FS2FS1 FS0 H1H0= FS1FS0

Datapath Representation (III)Datapath Representation (III)


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The Control Word (I)The Control Word (I)

Selection variables for thedatapath control themicrooperations executed withinthe datapath for any given clockpulse, including

addresses for data readingfrom file register function performed byfunction unit data loading into the fileregister

The combined values for theseselection variables specify a

control wordAs in the datapath the controlword consists of 16 binary controlinputs divided into 7 fields Encoding ofcontrol word forthe datapath (next slide)


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The Control Word (II)The Control Word (II)


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Sequences of microoperations can be realized by designing a control unitthat produces the appropriate sequences ofcontrol words

The Control Word (III)The Control Word (III)


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Pipelined Datapath (I)Pipelined Datapath (I)

APipelined Datapath is done by breaking a conventionaldatapath into parts by inserting registers as pipelineplatformsbetween these parts

APipelined Datapathprovides faster speed of execution

than conventional datapath

As in the next slide, Conventional: total delay = 12ns (clock period), rate ofmicrooperation execution = 83.3 MHz

Pipelined:delay of operand fetch (OF) is 4ns, delay ofexecution (EX) is 5ns, delay of write back (WB) is 5ns=> min clock period = 5ns => operating frequency = 200MHz

(2.4 times the conventional)


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Pipelined Datapath (II)Pipelined Datapath (II)


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The first person takes one or more components to be

included in custom product from storage bins and placesthem on the conveyor

The second person assembles the components

The third person takes the assembly from the conveyor belt

and puts it into storage bins

Pipelined Datapath (III)Pipelined Datapath (III)


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OF consists of readingregister values (A&B),selecting register value(MB). The pipeline platform

stores the operand(s) to beused in EX during next clockcycle In EX a function unitoperation occurs, and theresults captured by 2ndpipeline platform

WB includes selection ofthe MUX D input andwriting back into register file

Pipelined Datapath (IV)Pipelined Datapath (IV)


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ch02 datapathsaa

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