challenges of parallel simulation of power systems_english
TRANSCRIPT
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www.opal-rt.com
Ould Bachir, TarekJanuary 8th, 2015
Challenges of Parallel Simulation of
Power Systems
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Outline
1 2 3 4
Introduction Challenges
Large Nerworks
Problematic
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Outline
1 2 3 4
Introduction Challenges
Large Nerworks
Problematic
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Power System Simulation
Introduction
Network Simulation Controller Prototyping
Transients Analysis Fault Scenarios
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Power System Simulation
ePHASORsimReal-Time TransientStability Simulator10 ms time step
HYPERsimLarge Scale Power SystemSimulation for Utilities & Manufacturers25 µs to 100 µs time step
eFPGAsimPower Electronics Simulation on FPGA1 µs to 100 ns time step
1 s(1 Hz)
10,000
2,000
1,000
500
100
10
0
10 ms(100 Hz)
50 µs(20 KHz)
10 µs(100 KHz)
1µs(1 MHz)
100 ns(10 MHz)
10 ns(100 MHz)
20,000
Transients Period (frequency)
Number of buses
eMEGAsimPower System & Power Electronics SimulationBased on Matlab/Simulink and SimPowerSystems10 µs to 100 µs time step
Introduction
Phase Domain
Time Domain
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Introduction
The
Host
Controller
Real-Time Simulator
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Introduction
15-20 years ago, the revolution was to build simulators from off-the-shelf PC (PCs were connected in clusters)
HIL Simulators
OP5607 (Virtex 7)
OP4500 (Kintex 7)
CPU computing power is often insufficient, hence FPGA are often used to offload part or total of computing load
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Outline
1 2 3 4
Introduction Challenges
Large Nerworks
Problematic
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Problematic
In HIL simulation, a real hardware (i.e. a physical controller) is connected to the simulator. The simulation loop must be as fast as possible!
Simulated plantPhysical controller
PWM pulse
Analog V/I Hall Effect
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Problematic
• Advances in semiconductor technology allow very high switching frequencies (10kHz to 100kHz) to be reached
• Such frequencies have various benefits for the power system: higher power density, lower THD, etc.
• They are however very challenging for real-time simulatorsthat must achieve time steps below 1 μs
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1.51 kHz PWM (UA)
Logic
level
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Load currents
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Time (ms)
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Logic
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Time (ms)
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Curr
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Time (ms)
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1.520 kHz PWM (UA)
Logic
level
Time (ms)
0 5 10 15 20
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Load currents
Curr
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(A)
Time (ms)
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Problematic
• To meet such tight timing requirements, FPGA-based real-time simulation has proven to be an effective solution (the only one in fact!)
• However, solving differential algebraic equations (DAEs) on FPGA means designing an application specific processor (ASP) from scratch!
Physical controller
PWM pulse
Simulated plant
FPGA
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Outline
1 2 3 4
Introduction Challenges
Large Nerworks
Problematic
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Challenges
• Technical challenges:• Number format: Floating-Point (FP) vs. Fixed-Point (FXP)• FP Operators have long latencies• Clock Frequency: how to increase it with minimal impact on the latency• How to model power converters (switched networks)
• Practical challenges:• FPGA programming is tedious and requires special skills (end user is a
power electronics specialist)• Programming and reprogramming times are long: objective is to avoid the
penalty on prototyping
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Solutions to technical challenges
• Self-Alignement technique
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Solutions to technical challenges
• High Radix Carry Save (HRCS) used to reduce latency of the FP operators
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Solutions to technical challenges
• Custom operators with fused-path
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Solutions to practical challenges
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Solutions to practical challenges
• Architecture of the computing engine
Blocks RAM, CPU reprogrammable
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Solutions to practical challenges
Workflow
Host Computer(Console)
Design Power Electronics Circuit
Real-TimeSimulator
Execute the CPU Model
FPGA
Execute the power converter model on FPGA
No hardware design
skills required
No reprogramming
No bitstream generation
Physical controller
HIL Simulation
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Outline
1 2 3 4
Introduction Challenges
Large Nerworks
Problematic
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Large networks simulation
HVDC Transmission System
MMC 2MMC 1
1GW
± 320 kV
C = 10mF
Larm = 50mH
C = 10mF
Larm = 50mHBypass
breaker 1
Rstart = 100Ω
Bypass
breaker 2
Rstart = 100Ω 70 km DC cable
1 2 12
Main ac
breaker 1
Main ac
breaker 2
AC EQ.
SRC1
AC EQ.
SRC2
CPU #1:
Eq. Source no 1CPU #2: VSC-MMC Station no. 1 CPU #3: VSC-MMC Station no. 2
CPU #4:
Eq. Source no 2
Low Level
Control
CPU #6: Inverter Control
Upper Level
Control
Upper Level
Control
CPU #5: Rectifier Control
Low Level
Control
MMC ConvertersSimulated on FPGA
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Large networks simulation
MMC Structure
400 SM
eq. 9600 semi-conducteurs
MMC Computing Engine Architecture
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CPU MMC
FPGA MMC
Large networks simulation
Perfect match with the offline simulation reference
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time (s)
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i ua(p
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Vc
tot
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(pu)
time (s)
CPU MMC
FPGA MMC
Large networks simulation
Perfect match with the offline simulation reference
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Vc
tot
up A
(pu)
time (s)
CPU HVDC
FPGA HVDC
Large networks simulation
Perfect match with the offline simulation reference
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Thank you for your kind attention.
www.opal-rt.com
Acta est fabula
Contact:
Tarek Ould Bachir
R&D Engineer
Opal-RT Technologies