chameleon: a dual-mode bluetooth/wifi receiver design
TRANSCRIPT
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Chameleon: A Dual-Mode Bluetooth/WiFi Receiver Design
Ahmed Emira, Alberto Valdes-Garcia, Bo Xia, Ahmed Mohieldin, Ari Valero-Lopez, Sung Tae Moon and Chunyu Xin.
Faculty Advisor: Dr. Edgar Sánchez-Sinencio
Analog & Mixed-Signal Center (AMSC) Texas A&M University
IEEE CAS SocietyChapter at Dallas, Texas
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Outline• Previous work: Bluetooth Receiver in CMOS 0.35µm
• System Level Design– Technology features– Main Bluetooth and Wi-Fi specs– Previously reported architectures– Proposed dual-mode architecture– Impact of non-idealities on the BER performance
• Building Blocks– LNA– Mixer– VCO and PLL– VGA– ADC
• Experimental Results
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0.35µm CMOS Bluetooth Low-IF Receiver IC
PLL
LNA
I
QRF filter
PolyphaseFilter
Demodulator
OffsetCancellation
/Decision
2.4GHz 2MHz
Developed during 2001 and 2002 at the AMSC.
Authors: Wenjun Sheng, Bo Xia,Ahmed Emira, ChunyuXin, Ari Ari Valero-Lopez, Sung Tae Moon and Edgar Sanchez-Sinencio.
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• Publications:– 2002 RFIC Conference, Best Student Paper Award (third place).
– Journal of Solid-State Circuits: January 2003 (Receiver) and August 2003 (Demodulator).
– Transactions on Circuits and Systems – II: November 2003 (Complex Filter).
0.35µm CMOS Bluetooth Low-IF Receiver IC
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Chameleon Receiver: Timeline
802.11b/Bluetooth standards study
Dual-mode architectures survey
Baseband BER simulations
Rx System Specifications
Building Block Specifications
Circuit Level Design
Layout and Chip Submission
PCB Design for Block and System Testing
Block and System Testing
Paper Submission to ISSCC
Q2 Q3 Q4 Q1 Q2 Q3
2002 2003Phase
Spring Summer Fall Spring Summer Fall
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Chameleon Receiver• Previous work: Bluetooth Receiver in CMOS 0.35µm
• System Level Design– Technology features– Main Bluetooth and Wi-Fi specs– Previously reported architectures– Proposed dual-mode architecture– Impact of non-idealities on the BER performance
• Building Blocks– LNA– Mixer– VCO and PLL– VGA– ADC
• Experimental Results
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Technology features
• IBM SiGe BiCMOS 6HP 0.25um• Transit frequency (fT) 47GHz• 6 aluminum metal layers• Analog metal (4um thick, 0.00725 Ω/ )• Varactor diode (intrinsic base-collector diode)• Metal to metal cap (1.4fF/um2)• MOS cap (3.1 15%fF/um2)• Poly resistors (210 20%, 3600 25% Ω/ )
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Standards Overview
2.4 – 2.48GHz2.4 – 2.48GHzFreq band
DSSS-CCKFH-GFSKModulation
HigherLowerPower
1-11Mb/s1Mb/sData rate
802.11bBluetooth
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Dual-Mode Receiver Architecture
• 3 possible alternatives for Bluetooth and Wi-Fi dual mode architectures:
Area and power ↓
Sharing ↑
DC offset & 1/f noise ↑
Low-IF and DCR
Best fit for each standard Sharing ↓
Power ↑
Sharing ↓
Low-IF and Low-IF DCR and DCR
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Previously Reported Dual-Mode Receivers
• DCR for WiFi, low-IF for Bluetooth.• Shared RF front-end.• Separate baseband circuits
Fractional-NSynthesizer
BT/802.11b
SEL
Demod
802.11b
BT
ClockGenerator
I
Q
I
Q
LNA
[1] J. C. H. Darabi, et al "A Dual Mode 802.11b/Bluetooth Radio in 0.35mm CMOS," ISSCC 2003, San Francisco, CA.
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• Double downconversion to avoid LO self mixing and injection locking between PA and VCO.
• DCR for Wi-Fi and low-IF for Bluetooth.• Shared RF and programmable dual-mode baseband.
802.11b
LNA
LO2-I
LO2-QLO1
BTBT
802.11b
I
Q
[2] D. K. T. Cho, et al "A 2.4Ghz Dual-Mode 0.18mm CMOS Transceiver for Bluetooth and 802.11b," ISSCC 2003, San Francisco, CA.
Previously Reported Dual-Mode Receivers
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Proposed Dual-Mode Architecture
Direct-conversion BT/WiFi receiver architecture
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Remarks• Direct-conversion architecture is used for both
standards to save power and avoid the image problem in IF architectures.
• LNA & Mixer are shared between BT and Wi-Fi.• Gm-C LPF with programmable bandwidth is used to
accommodate both standards.• Parallel Pipeline ADC architecture is used:
– BT: sampling rate = 11MHz, 11bits– Wi-Fi: sampling rate 44MHz, 8bits
• Due to the short allowed settling time, the VGA has only two gain steps in BT mode and the signal level at the ADC input will vary by 24dB.
• In Wi-Fi mode, gain steps of 2dB are employed.
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Impact of DC offset and DC offset correction on the BER performance (Wi-Fi mode)
A: 0 offset. B: 5% offset, C: 10% offset, D: 15% offset E: offset cancelled with 4 HP poles at 5KHz, F: offset cancelled with 4 HP poles at 10KHz.
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Wi-Fi Interferer Rejection Requirements
• In the presence of a modulated interferer at 25MHz with a power 35dB above the signal of interest, the receiver should show 1E-5 BER for an SNR 6dB above the minimum sensitivity.
• The channel selection filter should reject an strong interferer while not affecting the spectrum of interest.
30
20
10
0
-10
-20
-30
-40
-50
-60
5 10 15 20 25 30 35 40 45
Frequency [MHz]
Sig
nal P
ower
[dB
]
Modulated Inteferer
Desired Signal
Filter Response
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Impact of the channel selection filter characteristics on the BER performance (Wi-Fi mode)
• 5th order Butterworth filter with fC=5.5MHz with (B) and without an interferer (A).
• 4th Chebyshev filter with fc=6MHz with (D) and without an interferer (C).
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Impact of the mismatch between I and Q channels on the BER performance (Wi-Fi mode)
• A: Receiver performance including channel selection filter and DC offset correction.
• B: Performance with a 10º error in the generation of I and Q signals.• C: Performance with 1.5dB gain mismatch between I and Q
channels in addition to the phase error.
Required Receiver SNR
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Adjacent Channel Test
LNA Mixer Filter VGA ADC-70
-60
-50
-40
-30
-20
-10
0
10Adjacent channel test in Bluetooth mode
Sig
nal l
evel
in d
Bm
Signal levelInterferer level
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NF, IIP3, and IIP2 contributions
Mixer
Filter
LNA+VGA+ADC
IIP2 contributions of different blocks
LNA
Mixer
Filter
IIP3 contributions of different blocks
LNA
Mixer
Filter
VGAADC
Noise contributions of different blocks
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Power consumption and area contributions
LNA/Mixer
PLL
Filter
VGA
ADC
Area contributions of different blocksin WiFi mode
LNA/Mixer
PLL Filter
VGA
ADC
Power consumption contributions of differentblocks in WiFi mode
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Chameleon Receiver• Previous work: Bluetooth Receiver in CMOS 0.35µm
• System Level Design– Technology features– Main Bluetooth and Wi-Fi specs– Previously reported architectures– Proposed dual-mode architecture– Impact of non-idealities on the BER performance
• Building Blocks– LNA– Mixer– VCO and PLL– VGA– ADC
• Experimental Results
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Low Noise Amplifier
• Gain = 15/-15dB
• NMOS drive is used for better linearity.
• Cm ensures matching in low-gain mode.
Ls Ls
LdLdLNA bypass switches and attenuator
LNA_rf_biasi_tail
CmVin+
Vin- M1 M2
M5
M6
M7
M8
M9
M3 M4
Q1 Q2
Rb Rb
Bond wire
Cd Cd
Vbb
Rb Rb
Cm
LNA_cas_bias
Vo+
Vo-
VDD
LNA_bypass
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I/Q Downconversion Mixer
• I & Q share the same RF drive stage• NMOS drive for better linearity• NPN switch to reduce LO drive and 1/f noise
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Frequency Synthesizer• VCO running at 2fo• I/Q generation using divide-by-2 flip flop.• Capacitor multiplier to integrate loop filter cap.
fref = 2MHz
4.9GHz
2
2.45GHz
CP PFD
2 2 2
mux
4
4 2 Programmable
Divider
15/16 Prescaler
ChannelSelection
C1=340pFC2=26pFVCO R1=52kΩΩΩΩBuffer
I
QToMixers
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Phase Switching Prescaler
fin / 4fin
÷ 2IQIQ
fin / 2
5 GHz 2.5 GHz1.25 GHz
To RF Mixers
625 MHz
÷ 2IQIQ
FrequencyControl
÷ 2
ModulusControl
÷ Nfout
IQIQ
÷ 2
FrequencyControl
fin / 8
/2
/2
/2
/2
/2
IQIQ
• Phase switching prescaler for reduced powerconsumption compared with traditional architectures.
• No feedback in flip-flops.
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Charge PumpVdd
Vdd
35 µµµµA
UP
DWN
Iout
VbiasN
VbiasP
Cascode current mirrors minimize the current mismatch in Up and Dwn operation.
VDD
UP
DWN
D Q
CLR
D Q
CLR
"1"
"1"
Div
Ref
Out
Charge PumpPFD
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Capacitance Multiplier
Total Current: 150 µµµµA
10
+=
Mz
zin
Vdd
C
5 µµµµA
VbiasN
VbiasPIin
1:25
1:25
M1
M2
M4
M3
A
B
Biasing
MC
1/Mgm1
1/Mgm1<<R1
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VCO
• LC tuned negative-gm VCO• Analog metal inductor• Varactor diode• DC-decoupling for driver
base to improve linearity and noise
• Bypass capacitor improves phase noise 2dB
• L=1.5nH, Q=13
Vc
Vb
Ib
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Channel Selection Filter• 5th order Butterworth OTA-C filter.• Passive 1st pole is used to relax the biquad (OTA)
linearity requirements.• Programmable bandwidth through switching R&C.
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Biquadratic Section
_
+
+_
_
+
+
_
_
+
+
_
_
+
+_
Vin+
Vin-
VBP1+
VBP1-
VLP1-
VLP1+
CM
Info
rmat
ion
CM
Info
rmat
ion
gm3 gm2 gm1 gm1
C
C
C
C
+
-
Vref+
-
Vref
Vbias Vbias
Direct connection between consecutive OTAs in the filter is exploited in the implementation of the CMFB circuit.
2
1
m
m
gg
Q =C
gm10 =ω
VDD
Ibias
M2
M1M1
VCMFB
VDD
IDC
VCM
M2
VDD VDD
VrefMS MS
MA MA
IDC
VDC=1.6V
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Dual-mode OTA
- Source degeneration- Current scaling Ibias×R=constant
- The standard is chosen by switching R (coarse tuning)- Fine frequency tuning using bank of capacitors C
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Variable Gain Amplifier
• 0-62dB gain, 2dB steps in Wi-Fi• 0/24dB (one stage) gain in Bluetooth• RC HPFs used to reject dc offset• VGA stage with constant output offset
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Constant output offset VGA
• The gain is controlled by d:
• The output offset is independent of d.
• This assumes that the offset in Vi is completely removed by the RC HPF.
• Problem: G11 and G12 will load the HPF we have to use a buffer at each input resistor
G2
G11
VOS
ViVi
G12d
2
1211
GdGG
Gain+=
OSVG
GGoffsetoutput
2
1211 +=
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Constant output offset VGA, Cont’d
• A buffer is used to drive eachinput resistor.
• The feedback factor isindependent of the gain. This makes the OpAmp designeasier.
• Bandwidth and phase marginare independent of the gain.
• Note that the capacitor C does not load the previous stage since it is in series.
• However, the parasitic capacitance of the top and bottom plates to ground will load the previous stage!
G2
G11Vi
Vo
G12d
bufferC
R
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Time-Interleaved Pipeline ADC
• Programmable resolution and sampling rate.
• On line digital calibration.
Dig
italC
orre
ctio
n
SHAVin
4 bit 3 bit 4 bit 3 bit
4 bit 3 bit 4 bit 3 bit
Dig
ital
Cor
rect
ion
SHAVin
4 bit 3 bit 4 bit 3 bit
Bluetooth Mode11bit - 11MS/s
11-bit
&M
ultip
lexe
r
Dig
italC
orre
ctio
n&
Mul
tiple
xer
SHAVin
4 bit 3 bit 4 bit
4 bit 3 bit 4 bit802.11b Mode8bits - 44MS/s
9-bit
DACADC
-+G
MDACSub-ADC
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Chameleon Receiver• Previous work: Bluetooth Receiver in CMOS 0.35µm
• System Level Design– Technology features– Main Bluetooth and Wi-Fi specs– Previously reported architectures– Proposed dual-mode architecture– Impact of non-idealities on the BER performance
• Building Blocks– LNA– Mixer– VCO and PLL– VGA– ADC
• Experimental Results
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Receiver Die Photo
5.6mm
3.8mm
Deep Trench Isolation
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Testing Board
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Receiver Sensitivity
Bluetooth = -91dBm Wi-Fi (11Mb/s) = -86.5dBm
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Receiver Linearity
-50 -45 -40 -35 -30 -25 -20 -15 -10-80
-60
-40
-20
0
20
40
60
2-Tone Input Power [dBm]
Out
put [
dBm
]
IIP3
-60 -50 -40 -30 -20 -10 0 10 20
-60
-40
-20
0
20
40
60
80
2-Tone Input Power [dBm]
Out
put [
dBm
]
IIP2
IIP3 = -13dBmIIP2 = 10dBm
Both BT / Wi-Fi modes
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LO Phase Noise
-124 dBc/Hz @ 3MHz
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LPF Programmability
BT Wi-Fi
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64.2 dB at 11MSample/s for the 550 kHz BT signal
59.7 dB at 44MSample/s for the 5.5 MHz 802.11b signal
SNR Measurement for ADCBT Wi-Fi
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Comparison Table
2.5V1.8V2.7VSupply voltage
10mm2----ADC area (w/ pads)
9mm2 (w/o ADC)16mm2 (transceiver)N/ARx area (w/ pads)
10dBm20dBmN/AN/AIIP2
-13dBm-12dBm-8dBm-7dBmIIP3
15.6mA13.4mA----ADC active current
30mA (w/o ADC)
27.9mA (w/o ADC)
60mA65mA46mARx active current
0.25µµµµm BiCMOS0.18 µµµµm CMOS0.35 µµµµm CMOSTechnology
-86dBm-91dBm-92dBm (0dB SNR)-80dBm-88dBm-82dbmSensitivity
6MHz (LPF)600kHz (LPF)7.5MHz (LPF)1MHz (BPF)7.5MHz (LPF)1MHz (BPF)Filter bandwidth
IncludedNot includedNot includedADC
SharedsharedseparateBaseband amplifier
ProgrammableprogrammableseparateChannel select filter
AC couplingInjection at AGC inputProgrammable loopOffset cancellation
DCRDCRDCRLow-IFDCRLow-IFReceiver Architecture
Wi-FiBTWiFiBTWiFiBT
This design[2][1]
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Summary• Direct conversion architecture for BT / Wi-Fi
allows maximum level of block sharing• Lower consumption than previous dual-mode
implementations (27.9 mA / 30mA)• Shared RF front-end and programmable
baseband components• Programmable channel selection filter with
constant linearity• AC coupled VGA with constant output offset• On-chip time interleaved pipeline ADC