chap. 6 digital arithmetic: operations & circuitsmicrocom.koreatech.ac.kr/course...

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Dept. of Info. & Comm.Chap. 6 Digital Arithmetic

6-1Chap. 6 Digital Arithmetic: Operations & Circuits

Introduction This chapter will be concentrate on how computers perform the basic

arithmetic operations 6-1 Binary Addition

Addition is the most important operation in digital systems Subtraction, multiplication and division are usually implemented using addition. Basic Rules :

0 + 0 = 01 + 0 = 11 + 1 = 10 = carry of next position + 0

1 + 1 + 1 = 11 = carry of next position + 1 Binary Example :

0 1 1 (3) 1 0 0 1 (9) 1 1. 0 1 1 (3.375)+ 1 1 0 (6) + 1 1 1 1 (15) + 1 0. 1 1 0 (2.750)1 0 0 1 (9) 1 1 0 0 0 (24) 1 1 0. 0 0 1 (6.125)



6-2

6-2 Representing signed Numbers Sign Bit

0 : positive, 1 : negative Sign-magnitude system : Fig. 6-1

Example : 5210 (decimal) = 1101002 (binary)+ 5210 = 01101002 (sign-magnitude)- 5210 = 11101002 (sign-magnitude)

This is simple, but is normally not used, as it makes circuit implementation more complex

1’s Complement Form Example : 101101(original binary number) 010010(1’s complement) Change each bit in the number to its complement

2’s Complement Form Example : 4510 (decimal) = 1011012 (binary)

+ 4510 = 01011012 (true binary) - 4510 = 10100112 (2’s complement)= 1010010(1’s complement) + 1

Take the 1’s complement and add 1 to the LSB position

1) Sign magnitude system2) 1’s complement system3) 2’s complement system

+14 -14

0 0001110 1 0001110

0 0001110 1 1110001

0 0001110 1 1110010



6-3

Representing signed Numbers Using 2’s Complement : Fig. 6-2 If number is positive

» Magnitude = true binary form, Sign = 0 is placed in front of the MSB If number is negative

» Magnitude = 2’s complement form, Sign = 1 is placed in front of the MSB

2’s complement is the most commonly used system for representing signed binary numbers Perform the operation of subtraction by actually performing addition

» A digital computer can use the same circuitry to both add and subtract(saving in hardware)

Negation The operation of converting a positive number to its negative equivalent

or a negative number to its positive equivalent» 0 1 0 0 1 = + 9 Start with» 1 0 1 1 1 = - 9 Negate(2’s complement)» 0 1 0 0 1 = + 9 Negate again(2’s complement)

We negate a signed binary number by 2’s complementing it Sign extension : 8 bit example ( 5 bits → 8 bits )

Leading 0 plus: +9 0000 1001 , Leading 1 minus: -9 1111 0111

Sign 과Magnitude를동시에 2’s 보수취하는

것과 동일함



6-4

Special Case in 2’s Complement Representation : 4 bits Tab. 6-1 Smallest number(using N magnitude bits)

» 1 followed by N zeros : 1000 = - 8 ( -2N ) Largest number(using N magnitude bits)

» 0 followed by N ones : 0111 = +7 ( 2N -1 )

Exam. 6-3, 6-4, 6-5 6-3 2’s Complement Addition

Addition Rules 1) Simply add the two signed 2’s complement numbers 2) Disregard any carry from the sign bit.

» Examples : 9 + 4 = 01001 + 00100 = 01101 9 + ( -4 ) = 01001 + 11100 = 1 00101 ( -9 ) + 4 = 10111 + 00100 = 11011 ( -9 ) + ( -4 ) = 10111 + 11100 = 1 10011 9 + ( -9 ) = 01001 + 10111 = 1 00000

Discard Carry



6-5

6-4 2’s Complement Subtraction Subtraction Rules

1) Negate the subtrahend 2) Add this to the minuend 3) Discard carry

» Examples : results = 2’s comp. 9 - 4 = 9 + ( - 4 ) = 01001 + 11100 ( - 9 ) - 4 = ( - 9 ) + ( - 4 ) = 10111 + 11100 9 - 9 = 9 + ( - 9 ) = 01001 + 10111

Arithmetic Overflow Overflow Condition

» Two positive or two negative numbers are being added Overflow Detection

» Detected by observing the carry into the sign bit position and the carry out of the sign bit position

» If these two carries are not equal, an overflow condition is produced(Exclusive-OR gate = 1)

Number circle : Fig. 6-3

* Overflow Exam)out in out in

carries 0 1 carries 1 0+ 70 0 1000110 - 70 1 0111010+ 80 0 1010000 - 80 1 0110000

+ 150 1 0010110 - 150 0 1101010

Sign reverse

+9 0 1001 -4 1 1100 +5 1 0 0101

-9 1 0111 -4 1 1100 -13 1 1 0011



6-6

Fig. 6-3 : Number circle



6-7

6-5/6-6 Binary Multiplication/Division Use the same procedures as for decimal multiplication and division Exam)

6-7 BCD Addition BCD Addition Procedure

1) Add the BCD code by using ordinary binary addition 2) The sum is 9 or less, no correction is needed 3) The sum is greater than 9,

the 0110(6) should be added BCD Subtraction Procedure : not covered

Complement-then-Add (similar to 2’s comp.)

Multiplication: Division: 9÷3

1 0 0 1 0 0 1 11 0 1 1 1 1 1 0 0 11 0 0 1 0 1 1

1 0 0 1 0 0 1 10 0 0 0 0 1 1

1 0 0 1 01 1 0 0 0 1 1

shift (left) and add! shift (right) and subtract!

0 1 1 0 BCD for 6+ 0 1 1 1 BCD for 7

1 1 0 1 invalid sum0 1 1 0 add 6 for correction

0 0 0 1 0 0 1 1 BCD for 13



6-8

6-8 Hexadecimal Arithmetic Hex Addition : Exam. 6-6, 6-7, 6-8 Hex Subtraction : Exam. 6-9

1) The 2’s complement of the subtrahend will be taken, then added to the minuend

2) Any carry out of the MSD position will be disregarded Hex Representation of Signed Number : Tab. 6-2

Computer Numbering System = 2’s Complement System

6-9 Arithmetic Circuits ALU(Arithmetic/Logic Unit) : Fig. 6-4

All arithmetic operation take place in the ALU of a computer The purpose of the ALU :

» 1) Accept binary data that are stored in the memory» 2) Execute arithmetic and logic operations on these data (according to instruction from

the control unit) ALU contains at least two flip/flop registers : Accumulator(ACC or A), B register

» A : Operand 1 저장(중간 또는최종연산결과저장)» B : Operand 2 저장



6-9

Fig. 6-4 : ALU

Arithmetic/



6-10

A typical sequence of operation : A + B register 1) Control Unit은명령어에명시된 Operand 주소에따라메모리번지를지정한다. 2) 메모리로부터 Operand 데이터를 B register로전송 3) A 와 B 를더한후, 그결과를 A에저장 4) A는다른 Operand와다시더해질수있으며, 또는메모리에저장될수있다.

6-10 Parallel Binary Adder Typical binary addition : Fig. 6-5

Augend : A register, Addend : B register Parallel Adder : Fig. 6-6

The augend and addend are fed to a full adder(Sec. 6-11) The additions in each bit are taking place at the same time

6-11 Design of a Full Adder Truth Table for a Full Adder : Fig. 6-7

Complete Circuitry for a Full Adder : Fig. 6-8 K-Map Simplification : Fig. 6-9

ABACBCCCBAS

ININOUT

IN

][

Full Adder : 3 inputsHalf Adder : 2 inputs



6-11

6-12 Complete Parallel Adder with Registers : Fig. 6-10 Sequence of Operations : Exam) 1001(A) + 0101(B)

t1 : CLEAR (A = 0000) t2 : LOAD (B= 1001) [M] → [B] t3 : TRANSFER (A= 1001) [S] → [A] = [A] + [B] → [A] t4 : LOAD (B= 0101) [M] → [B] t5 : TRANSFER (A= 1110) [S] → [A] = [A] + [B] → [A]

Register Notation The contents of register A : The contents of the B register is transferred to the A register :

» the A register will be changed, and the B register will be unchanged

6-13 Carry Propagation Carry Propagation = Carry Ripple

The speed of parallel adder(Fig. 6-10) is limited by an effects called carry propagation or carry ripple

» Last position(MSB) will not reach its final value until after n FF propagation delays (for n bit adder)

A scheme for reducing this delay : Look-ahead Carry» Utilize logic gates to look at the lower-order bits of the augend and addend(to see if a

higher-order carry is to be generated)» Many IC adders use look-ahead carry

0000(A)+ 1001(B)

1001(A) + 0101(B)

1011][ A][][ AB

Carry Propagation is solved by more hardware circuitry



6-12

Fig. 6-10 : 4-bit adder with registers



6-13

Carry Look-ahead Adder Sum : S

Carry : C

Substitute : P 및 G 미리계산 (A 및 B는기지수)

Final results : 하드웨어로구현

1 iiii CBAS

1 iiiiii CBABAC

1 iii CPS

1 iiii CPGC

iii BAP

iii BAG



6-14

6-14 IC Parallel Adder 7483/74283 : Fig. 6-11(a) Cascading Parallel Adders : Fig. 6-11(b) Exam. 6-10) Determine the inputs/outputs when 72 is added to 137 in Fig. 6-11

6-15 2’s Complement System Addition : Fig. 6-12

+6 ( 0110 ) + -3 ( 1101 ) = +3 ( 0011 ) + 0(Co) Subtraction : Fig. 6-13

4 ( 0100 ) - 6 ( 0110 ) = 4 ( 0100 ) + -6 (2’s complement of +6)= 0100 + 1001(1’s complement of +6) + 1(Co) = 1110 ( -2 )

Combined Addition and Subtraction : Fig. 6-14 ADD = 1, SUB = 0

» Enable : AND gate 1,3,5,7 Disable : AND gate 2,4,6,8 ADD = 0, SUB = 1

» Enable : AND gate 2,4,6,8 Disable : AND gate 1,3,5,7 Co = 1 = SUB

* 차이점83 : GND= 12 , Vcc= 5283 : GND= 8 , Vcc= 16

B 입력



6-15

Fig. 6-14 : Parallel adder/subtractor using the 2’s complement system



6-16

6-17 ALU IC 74382 : Fig. 6-15

Exam. 6-11 Expanding the ALU : Fig. 6-16

Exam. 6-12 Other ALU : 74181

16 operations : ,...1,)(,)(,)(,,1,,1,1

,)(,,1,

AABAABAABBAABAABABAABBABABABAABABA

Fig. 6-15 : (a) Block symbol for 74LS382 ALU chip (b) Function Table



6-17

6-17 Troubleshooting Case Study Test Results

Mode 1 : ADD = 0, SUB = 0» Result : Sum = A + 1 ( 정상 : Sum = A + 0 = A )

Mode 2 (add) : ADD = 1, SUB = 0» Result : Sum = A + B + 1 ( 정상 : Sum = A + B )

Mode 3 (sub) : ADD = 0, SUB = 1» Result : Sum = A - B ( 이상없음 )

Possible Faults 1) LSB 가항상 1 : Mode 3에서정상임으로배제 2) Co = 1 : SUB와 Co 사이에 Open = HIGH Input = 1

Exam. 6-13) Describe the effects of a break in between SUB and AND(X) gate in Fig. 6-17

Mode 1 : A + B (Co = 0, SUB= 1) Mode 2 : A + B + B = A + 1111 = A – 1 (Co = 0, SUB= 1, ADD= 1)

Mode 3 : A - B, 이상없음1 OR 0 = 10 OR 1 = 1



6-18

x

Fig. 6-17 : Parallel Adder / Subtractor

Exam. 6-13



6-19

6-18. Using Altera Library Functions Adder and ALU can be described using HDL macrofuntion/megafunction1. Altera offers pre-defined logic circuits in macrofunction library.

Altera provides some good documentation through the HELP menu for macrofunction.

The documentation tells us what the macrofunction is, what it does, and the names of the inputs and outputs.

Example : 8-bit ALU using 74382 Function - Fig. 6-18

2. Megafunction LPMs for Arithmetic Circuits 8-bit Parallel Adder :

» 74283 macrofunction : Fig. 6-19(a)» LPM megafunction : Fig. 6-19(b)

4-bit Multiplier : Section 6-5» 7408 macrofunction : Fig. 6-20(a) Partial Product + Fig. 6-20(b) Adder» LPM megafunction : Fig. 6-20(d)» Simulation Results : Fig. 6-20(c)

4-bit Binary up Counter : Fig. 6-21

FUNCTION 74382 (sumout[7..0], Ain[7..0], Bin[7..0], caryin)



6-20

Exam. 6-14) Create a mod-8 down counter using LPM blocks. 3-bit down counter : Fig. 6-22(a)

» “subtracter” is used instead of “adder” : always -1

6-19 Logical Operations on Bit Arrays with HDLs Register (Array) Logical Operation : Exam. 6-15 and Exam. 6-16

4-bit array signal d:» AHDL – VARIABLE d[3..0] : NODE» VHDL – SIGNAL d : BIT_VECTOR (3 DOWNTO 0)

Exam. 6-15) What is the value of Y after Y = D G 4-bit array for AND operation

Exam. 6-16) Declare each d, g, and y. Then write an expression using your favorite HDL



6-21

6-20. HDL Adders AHDL 8-bit Adder : Fig. 6-23 VHDL 8-bit Adder : Fig. 6-24

6-21 Parameterizing the Bit Capacity of a Circuit To expand the bit capacity of circuit

1. Stage cascade 2. Keyword CONSTANT 1. The VHDL generate [GENERATE] statement can be used to concisely replicate several components that are cascaded [casc] together.

1- bit full adder GENERATE statement 8-bit full adder

2. Constants are fixed numbers that is used in the code to refer to the value.* AHDL n-bit adder/subtractor : Fig. 6-25.

Keyword CONSTANT is followed by the symbolic name and value assigned.* VHDL n-bit adder/subtractor : Fig. 6-26.

Within the package the keyword CONSTANT is followed by the symbolic name, type, and the value to be assigned.

chap. 6 digital arithmetic: operations & circuitsmicrocom.koreatech.ac.kr/course...

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