*Crowley OS Chap. 2*The Hardware InterfaceChapter 2

Crowley OS Chap. 2

*Crowley OS Chap. 2*Key concepts in chapter 2General and special-purpose registersProcessor modes: user and systemMemory addressingphysical (or absolute) addresses and address spacelogical addresses and address spaceI/O address spaceInterruptsI/O devices and memory-mapped I/O

Crowley OS Chap. 2

*Crowley OS Chap. 2*CRA-1 organization

Crowley OS Chap. 2

*Crowley OS Chap. 2*General-purpose registers32 general registers, each 32 bits longr0: always 0r1: return values of functionsr8, r9, r10, r11: function parametersr29: frame pointerr30: stack pointerr31: return address for function call instruction

Crowley OS Chap. 2

*Crowley OS Chap. 2*Control registersia: address of the next instruction to executepsw: program status word, processor statebase: memory-mapping base registerbound: memory-mapping bound registeriia: saves ia during an interruptipsw: saves psw during an interruptip: saves interrupt-specific dataiva: address of the interrupt vector areatimer: interval timer

Crowley OS Chap. 2

*Crowley OS Chap. 2*Processor modespsw bit 0: 1 if system mode, 0 if user modeUser modea user program is runningcertain instructions are not allowedmemory mapping (base and bound) is enabledSystem modethe operating system is runningall instructions are allowedmemory mapping (base and bound) is disabled

Crowley OS Chap. 2

*Crowley OS Chap. 2*Instruction set of the CRA-1Load and store register (including control registers when in system mode)Load and store all register (for saving state)Move register to registerSystem callReturn from interruptPlus many others not relevant here

Crowley OS Chap. 2

*Crowley OS Chap. 2*CRA-1 memory and addressing32-bit physical (a.k.a. absolute) addresses8-bit bytesphysical address space: 0 to 0xFFFFFFFFmemory address space: 0 to 0xEFFFFFFFI/O address space: 0xF0000000-0xFFFFFFFF32-bit logical addresses mapped by base and bound registersdefines a logical address space

Crowley OS Chap. 2

*Crowley OS Chap. 2*InterruptsSystem call: program executed a syscallTimer: timer register went from 1 to 0a non-zero timer counts down every microsecondDisk: a disk operation completedProgram errorip=0: undefined instructionip=1: illegal instruction in user modeip=2: logical address >= bound register

Crowley OS Chap. 2

*Crowley OS Chap. 2*Interrupt processingSteps in handling an interruptpsw saved in ipsw, psw set to 0interrupt parameter (if any) placed in ip registeria saved in iianew is taken from interrupt vector area (offset depends on which interrupt it is)timer and disk interrupt can be masked (recorded but delayed) by setting psw bit 0

Crowley OS Chap. 2

*Crowley OS Chap. 2*CRA-1 I/O devicesMemory-mapped I/Odevice registers are in the physical address spaceDisk controller and disk4 Kbyte disk blocks20 bit disk block numbers

Crowley OS Chap. 2

*Crowley OS Chap. 2*Disk controller informationconst int BlockSize = 4096; enum disk_command {LoadBlock=0, StoreBlock=1}; struct disk_control_reg { unsigned int command : 1; unsigned int interrupt_enabled : 1; unsigned int disk_block : 20; unsigned int padding : 10; }; volatile disk_control_reg *Disk_control = (disk_control_reg *)0xF0000000; void **Disk_memory_addr = (void **)0xF0000004; enum disk_status { DiskIdle=0, DiskBusy=1 }; struct disk_status_reg { unsigned int busy : 1; unsigned int padding : 31; }; disk_status_reg *Disk_status = (disk_status_reg *)0xF0000008;

Crowley OS Chap. 2

*Crowley OS Chap. 2*Simple OS code and simulatorsCRA-1 Simple OScode in the book, but there is no simulatorMIPS Simple OScode in distribution, runs on UNIX systemsa number of changes in the low-level code that interfaces to the hardwareJava Simple OScode in distribution, runs on Java 1.1 systems and Java 1.1 browsersa number of changes in the low-level code that interfaces to the hardware

Crowley OS Chap. 2

*Crowley OS Chap. 2*MIPS Hardware InterfaceTBD

Crowley OS Chap. 2

*Crowley OS Chap. 2*Java Hardware InterfaceTBD

Crowley OS Chap. 2