VLSI DesignLecture 5: Logic GatesMohammad Arjomand

CE DepartmentSharif Univ. of Tech.

Adapted with modifications from Wayne Wolfs lecture notes

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

TopicsCombinational logic functions.Static complementary logic gate structures.

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Combinational logic expressionsCombinational logic: function value is a combination of function arguments.A logic gate implements a particular logic function.Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Gate designWhy designing gates for logic functions is non-trivial:may not have logic gates in the libray for all logic expressions;a logic expression may map into gates that consume a lot of area, delay, or power.

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Boolean algebra terminologyFunction:

f = ab + aba is a variable; a and a are literals.ab is a term.A function is irredundant if no literal can be removed without changing its truth value.

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

CompletenessA set of functions f1, f2, ... is complete iff every Boolean function can be generated by a combination of the functions.NAND is a complete set; NOR is a complete set; {AND, OR} is not complete.Transmission gates are not complete.If your set of logic gates is not complete, you cant design arbitrary logic.

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Static complementary gatesComplementary: have complementary pullup (p-type) and pulldown (n-type) networks.Static: do not rely on stored charge.Simple, effective, reliable; hence ubiquitous.

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Static complementary gate structurePullup and pulldown networks:pullupnetworkpulldownnetworkVDDVSSoutinputs

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Inverter

aout+

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Inverter layout(tubs notshown)

aout+aout

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

NAND gate

+baout

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

NAND layout

+baoutbaout

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

NOR gate

+baout

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

NOR layout

baout

about

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

AOI/OAI gatesAOI = and/or/invert; OAI = or/and/invert.Implement larger functions.Pullup and pulldown networks are compact: smaller area, higher speed than NAND/NOR network equivalents.AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

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AOI exampleout = [ab+c]:symbolcircuitandorinvert

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Pullup/pulldown network designPullup and pulldown networks are duals.To design one gate, first design one network, then compute dual to get other network.Example: design network which pulls down when output should be 0, then find dual to get pullup network.

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Dual network construction

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Logic levelsSolid logic 0/1 defined by VSS/VDD. Inner bounds of logic values VL/VH are not directly determined by circuit properties, as in some other logic families.

logic 1logic 0unknownVDDVSSVHVL

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Logic level matchingLevels at output of one gate must be sufficient to drive next gate.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Transfer characteristicsTransfer curve shows static input/output relationshiphold input voltage, measure output voltage.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Inverter transfer curve

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Logic thresholdsChoose threshold voltages at points where slope of transfer curve = -1.Inverter has a high gain between VIL and VIH points, low gain at outer regions of transfer curve.Note that logic 0 and 1 regions are not equal sizedin this case, high pullup resistance leads to smaller logic 1 range.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Noise marginNoise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output.In static gates, t= voltages are VDD and VSS, so noise margins are VDD-VIH and VIL-VSS.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

CMOS Inverter: Transfer characteristic (Review)A: N: off P: linear B: N: saturated P: linearC: N: saturated P: saturated D: N: linear P: saturatedE: N: linear P: off

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Device Models (Review)*

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Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

DelayAssume ideal input (step), RC load.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Delay assumptionsAssume that only one transistor is on at a time. This gives two cases:

rise time, pullup on;fall time, pullup off.Assume resistor model for transistor. Ignores saturation region and mischaracterizes linear region, but results are acceptable.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Current through transistorTransistor starts in saturation region, then moves to linear region.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Capacitive loadMost capacitance comes from the next gate.Load is measured or analyzed by Spice.Cl: load presented by one minimum-size transistor.

CL = S (W/L)i Cl

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Resistive model for transistorAverage V/I at two voltages:

maximum output voltagemiddle of linear regionVoltage is Vds, current is given Id at that drain voltage. Step input means that Vgs = VDD always.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Resistive approximation

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Ways of measuring gate delayDelay: time required for gates output to reach 50% of final value.Transition time: time required for gates output to reach 10% (logic 0) or 90% (logic 1) of final value.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Inverter delay circuitLoad is resistor + capacitor, driver is resistor.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Inverter delay with t modelt model: gate delay based on RC time constant t.Vout(t) = VDD exp{-t/(Rn+RL)/ CL}tf = 2.2 R CLFor pullup time, use pullup resistance.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

t model inverter delay 0.5 micron process:

Rn = 6.47 kWCl = 0.89 fFCL = 1.78 fFSo

td = 0.69 x 6.47E3 x 1.78E-15 = 7.8 ps.tf = 2.2 x 6.47E3 x 1.78E-15 = 26.4 ps.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Quality of RC approximation

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Power consumption analysisAlmost all power consumption comes from switching behavior.Static power dissipation comes from leakage currents.Surprising result: power consumption is independent of the sizes of the pullups and pulldowns.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Other modelsCurrent source model (used in power/delay studies):

tf = CL (VDD-VSS)/Id = CL (VDD-VSS)/0.5 k (W/L) (VDD-VSS -Vt)2Fitted model: fit curve to measured circuit characteristics.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Power consumption circuitInput is square wave.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Power consumptionA single cycle requires one charge and one discharge of capacitor: E = CL(VDD - VSS)2 .Clock frequency f = 1/t.Energy E = CL(VDD - VSS)2.Power = E x f = f CL(VDD - VSS)2.

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Observations on power consumptionResistance of pullup/pulldown drops out of energy calculation.Power consumption depends on operating frequency.

Slower-running circuits use less power (but not less energy to perform the same computation).

Modern VLSI Design 4e: Chapter 3Copyright 2008 Wayne Wolf

Speed-power productAlso known as power-delay product.Helps measure quality of a logic family.For static CMOS:

SP = P/f = CV2.Static CMOS speed-power product is independent of operating frequency.

Voltage scaling depends on this fact.

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