chapter 04 tutorial using statecad. objective this tutorial will give you exposure to using statecad...
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Chapter 04Tutorial Using StateCAD
Objective
This tutorial will give you exposure to using StateCAD and VHDL
Using HDL Bencher and Modelsim for simulating the functional design
This tutorial shows you how to create, using StateCAD and VHDL, a simple sequence generator
Sequence Generator State Table
Current State
Next State
Output
M A B A B DOUT<1>
DOUT<0>
0 0 0 1 0 1 0
0 0 1 1 1 1 1
0 1 0 0 1 0 1
0 1 1 0 0 0 0
1 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 0 0 0 0
Sequence Generator State Diagram
Create a New Project
Enter a Name and Location for the Project
Select the Device and Design Flow for the Project
Create a New Source
Select State Diagram and Enter File Name
New Source Information
New Source Information
Next Step
Finish
Create a Blank StateCAD
State Machine Wizard: Draw State Machines
Select the Appearance of the State Machine
Reset the State Machine
Setup Transitions
Placed Template State Diagram
Edit Conditions in the transition arrow State0State1
Left-Click
Output Wizard
Enter Constraint Value
Completed Transition
Modified State Diagram
Insert a New Transition
Enter Constraint Value
State2State1
Final State Diagram
Generate HDL
Optimize Outputs for Speed
Result Windows
StateCAD HDL
Create Test Bench (State Bench)
State Bench
Reset
Input CLK
Review Sequence Generator State Table
Current State
Next State
Output
M A B A B DOUT<1>
DOUT<0>
0 0 0 1 0 1 0
0 0 1 1 1 1 1
0 1 0 0 1 0 1
0 1 1 0 0 0 0
1 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 0 0 0 0
Summary Sequence Generator State Table
M=0, then State 02130…… M=1, then State 01 0…… , State 20, and State 30.
Check M=0 Then DOUT 0,2,1,3(State 0,2,1,3)
Check M=1 Then DOUT 0, 1(State 0,1)
Check M=1 Then State2 State0 and State3State0
Questions and Answers