chapter 1 – computer systems. byu cs 345os overview (chapter 1)2 cs 345 stalling’s...

Chapter 1 – Computer Systems

BYU CS 345 OS Overview (Chapter 1) 2

CS 345

Stalling’s Chapter # Project

1: Computer System Overview2: Operating System Overview

4 P1: Shell

3: Process Description and Control4: Threads

4 P2: Tasking

5: Concurrency: ME and Synchronization6: Concurrency: Deadlock and Starvation

6 P3: Jurassic Park

7: Memory Management8: Virtual memory

6 P4: Virtual Memory

9: Uniprocessor Scheduling10: Multiprocessor and Real-Time Scheduling

6 P5: Scheduling

11: I/O Management and Disk Scheduling12: File Management

8 P6: FAT

Student Presentations 6

OS Overview (Chapter 1) 3

Learning Objectives

Describe the basic elements of a computer system and their interrelationship.

Explain the steps taken by a processor to execute an instruction. Understand the concept of interrupts and how and why a processor

uses interrupts List and describe the levels of a typical computer memory

hierarchy. Explain the basic characteristics of multiprocessor and multicore

organization. Discuss the concept of locality and analyze the performance of a

multilevel memory hierarchy. Understand the operation of a stack and its use to support

procedure call and return.

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Quiz: Define the following terms

Kernel

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Systems program

Applications program

Middleware

Firmware

Bootstrap program

Daemon

Device driver

Asymmetric multiprocessing

Symmetric multiprocessing


Operating System Tradeoffs

Convenience vs efficiency Ease of use vs maximum resource utilization Interactive user interface vs no user view Asymmetric vs symmetric processing Single-processor vs multiprocessor systems Unicore vs multicore systems UMA vs NUMA Batch vs time sharing Logical vs physical memory Dual mode vs multimode

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Learning Objectives


Explain the steps taken by a processor to execute an instruction.

Understand the concept of interrupts and how and why a processor uses interrupts

List and describe the levels of a typical computer memory hierarchy.

Explain the basic characteristics of multiprocessor and multicore organization.

Discuss the concept of locality and analyze the performance of a multilevel memory hierarchy.

Understand the operation of a stack and its use to support procedure call and return.

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OS Overview (Chapter 1) 7BYU CS 345

Processor Registers

User-visible registers May be referenced by machine language Available to all programs - application programs and system

programs Data Registers – can be changed by user Address Registers – could be separate from data register Stack Registers – user / supervisor stacks Condition Codes – results of operations

Control and status registers May or may not be visible

Program Counter (PC) – address of next instruction Instruction Register (IR) – most recently fetched instruction MAR/MBR – memory reference registers Program Status Word (PSW) – condition codes, interrupts, mode

Registers


CPURegisters


Instruction ExecutionRegisters


Learning Objectives


Explain the steps taken by a processor to execute an instruction. Understand the concept of interrupts and how and

why a processor uses interrupts List and describe the levels of a typical computer memory





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12

Main Routine(synchronous)

Interrupt Service Routines

BYU CS 345 OS Overview (Chapter 1)

Interrupt Service Routine

Interrupt


(asynchronous)



(asynchronous)



(asynchronous)



Interrupts

The interrupt was the principle tool available to system programmers in developing multi-tasking systems!

Classes of Interrupts Program: arithmetic overflow, division by zero Execute illegal instruction Reference outside user’s memory space I/O: Timer, DMA Hardware failure

Interrupt control Disable during ISR Enable upon exiting Allow Interrupts? Priorities?


Learning Objectives



uses interrupts List and describe the levels of a typical computer

memory hierarchy. Explain the basic characteristics of multiprocessor and multicore




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Storage Performance

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Level 1

Name Registers

Typical Size < 1KB

ImplementationTechnology

Custom memory

w/multiple ports CMOS

Access time (ns) 0.25-0.5

Bandwidth (MB/sec) 20,000-100,000

Managed by Compiler

Backed by Cache


Storage Performance

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Level 1 2

Name Registers Cache

Typical Size < 1KB < 16MB


Custom memory


On-chip CMOS RAM

Access time (ns) 0.25-0.5 0.5-25


5,000-10,000

Managed by Compiler Hardware

Backed by Cache Main


Storage Performance

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Level 1 2 3

Name Registers CacheMain

memory

Typical Size < 1KB < 16MB <64GB


Custom memory


On-chip CMOS RAM

CMOS SRAM

Access time (ns) 0.25-0.5 0.5-25 80-250


5,000-10,000

1,000-5,000

Managed by Compiler Hardware OS

Backed by Cache Main Disk


Storage Performance

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Level 1 2 3 4


memorySolid state

disk

Typical Size < 1KB < 16MB <64GB <1TB


Custom memory


On-chip CMOS RAM

CMOS SRAM

Flash

Access time (ns) 0.25-0.5 0.5-25 80-25025,000-50,000


5,000-10,000

1,000-5,000

500

Managed by Compiler Hardware OS OS

Backed by Cache Main Disk Disk


Storage Performance

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Level 1 2 3 4 5


memorySolid state

diskHard disk

Typical Size < 1KB < 16MB <64GB <1TB <10TB


Custom memory


On-chip CMOS RAM

CMOS SRAM

Flash Hard disk

Access time (ns) 0.25-0.5 0.5-25 80-25025,000-50,000

5,000,000


5,000-10,000

1,000-5,000

500 20-50

Managed by Compiler Hardware OS OS OS

Backed by Cache Main Disk DiskDisk or

tape


Learning Objectives




hierarchy. Explain the basic characteristics of multiprocessor

and multicore organization. Discuss the concept of locality and analyze the performance of a



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Cluster computing Loosely coupled - network Client / server environment Middleware DME, RPC

Multi (processor/core)

Traditionally, the computer has been viewed as a sequential machine.

Multiple control signals Pipelining

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Parallelism Symmetric Multiprocessors (SMP)

2 or more identical processors that share resources Integrated OS to control jobs, tasks, files, data elements… High degree of interaction/cooperation between processes

Multicore Computers Single piece of silicon (die) Independent processors + levels of cache Intel Core i7 Prefetching


Learning Objectives





organization. Discuss the concept of locality and analyze the

performance of a multilevel memory hierarchy. Understand the operation of a stack and its use to support


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Given: Processor speed is faster than memory speed Execution/data localizes

Processor Cache: Contains a portion of main memory Invisible to operating system Used similar to virtual memory Increases the speed of memory

Processor first checks cache - If not found in cache, the block of memory containing the needed information is moved to the cache

Disk cache, I/O cache, VM cache,…

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Two-Level Memory

Locality Spatial locality – clustered access

Large cache Pre-fetch

Temporal locality – recent/repeated access Cache Least Recently Used (LRU) Cache hierarchy

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Learning Objectives






multilevel memory hierarchy. Understand the operation of a stack and its use to

support procedure call and return.

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The Call / Return Mechanism

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Subroutines

Smaller programs.Easier to maintain.Reduces development costs.Increased reliability.Fewer bugs do to copying code.More library friendly.

Faster programs.Less overhead.

Summary…


What is an O.S.?

Not always a clear definition as to what constitutes an O.S. and what is an application

CD-Rom Driver Scandisk Internet Explorer

Intermediary between the hardware and the users Allocate resources (CPU, Memory, disk space, etc.) between

programs and users efficiently Allow the user to conveniently access data and programs Protect the system from incorrect or malicious programs and

users

Summary


Hardware Review

Elements of a system:· Processor

Registers (address, data, control) Instruction cycle (fetch, decode, execute) Interrupts Usually includes hardware and special instructions to help

the O.S. manage memory, devices, etc.· Memory

Different levels (cache, main memory, disk) Operating system will generally manage memory (both

RAM and disk), and move data back and forth as required· I/O

Usually use Interrupts, DMA Operating system usually controls use of I/O devices

Summary


Registers

Used for frequently accessed items User-Visible registers – Available to the programmer and

compiler Data Registers Address Registers (Index, Segment, Stack Pointer) Condition code/flags

Control and Status registers – Used to control the processor

Program Counter/Instruction Pointer Memory address/data Processor Status Word Debugging registers Temp registers Memory Management registers

Summary


Interrupts

Interrupts Allow I/O devices to get the CPUs attention at regular

intervals (Program, Timer, I/O, Hardware failure) Helps the O.S. by reducing the time spent monitoring

I/O devices CPU checks for interrupts after each instruction, starts

the handler if needed May allow nested interrupts

I/O techniques Programmed I/O Interrupt-Driven I/O Direct Memory Access

Summary


Interrupts and I/O

Handling and Interrupts: Figure 1.10 (pg 23) Device sends interrupt request to CPU CPU finishes current instruction CPU acknowledges request CPU saves PC and PSW CPU loads PC with the address of the first instruction in the

interrupt handler (may get help from interrupt request) Interrupt handler starts, often saves other CPU registers and key

values Interrupt handler responds to the device Interrupt handler restores CPU registers and key values CPU restores PC and PSW and resumes previous program

Summary


Memory

Varying types of memory Registers, Cache, RAM, Disk, CD Vary in speed, size, cost CPU and O.S. try to keep frequently used data in faster memory

Cache – Use a small high-speed memory to improve the apparent speed of a larger low-speed memory

Keep track of what is currently being used, load into high-speed memory

Replacement Algorithm – What do we get rid of when we run out of memory?

Write Policy – How do we respond to modifications?

Summary

chapter 1 – computer systems. byu cs 345os overview (chapter 1)2 cs 345 stalling’s...

Documents

os overview chapter

computer systems chapter

stallings chapter

computer system overview2

following termskernelbyu

multilevel memory hierarchy

memory management8

concept of interrupts