chapter 1 introduction · computer intensive digital signal processing tasks. dsp advantages...
TRANSCRIPT
Introduction:
What Is DSP?
Digital
Operating by the use of discrete signals to represent data in the form of numbers
Signal
A variable parameter by which information is conveyed through an electronic circuit
Processing
To perform operations on data according to programmed instructions
Digital Signal processing Changing or analyzing information, which is, measured as discrete sequences of numbers. DSPs are a high-speed single chip microprocessor or microcomputer designed to perform computer intensive digital signal processing tasks.
DSP ADVANTAGES Advantages
The big advantage of DSP lies in the programmability of the processor, allowing parameters to be easily changed.
Versatility Digital systems can be reprogrammed for other applications (at least where programmable
DSP chips are used).
Digital systems can be ported to different hardware (for example a different DSP chip or
board level product).
Repeatability
Digital systems can be easily duplicated.
Digital systems do not depend on strict component tolerances.
Digital system responses do not drift with temperature.
Simplicity Some things can be done more easily digitally than with analogue systems. Advantages of designing with DSP over other architectures
Multiple multiply-accumulate operations per cycles. Real time performance, simulation and emulation. Flexibility Reliability Increased system performance and reduced system cost
Advantages related to current uses of the DSP
When you talk on the cell phone, DSP noise cancellation eliminates the echo effect. It also means the voice you hear is very clear - no hum or static in the background.
The Internet runs faster, as DSPs at both ends of the wire process information at blistering speeds.
Videoconference calls will have full-motion video, instead of people moving like puppets.
The storage capacity of a hard disk drive has more than tripled in the last 18 months. The capacity of a single 3.5" disk platter is now more than 2 gigabytes (GB) compared to 540MB in 1996.
Read/write electronics featuring TI DSPs, and DSPS solutions, enable hard disk drive designers to store more information with higher levels of drive performance-greater bit density/capacity, higher data rates and faster access times.
Entertainment is just now starting to go digital and this will drive huge DSP demand in the next decade.
Motors controlled by DSP will be more efficient, reducing the number of mechanical parts and lowering the energy consumption in a huge variety of applications - home appliances, automobiles, and industrial and commercial motors. Only a small percentage of motors today use electronic motor controls - this represents a huge market opportunity for DSPs (an estimated 1.4 billion motors will be manufactured in the year 2001).
In health care, DSP solutions can enhance sight and hearing capabilities for those with disabilities.
COMPARISION BETWEEN DSPS & MICROCONTROLLER
Difference Between Microcontrollers And DSPs
Microcontrollers and Digital Signal Processors (DSPs) are the main engines of the deeply embedded development world.
A MICROCONTROLLER is a highly integrated chip which includes, on one chip, all or most of the parts needed for a controller, is used to control some process or aspect of the environment. The microcontroller could be called a "one-chip solution".
DSPs are a high-speed single chip microprocessor or microcomputer designed to perform computer intensive digital signal processing tasks.
Microcontrollers are primarily used in control-oriented applications that are interrupt-driven, sensing and controlling external events.
DSPs, meanwhile, are traditionally found in systems that require the precision processing of analog signals.
Microcontrollers are inexpensive, small, and flexible. DSP is larger, more expensive, and more specialized.
Introduction to TMS320C6748: The TMS320C6748 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance. For security-enabled devices, TI‟s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust”, the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects customers‟ IP and lets them securely set up the system and begin device operation with known, trusted code. Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16
serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller. The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces. The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps). The uPP provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters. A video port interface (VPIF) is included providing a flexible video I/O port. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
Features: 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP C674x Instruction Set Features
o Superset of the C67x+ and C64x+ ISAs o Up to 3648 MIPS and 2746 MFLOPS o Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) o 8-Bit Overflow Protection o Bit-Field Extract, Set, Clear o Normalization, Saturation, Bit-Counting o Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture o 32KB of L1P Program RAM/Cache o 32KB of L1D Data RAM/Cache o 256KB of L2 Unified Mapped RAM/Cache o Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3): o 2 Channel Controllers o 3 Transfer Controllers o 64 Independent DMA Channels o 16 Quick DMA Channels o Programmable Transfer Burst Size
TMS320C674x Floating-Point VLIW DSP Core o Load-Store Architecture with Nonaligned Support o 64 General-Purpose Registers (32-Bit) o Six ALU (32- and 40-Bit) Functional Units
Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
o Two Multiply Functional Units: Mixed-Precision IEEE Floating-Point Multiply Supported up to:
2 SP x SP → SP Per Clock 2 SP x SP → DP Every Two Clocks 2 SP x DP → DP Every Three Clocks 2 DP x DP → DP Every Four Clocks
Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
o Instruction Packing Reduces Code Size o All Instructions Conditional o Hardware Support for Modulo Loop Operation o Protected Mode Operation o Exceptions Support for Error Detection and Program Redirection
Software Support o TI DSPBIOS o Chip Support Library and DSP Library
128KB of RAM Shared Memory 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
Two External Memory Interfaces: o EMIFA
NOR (8- or 16-Bit-Wide Data) NAND (8- or 16-Bit-Wide Data) 16-Bit SDRAM with 128-MB Address Space
o DDR2/Mobile DDR Memory Controller with one of the following: 16-Bit DDR2 SDRAM with 256-MB Address Space 16-Bit mDDR SDRAM with 256-MB Address Space
Three Configurable 16550-Type UART Modules: o With Modem Control Signals o 16-Byte FIFO o 16x or 13x Oversampling Option
LCD Controller Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO)
Interfaces Two Master and Slave Inter-Integrated Circuits
(I2C Bus) One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High
Bandwidth Programmable Real-Time Unit Subsystem (PRUSS)
o Two Independent Programmable Real-Time Unit (PRU) Cores 32-Bit Load-Store RISC Architecture 4KB of Instruction RAM Per Core 512 Bytes of Data RAM Per Core PRUSS can be Disabled via Software to Save Power Register 30 of Each PRU is Exported From the Subsystem in Addition to the
Normal R31 Output of the PRU Cores. o Standard Power-Management Mechanism
Clock Gating Entire Subsystem Under a Single PSC Clock Gating Domain
o Dedicated Interrupt Controller o Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1) USB 2.0 OTG Port with Integrated PHY (USB0)
o USB 2.0 High- and Full-Speed Client o USB 2.0 High-, Full-, and Low-Speed Host o End Point 0 (Control) o End Points 1,2,3,4 (Control, Bulk, Interrupt, or ISOC) RX and TX
One Multichannel Audio Serial Port (McASP): o Two Clock Zones and 16 Serial Data Pins o Supports TDM, I2S, and Similar Formats o DIT-Capable o FIFO Buffers for Transmit and Receive
Two Multichannel Buffered Serial Ports (McBSPs): o Supports TDM, I2S, and Similar Formats o AC97 Audio Codec Interface o Telecom Interfaces (ST-Bus, H100) o 128-Channel TDM o FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
o IEEE 802.3 Compliant o MII Media-Independent Interface o RMII Reduced Media-Independent Interface o Management Data I/O (MDIO) Module
Video Port Interface (VPIF): o Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture
Channels o Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
Universal Parallel Port (uPP): o High-Speed Parallel Interface to FPGAs and Data Converters o Data Width on Both Channels is 8- to 16-Bit Inclusive o Single-Data Rate or Dual-Data Rate Transfers o Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
Serial ATA (SATA) Controller: o Supports SATA I (1.5 Gbps) and SATA II
(3.0 Gbps) o Supports All SATA Power-Management Features o Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries o Supports Port Multiplier and Command-Based Switching
Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-
Purpose Timers) Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
o Dedicated 16-Bit Time-Base Counter with Period and Frequency Control o 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric
Outputs o Dead-Band Generation o PWM Chopping by High-Frequency Carrier o Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules: o Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM)
Outputs o Single-Shot Capture of up to Four Event Time-Stamps
Packages: o 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch o 361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch Commercial, Extended, or Industrial Temperature
TMS320C6748 DSP Block Diagram:
Device Compatibility The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both the C64x+ and C67x+ DSP families
DSP Subsystem: The DSP Subsystem includes the following features: • C674x DSP CPU • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 256KB Unified Mapped RAM/Cache (L2) • Boot ROM (cannot be used for application code) • Little endian DSP TMS320C6748 Mega Module Block Diagram:
TMS320C674x Mega Module: The C674x Mega module consists of the following components: • TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)
Device Nomenclature: To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6745). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications.TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device.Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following Disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default).
About This Manual
This document describes board level operations of the EPB_C6748 based on the Texas
Instruments TMS320C6748 DSP
The EPB_C6748 is a stand-alone module permitting engineers and software developer‟s
evaluation of certain characteristics of the TMS320C6748 DSP to determine processor
applicability to design requirements. Evaluators can create software to execute onboard or
expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The “Educational Practice Board C6748” will sometimes be referred to as the “EPB_C6748”.
Information about Cautions
This Technical Reference Manual may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
hardware, or other equipment. The information in a caution is provided for your protection.
Please read each caution carefully.
Introduction to the EPB_C6748
This chapter provides a description of the EPB_C6748 for the TMS320C6748 DSP, key
features, and block diagram of the circuit board
Topic
1.0 Overview of the EPB_C6748
1.1 Key Features of the EPB_C6748
1.1.1 Hardware Features
1.1.2 Software Features
1.2 Functional Overview of the EPB_C6748
1.0 Overview of the EPB_C6748
The EPB_C6748 is a stand-alone card--allowing developers to evaluate the TMS320C6748
DSP to determine if it meets their Application requirements. Furthermore, the module is an
excellent platform to develop and run software for the TMS320C6748 DSP.
The EPB_C6748 is shipped with a TMS320C6748 DSP. The EPB_C6748 allows full speed
verification of C6748 code.
To simplify code development and shorten debugging time, a C6000 Code Composer Studio
driver is provided. In addition, an onboard JTAG connector provides interface to emulators,
with assembly language and „C‟ high level language debug.
1.1 Key Features of the EPB_C6748
1.1.1 Hardware Features
Mechanical Parameters
Size: 160mm x 136mm
Input Voltage - 5V DC
Processor
TMS320C6748 – Fixed/ Floating Point Digital Signal Processor
DSP with up to 375/456 MHz performance.
On board 14 Pin (2x7 Pin) JTAG emulation connector
Boot mode selection switch
Memory
On board 256 MB Flash memory
On board 128 MB DDR2 RAM memory
Data Transfer Interfaces
On board DB9 connector for UART-1 interface
On board 3 pin header for UART-2 interface
On board USB TYPE B Connector for UART-2 interface for Debug Console
LED indication for USB connection for Debug Console
On board Reset Switch with LED indication
On board USB Type A Connector for USB host interface
On board micro USB Type A Connector for USB OTG interface
On board RJ45 connector for 10/100 Ethernet interface
On board I2C based Temperature sensor
On board I2C based RTC interface with battery backup
On board SPI based micro SD card interface
On board SATA connector
Input/Output Interfaces and other Facilities
On board Power-On LED indication
On board 4 User LED at GPIO Pin as GPIO Test point
On board 5 user push buttons for various applications
Special functionality
Boot mode selection switch
On board Video in port available
On board VGA out connector
On board composite video out connector
On board Graphics LCD interface connector
On board audio jack and speaker (Mic in) interface
On board audio codec for speaker out
On board CMOS sensor connector to interface CMOS camera
On board Temperature sensor with interrupt out facility
On board jumper selection to switch various video out options
On board LED to indicate power surge
On board LED to indicate high voltage input
On board excessive voltage protection circuit with LED indication
Various test points for various signals
On board jumper selection to switch UART2 between USB connector and 3 pin connector
1.1.2 Software Features
TI Code Composer Studio 5.0 or later
BIOS C600SDK
1.2 Functional Overview of the EPB_C6748
1.2.1 Figure shows a block diagram of the basic configuration for the TMS320C6748.
Operation of the EPB_C6748 This chapter describes the operation of the EPB_C6748, key interfaces and includes a circuit
board outline.
2.0 The EPB_C6748 Operation
2.0.1 Specification
2.1 The EPB_C6748 Board
2.2 EPB_C6748 Memory
2.2.1 Memory Map
2.3 EPB F28335 Connectors
2.3.1 MMC connector
2.3.2 SATA connector
2.3.3 JTAG connector
2.3.4 CMOS CAMERA connector
2.3.5 Composite Video IN connector
2.3.6 Ethernet connector
2.3.7 USB Host/Device Selection Jumper
2.3.8 USB OTG connector
2.3.9 USB Host connector
2.3.10 UART1 connector
2.3.11 UART2 TxD Jumper
2.3.12 UART2 connector
2.3.13 UART2 RxD Jumper
2.3.14 VGA connector
2.3.15 UART2 (USB) connector
2.3.16 Power Supply connector
2.3.17 LED connectors
2.3.18 MIC IN connector
2.3.19 Audio IN connector
2.3.20 Audio Out connector
2.3.22 Composite Video Out connector
2.4 Jumper
2.5 LEDs
2.6 Switch
2.7 Test points
2.0 EPB_C6748 Operation
This chapter describes the EPB_C6748, key components, and operation.
Information on the EPB‟s various interfaces is also included. The EPB_C6748 consists of
seven major blocks of logic:
Power Supply Audio Interface Connector Video Peripheral Interface SATA interface CMOS Camera Interface LCD interface I/O Interface Connector On board Memory JTAG Interface
Communication Block Control Circuitry
2.0.1 Specifications:
Parameter Description
Voltage Supply 5V DC
CPU TMS320C6748
Operating
Frequency
300MHz/ 375MHz/ 456MHz
Operating Temperature
from -40ºC to 85ºC
2.1 The EPB_C6748 Board
2.2 The EPB_C6748 Memory
The EPB includes the following on-chip memory:
32KB of L1P Program RAM/Cache – Exceptions Support for Error Detection and Program Redirection
32KB of L1D Data RAM/Cache • Software Support 256KB of L2 Unified Mapped RAM/Cache – TI DSP/BIOS™ Flexible RAM/Cache Partition (L1 and L2)
In addition 128MB off-chip DDR2 is provided. And 256MB of Flash memory is also provided
for the same also.
The EPB can load RAM for debug or FLASH ROM can be loaded and run. For larger software
projects it is suggested to do a initial debug with on EPB_C6748 module which supports a
total RAM environment.
2.2.1 Memory Map
The figure below shows the memory map configuration on the EPB_C6748
2.3 EPB_C6748 Connectors
The EPB_C6748 has 22 connectors. The function of each connector is shown in the table
below:
Unit Reference Description
MMC J1 Micro SC Card Connector
SATA J2 SATA Connector
JTAG J3 14 Pin FRC
CMOS J4 36 pin Micro FRC CMOS Sensor Connector
Composite Video In J5 RC2/RCA Metal Jack Connector for Composite
Video In
Ethernet J6 RJ45 Ethernet Connector
Jumper J7 2 Pin jumper
USB OTG J8 Micro USB Connector
USB Host J9 USB A type connector
UART1 J10 DB9-Male Connector
UART2 - TX J11 3-Pin Selection Jumper
UART2 J12 3-Pin Relimate Connector
UART2 – RX J13 3-Pin Selection Jumper
VGA J14 DB15 Female Connector
UART2 J15 USB B type Connector
Power Supply J16 Power Jack Socket
LCD J17, J20 20 Pin FRC Male Connector
Audio J18 3.5mm SMT STEREO Jack
Audio J19 3.5mm SMT STEREO Jack
Audio J21 3.5mm SMT STEREO Jack
Composite Video Out J22 RC2/RCA Metal Jack Connector for Composite
Video Out
2.3.1 MMC Connector (J1):
The EPB_C6748 has an MMC connector which brings out the MMC related SPI signals which
are routed to J1.
The pin numbers and their corresponding signals are shown in the table below.
Pin Number Connection
1 MMCD2
2 MMCD3
3 MMC_CMD
4 3.3V
5 MMC_CLK
6 VSS/ GND
7 MMCD0
8 MMCD1
9 COM/ GND
10 MechPIN/ GND
11 MMC_CD
2.3.2 SATA Connector (J2):
The EPB_C6748 has an SATA connector which brings out the SATA related signals which are
routed to J2. Pin details for the connector are as shown here.
Pin Number Connection
1 GND
2 SATA_TXP
3 SATA_TXN
4 GND
5 SATA_RXN
6 SATA_RXP
7 GND
8 GND
9 GND
2.3.3 JTAG Connector (J3):
The EPB_C6748 is supplied with a 14-pin header interface, J3. This is the standard interface
used by JTAG emulators to interface to Texas Instruments DSPs.
The pin numbers and their corresponding signals are shown in the figure below.
Pin Number Connection
1 TMS
2 TRSTn
3 TDI
4 GND
5 PD/VCC
6 NC
7 TDO
8 GND
9 RTCK
10 GND
11 TCK
12 GND
13 EMU0
14 EMU1
2.3.4 CMOS Camera Connector (J4):
The EPB_C6748 is supplied with a 36-pin header interface, J4. This is the standard interface
used by CMOS Camera interface to Texas Instruments DSPs.
The pin numbers and their corresponding signals are shown in the figure below.]
Pin Number Connection
1 VCC 3.3V
2 VCC 3.3V
3 VCC 3.3V
4 VCC 5V
5 VCC 5V
6 GND
7 NC
8 GND
9 CAM_Clock
10 GND
11 Cvideo_Din15_Vsync
12 Cvideo_Din14_Hsync
13 CVIDEO_DIN11
14 CVIDEO_DIN10
15 CVIDEO_DIN9
16 CVIDEO_DIN8
17 CVIDEO_DIN7
18 CVIDEO_DIN6
19 CVIDEO_DIN5
20 CVIDEO_DIN4
21 CVIDEO_DIN3
22 CVIDEO_DIN2
23 CVIDEO_DIN1
24 CVIDEO_DIN0
25 GND
26 GND
27 Pulled down to GND
28 Pulled down to GND
29 I2C0_SCL
30 I2C0_SDA
31 SPI_SOMI
32 SPI_CLK
33 CMOS_RST (Pulled up by VCC)
34 SPI_CS
35 NC
36 SPI_SIMO
2.3.5 Composite Video IN Connector (J5):
The EPB_C6748 has Composite Video In connector which brings out the Composite Video in
analog signals which are routed to J5. Pin details for the connector are as shown here.
Pin Number Connection
1 GND
2
Composite Video In analog
Signal
3 GND
4 GND
2.3.6 Ethernet Connector (J6):
The EPB_C6748 is supplied with a Ethernet connector as RJ45 connector designator named
J6. This is the standard interface used by Ethernet interface to Texas Instruments DSPs.
The pin numbers and their corresponding signals are shown in the figure below.
Pin Number Connection
1 TX+
2 TX-
3 RX+
4 NC
5 NC
6 RX-
7 NC
8 NC
9 LED_Green (NWAY)
10 LED1_GND/ Pulled UP
11 LED_Yellow (Speed)
12 LED2_GND/ Pulled UP
13 NC/ Earth
14 NC/ Earth
2.3.7 USB Jumper (J7):
It is used to select USB OTG to work as USB Host or USB Device
2.3.8 USB OTG Connector (J8):
The EPB_C6748 has USB OTG connector which brings out the USB signals which are routed
to J8. This connector can work as USB host as well as USB device.
Pin details for the connector are as shown here.
Pin Number Connection
1 VB
2 D-
3 D+
4 ID
5 G1, GND
6 GND
7 GND
8 GND
9 GND
2.3.9 USB Host Connector (J9):
The EPB_C6748 has USB HOST connector which brings out the USB signals which are routed
to J9.
Pin details for the connector are as shown here.
Pin Number Connection
1 VBUS
2 D-
3 D+
4 AGND
5 GND
6 GND
2.3.10 UART1 Connector (J10):
The EPB_C6748 has an RS-232 connector which brings out the UART1 signals. This UART1
connector uses MAX3232 and is routed to a Male 9 pin D-connector, J10. The pin positions
for the J10 connector are shown below
The pin numbers and their corresponding signals are shown in the table below. This
corresponds to a standard dual row to DB-9 connector interface used on personal
computers.
Pin\Name Connection
1 NC
2 RXD
3 TXD
4 NC
5 GND
6 NC
7 NC
8 NC
9 NC
2.3.11 UART2 Transmit line Jumper (J11):
Its UART2 Transmit DATA line selection Jumper
If Jumper is connected between pin1 and pin2, UART2 will work using USB
connector/ Using CP2103
If Jumper is connected between pin2 and pin3, UART2 will work using 3 pin
relimate connector
2.3.12 UART2 Module (J12):
The EPB_C6748 has a 3 pin male relimate connector which brings out the UART2 signals.
This UART2 connector uses MAX3232 and is routed to a 3 pin male relimate connector, J12.
The pin numbers and their corresponding signals are shown in the table below.
Pin Number Connection
1 GND
2 TxD
3 RxD
2.3.13 UART2 Receive line Jumper (J13):
Its UART2 Receive DATA line selection Jumper
If Jumper is connected between pin1 and pin2, UART2 will work using USB
connector/ Using CP2103
If Jumper is connected between pin2 and pin3, UART2 will work using 3 pin
relimate connector
2.3.14 VGA Module (J14):
The EPB_C6748 has a 15 Pin female D-type connector which brings out the VGA signals.
This VGA connector uses routed to a Fe-Male 15 pin D-connector, J14. The pin positions for
the J14 connector are shown below
Pin Number Connection
1 LCD_RED
2 LCD_GREEN
3 LCD_BLUE
4 NC
5 GND
6 GND
7 GND
8 GND
9 VCC_5V
10 GND
11 NC
12 SDA
13 LCD_HSYNC_5V
14 LCD_VSYNC_5V
15 SCL
16 GND
17 GND
2.3.15 UART2 Module/ USB connector (J15):
The EPB_C6748 has an USB B-type connector which brings out the UART2 signals. This USB
connector uses CP2103 and is routed to a USB B-Type, J15. User can use USB connector
directly with the PC to use the serial port UART2. The pin positions for the PL10 connector
are shown below
The pin numbers and their corresponding signals are shown in the table below.
Pin Number Connection
1 VBUS
2 D-
3 D+
4 GND
2.3.16 Power Connector (J16):
Power (5 volts) is brought onto the EPB_C6748 via the J16 connector. The connector has an
outside diameter of 5.5 mm. and an inside diameter of 2 mm.
The diagram of J16, which has the input power, is shown below.
2.3.17 LCD Connector1 (J17) and LCD Connector2 (J20):
The EPBF28335 has two 20 pin FRC connector which brings out the TFT LCD interfacing signals on J17 and J20 connectors. The pin positions for the J17 and J20 connector are shown below
The pin numbers and their corresponding signals are shown in the table below.
Pin Number J17 Connection J20 Connection
1 GND GND
2 VCC_5V VCC_3.3V
3 SPI_SCSn0 GND
4 SPI_SIMO GND
5 SPI_CLK LCD_DATA5
6 LCD_GP1 LCD_DATA6
7 LCD_GP3 LCD_DATA7
8 LCD_GP2 LCD_DATA8
9 GND LCD_DATA9
10 GND LCD_DATA10
11 GND GND
12 LCD_DATA0 GND
13 LCD_DATA1 GND
14 LCD_DATA2 LCD_DATA11
15 LCD_DATA3 LCD_DATA12
16 LCD_DATA4 LCD_DATA13
17 SPI_SOMI LCD_DATA14
18 LCD_VSYNC LCD_DATA15
19 LCD_PCLK I2C0_SDA
20 LCD_HSYNC I2C0_SCL
2.3.18 MIC IN Connector (J18)
The EPB_C6748 has one 3.5 mm Audio jack connector which brings out the MIC IN signal on J18. The audio codec used as hardware is TLV320AIC3106IRGZ. The pin positions for the J18 connector are shown below.
Pin Number Connection
1 GND
2 MIC_LEFT/ GND
3 MIC_RIGHT
4 GND
2.3.19 AUDIO IN Connector (J19)
The EPB_C6748 has one 3.5 mm Audio jack connector which brings out the Audio IN signal on J19. The audio codec used as hardware is TLV320AIC3106IRGZ. The pin positions for the J19 connector are shown below.
Pin Number Connection
1 GND
2 LINE_IN_LEFT
3 LINE_IN_RIGHT
4 GND
2.3.21 AUDIO OUT Connector (J21)
The EPB_C6748 has one 3.5 mm Audio jack connector which brings out the Audio OUT signal on J21. The audio codec used as hardware is TLV320AIC3106IRGZ. The pin positions for the J21 connector are shown below.
Pin Number Connection
1 GND
2 AUDIO_LEFT
3 AUDIO_RIGHT
4 GND
2.3.22 Composite Video OUT Connector (J22):
The EPB_C6748 has Composite Video Out connector which brings out the Composite Video
Out analog signals which are routed to J22. Pin details for the connector are as shown here.
Pin Number Connection
1 GND
2
Composite Video Out analog
Signal
3 GND
4 GND
2.4 Jumpers
The EPB_C6748 has 4 jumpers available to the user which determine how features on the
EPB_C6748 are utilized. The table below lists the jumpers, their type and their position as
shipped from factory. The following sections describe the use of each jumper.
Jumper Number Type Position as Shipped from
Factory
J11 1x3 Pin 1 and pin 2 short
J13 1x3 Pin 1 and pin 2 short
J7 1x2 Open
Video Out Selection Jumper 1x4 Short towards VGA side
Detail description:
Jumper J11:
J11 is used to select UART2 TXD line to use via MAX3232 IC and 3 pin relimate connector J12 or by CP2103 IC and USB connector J15. Type:
Short pin1 and pin2 of J11 of UART2- TX line so that UART2 can be worked using CP2103 IC and USB connector J15.
Short pin2 and pin3 of J11 of UART2- TX line so that UART2 can be worked using 3 pin relimate connector J12
Jumper J13:
J13 is used to select UART2 RXD line to use via MAX3232 IC and 3 pin relimate connector J12 or by CP2103 IC and USB connector J15. Type:
Short pin1 and pin2 of J13 of UART2- RXD line so that UART2 can be worked using CP2103 IC and USB connector J15.
Short pin2 and pin3 of J11 of UART2- RXD line so that UART2 can be worked using 3 pin relimate connector J12
Video Out Selection Jumper:
Video Out Selection Jumper is used to select Video out port for the Image of Video display.
It‟s basically 4 pin jumper as shown in figure. Its basic designator nomenclature is as shown
here
Pin 1 = TP13
Pin 2 = TP16
Pin 3 = TP15
Pin 4 = TP14
Type:
Short pin1 and pin2 of Jumper to select Composite video out port as active video out.
Short pin2 and pin3 of Jumper to select LCD port as active video out.
Short pin4 and pin2 of Jumper to select VGA out port as active video out.
Jumper J7:
J7 is 2 pin jumper. It is used to select USB OTG to work as USB Host or USB
Device
If it is kept open, it will work as USB Host
If it is kept short, it will work as USB Device
2.5 LEDs
The EPB_C6748 has 8 light-emitting diodes.
LED1, LED2, LED3 and Led4 are user LEDs. It can be controlled by User Program
LED5 indicates the presence of USB cable connection to the PC and with J15 connector of
EPB_C6748 and is normally „on‟ when USB cable is connected to the board and PC.
LED6 indicates the presence of +3.3 volts and is normally „on‟ when power is applied to the
board.
LED7 (BLUE) indicates the presence of over-voltage. Power off the board if it is ON.
LED8 (RED) is ON when board is in Reset otherwise it remains OFF
2.6 Switches
The EPB_C6748 has 3 switches.
S6 is RESET switch. It is used to reset the board without power off.
Key1, Key2, Key3, Key4, Key5 are User switches. These switches are controlled by user
program
SW1 is Boot mode select switch. It is used to select the power on boot load options.
2.6.1 Boot Load Option Switch
Switch SW1 is used to select the boot load option used by the L138/C6748 processor on
power up. These selections are shown in the table below. As default all the switches of SW1
are at OFF position.
Below table lists various boot modes supported by the bootloader and a configuration of
boot pins required to select a boot mode. The boot pins are latched by the bootloader when
the device exits reset (on the rising edge of reset).
2.7 Test Point Information:
Designator Use and description
TP1 HS for TVP5147
TP2 VS for TVP5147
TP3 CLOCK OUT pin from the CPU C6748
TP4 +3.3V
TP5 +1.2V
TP6 Vin/ Supply In
TP7 +1.8V
TP8 PGND
TP9 DGND
TP10 DAC4 of ADC7343
TP11 DAC5 of ADC7343
TP12 DAC6 of ADC7343
TP13 Video Out Enable
TP14 VGA Enable
TP15 LCD Enable
TP16 DGND
TP17 RESET IN for CPU
TP18 RESET out from CPU
Practical 1: Installing Code Composer Studio v5.3 Objective: To install Code Composer Studio, that is used for programming in EPB_C6748. Procedure: Run the ccs_setup_5.3.0.00090.exe from the CCS5.3.0.00090_win32 folder
Following screen will appear select “I accept the terms of the License agreement” and click
on Next
Keep the installation path as “C:/ti” and click on Next
Click Next. The installation Process will start as shown below. The installation will take some
time.
Meanwhile installation it will ask for the different tool‟s installation permissions as pop up
window, click OK or Yes for permission grant.
Once installation finish, click on Finish Enjoy…!
Practical 2: Installing BIOS for C6000 Objective: To install the packages for BIOS for C6000 Procedure: Bios Installation: Install bios_c6sdk_02_00_00_00_setupwin32.exe installation steps from setup folder from EPB_6748/EPB_L138 Click next.
Don‟t panic at this stage as it will take too much time to install. As a background it will install too many libraries and installation components
After this installation gets finished, restart PC and again start CCSv5. It will ask “new component discovered”. At this time select all and click Finish. So, CCSv5 gets updated with all new components installed.
Enjoy..!
Document for creating new project: Open CCS V5.3 from desktop shortcut
It will open default CCS V5 screen.
Then it will ask for workspace path Select path “C:\Documents and Settings\<User Name>\workspace_v5_3” for windows XP OS Select path “C:\Users\<User Name>\workspace_v5_3” for windows7 OS
Then it will open Default CCS5 screen as shown below
Click “Project -> New CCS Project” menu.
It will open Following screen Type project name as desired, select output type as Executable as in figure. keep selected “use default location “ so that project will be created in workspace with project name typed Select family: C6000, Variant: C674x Floating point DSP, then select processor TMS320C6748 and use connection type as Texas Instruments XDS100V2 USB Emulator. Then at last select “Hello World” example from “Basic Examples” location in Project Templates and example tab. And Finish
It will open screen as shown here. Here project is already created and it can be seen from
“project explorer”
Editor window will show hello.c file which can be edited as per requirement.
Compile the program by “right click-> build project” or “right click-> rebuild project” as
shown. It will generate hello.out file in “debug” folder.
How to run program:
Hardware connection: Power on EPB_6748 hardware using +5V Power supply Connect XDS100V2 with EPB_6748 using USB A-to-B cable with CPU Reset CPU Steps to run program: Now to debug the program click “debug” as shown in the screen from home screen icon OR from “run->debug” menu.
It will configure/connect EPB_6748 kit with the CCSV5 using XDS100V2 and download the
program in C6748 CPU. It will be automatically.
Once program is loaded click “resume”. It will execute the program and give output on
consol window
Enjoy…!
Program changes in “Hello World” program
1. You can edit the source code of hello.c file as per your requirement,
compile/build/rebuild and debug/execute the code.
2. Default hello world program consist default command file named “C6748.cmd”.
a. Content is as shown here.
b. Here CPU TMS320C6748‟s memory map is organized as per the datasheet.
c. MEMORY area consists of different types of memory‟s start address and its
total length.
d. Comment line displays its type and total size for that memory section.
e. SECTIONS area consist of different section of programs i.e. text, stack, ebss
, cinit etc.
f. This area decides runtime program memory allocation. User can change the
command file for this section as per their requirement.
These sections cover different parts of the object module, which must be “linked” to
physical memory. Our four sections are:
• .text This section collects all assembly code instructions
• .ebss The section covers all global and static variables
• .cinit This section is used for initial values
• .stack The stack memory for local variables, return addresses, parameters
Below C6748.cmd command file will take care the default hello world program with SHRAM memory that is 128KB shared RAM section.
g. Now execute the program with this SHRAM setting for Command file and check the output using same
/****************************************************************************/
/* C6748.cmd */
/* Copyright (c) 2010 Texas Instruments Incorporated */
/* Author: Rafael de Souza */
/* */
/* Description: This file is a sample linker command file that can be */
/* used for linking programs built with the C compiler and */
/* running the resulting .out file on a C6748 */
/* device. Use it as a guideline. You will want to */
/* change the memory layout to match your specific C6xxx */
/* target system. You may want to change the allocation */
/* scheme according to the size of your program. */
/* */
/****************************************************************************/
MEMORY
{
DSPL2ROM o = 0x00700000 l = 0x00100000 /* 1MB L2 Internal ROM */
DSPL2RAM o = 0x00800000 l = 0x00040000 /* 256kB L2 Internal RAM */
DSPL1PRAM o = 0x00E00000 l = 0x00008000 /* 32kB L1 Internal Program RAM */
DSPL1DRAM o = 0x00F00000 l = 0x00008000 /* 32kB L1 Internal Data RAM */
SHDSPL2ROM o = 0x11700000 l = 0x00100000 /* 1MB L2 Shared Internal ROM */
SHDSPL2RAM o = 0x11800000 l = 0x00040000 /* 256kB L2 Shared Internal RAM */
SHDSPL1PRAM o = 0x11E00000 l = 0x00008000 /* 32kB L1 Shared Internal Program RAM */
SHDSPL1DRAM o = 0x11F00000 l = 0x00008000 /* 32kB L1 Shared Internal Data RAM */
EMIFACS0 o = 0x40000000 l = 0x20000000 /* 512MB SDRAM Data (CS0) */
EMIFACS2 o = 0x60000000 l = 0x02000000 /* 32MB Async Data (CS2) */
EMIFACS3 o = 0x62000000 l = 0x02000000 /* 32MB Async Data (CS3) */
EMIFACS4 o = 0x64000000 l = 0x02000000 /* 32MB Async Data (CS4) */
EMIFACS5 o = 0x66000000 l = 0x02000000 /* 32MB Async Data (CS5) */
SHRAM o = 0x80000000 l = 0x00020000 /* 128kB Shared RAM */
DDR2 o = 0xC0000000 l = 0x20000000 /* 512MB DDR2 Data */
}
SECTIONS
{
.text > SHRAM
.stack > SHRAM
.bss > SHRAM
.cio > SHRAM
.const > SHRAM
.data > SHRAM
.switch > SHRAM
.sysmem > SHRAM
.far > SHRAM
.args > SHRAM
.ppinfo > SHRAM
.ppdata > SHRAM
/* COFF sections */
.pinit > SHRAM
.cinit > SHRAM
/* EABI sections */
.binit > SHRAM
.init_array > SHRAM
.neardata > SHRAM
.fardata > SHRAM
.rodata > SHRAM
.c6xabi.exidx > SHRAM
.c6xabi.extab > SHRAM
}
3. Now change the command file as shown here and check the program output and verify.
Replace SHRAM from the SECTIONS section by DSPL2RAM and SHDSPL2RAM so that the program sections will be downloaded to that RAM location and will be executed from that location.
h. Same as change this SECTIONS section for different RAM locations and check
the program output and behavior.
/****************************************************************************/
/* C6748.cmd */
/* Copyright (c) 2010 Texas Instruments Incorporated */
/* Author: Rafael de Souza */
/* */
/* Description: This file is a sample linker command file that can be */
/* used for linking programs built with the C compiler and */
/* running the resulting .out file on a C6748 */
/* device. Use it as a guideline. You will want to */
/* change the memory layout to match your specific C6xxx */
/* target system. You may want to change the allocation */
/* scheme according to the size of your program. */
/* */
/****************************************************************************/
MEMORY
{
DSPL2ROM o = 0x00700000 l = 0x00100000 /* 1MB L2 Internal ROM */
DSPL2RAM o = 0x00800000 l = 0x00040000 /* 256kB L2 Internal RAM */
DSPL1PRAM o = 0x00E00000 l = 0x00008000 /* 32kB L1 Internal Program RAM */
DSPL1DRAM o = 0x00F00000 l = 0x00008000 /* 32kB L1 Internal Data RAM */
SHDSPL2ROM o = 0x11700000 l = 0x00100000 /* 1MB L2 Shared Internal ROM */
SHDSPL2RAM o = 0x11800000 l = 0x00040000 /* 256kB L2 Shared Internal RAM */
SHDSPL1PRAM o = 0x11E00000 l = 0x00008000 /* 32kB L1 Shared Internal Program RAM */
SHDSPL1DRAM o = 0x11F00000 l = 0x00008000 /* 32kB L1 Shared Internal Data RAM */
EMIFACS0 o = 0x40000000 l = 0x20000000 /* 512MB SDRAM Data (CS0) */
EMIFACS2 o = 0x60000000 l = 0x02000000 /* 32MB Async Data (CS2) */
EMIFACS3 o = 0x62000000 l = 0x02000000 /* 32MB Async Data (CS3) */
EMIFACS4 o = 0x64000000 l = 0x02000000 /* 32MB Async Data (CS4) */
EMIFACS5 o = 0x66000000 l = 0x02000000 /* 32MB Async Data (CS5) */
SHRAM o = 0x80000000 l = 0x00020000 /* 128kB Shared RAM */
DDR2 o = 0xC0000000 l = 0x20000000 /* 512MB DDR2 Data */
}
SECTIONS
{
.text > DSPL2RAM
.stack > DSPL2RAM
.bss > DSPL2RAM
.cio > DSPL2RAM
.const > DSPL2RAM
.data > DSPL2RAM
.switch > DSPL2RAM
.sysmem > DSPL2RAM
.far > DSPL2RAM
.args > DSPL2RAM
.ppinfo > DSPL2RAM
.ppdata > DSPL2RAM
/* COFF sections */
.pinit > DSPL2RAM
.cinit > DSPL2RAM
/* EABI sections */
.binit > DSPL2RAM
.init_array > DSPL2RAM
.neardata > DSPL2RAM
.fardata > DSPL2RAM
.rodata > DSPL2RAM
.c6xabi.exidx > DSPL2RAM
.c6xabi.extab > DSPL2RAM
}