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Contemporary Logic DesignIntroduction

© R.H. Katz Transparency No. 1-1

Chapter # 1: Introduction

Contemporary Logic Design

Randy H. KatzUniversity of California, Berkeley

May 1993



Motivation

Dramatic Change in the Way Industry Does Hardware Design

" Pervasive use of Computer-Aided Design Tools

Deemphasis on hand design methods

Emphasis on abstract design representations

Hardware design begins to look like software design

" Emergence of Rapid Implementation Circuit Technology

Programmable rather than discrete logic

" Importance of Sound Design Methodologies

Synchronous Designs

Rules of Composition



The Elements of Modern Design

Rapid PrototypingTechnologies

DesignRepresentations

CircuitTechnologies

MOS

TTL

Behaviors

Blocks

Waveforms

Gates

Truth Tables

Boolean Algebra

Switches

Simulation Synthesis PAL, PLA, ROM, PLD

Computer-AidedDesign

Representations, Circuit Technologies, Rapid Prototyping



Chapter Overview

" Process of Design

" Digital Systems

" Design Representations

" Rapid Prototyping



The Process Of Design

DesignInitial concept: what is the function performed by the object?Constraints: How fast? How much area? How much cost?Refine abstract functional blocks into more concrete realizations

Implementation

Assemble primitives into more complex building blocksComposition via wiringChoose among alternatives to improve the design

DebugFaulty systems: design flaws, composition flaws, component flawsDesign to make debugging easierHypothesis formation and troubleshooting skills

Implementation

Design

Debug



The Art Of Design: Refinement of Representations

1. Functional Specification/What the System Does

Ex: Traffic Light Controller

��

��

Lights point in the directions N, S, E, W

Illuminates the same lights N as S and E as W

Cycles thru the sequence GREEN-YELLOW-RED

N-S and E-W never GREEN or YELLOW at the same time

Stay GREEN for 45 seconds, yellow for 15, red for 60

2. Performance Constraints/Requirements to be Met

speed: compute changes in under 100 ms

power: consume less than 20 watts

area: implementation in less than 20 square cm

cost: less than $20 in manufacturing costs



The Art of Design: "To Design Is To Represent"

1. English language specificationeasy to write, but not precise and subject to ambiguity

2. Functional description

more precise specification

flow charts, program fragments

3. Structural description

complex components decomposed intocompositions of less complex components

4. Physical description

the design in terms of most primitivebuilding blocks, e. g., logic gates ortransistors

Start

after 45 seconds

after 15 seconds

after 45 seconds

after 15 seconds

N-S Red E-W Y ellow

N-S Red E-W Green

N-S Y ellow E-W Red

N-S Green E-W Red



The Process of Design

Top Down Design: Complex functions replaced by more primitive functions

Bottom Up Design: Primitives composed to build more and more complex assemblies

Rules of Composition and Correctness by Construction: Electrical Rules: how many components can be cascaded? Timing Rules: how does the system change in conjunction with periodic triggering events?

Implementation as Assembly




StructuralRepresentation

To decomposition of high level functions into more primitive functions

Top Down Decomposition

T raffic Light Subsystem

T imer

Start

45 seconds

Start

T imer

15 seconds

Start

N-S Lights

E-W Lights

N-S Green N-S Y ellow

N-S Red E-W Green

E-W Y ellow E-W Red


N-S Red E-W Green

E-W Y ellow E-W Red


N-S Red E-W Green

E-W Y ellow E-W Red

Light Sequencer

Primitive Sequencer

45 seconds

15 seconds

Decoder




Rooms

Floor

Building

Bottom Up Assembly

Primitives composed to buildmore and more complex assemblies

e.g., a group of rooms form a floor

e.g., a group of floors form a bldg.

a group of transistors form a gate

a group of gates form an addition circuit

addition circuits plus storage circuitsform a processor datapath



The Process of Design: Debugging the System

" Design Flaws

Implementation does not meet functional specification

Logic design is incorrect (wrong function implemented)

Misinterpretation or corner cases ignored

" Implementation Flaws

Individual modules function correctly but their compositions do not

Misunderstanding of interface and timing behavior

Wiring mistakes, Electrical mistakes

" Component Flaws

Logically correct and correctly wired

Not all hardware components are guaranteed to work!

E.g., burnt out component

What Can Go Wrong




Debugging via Simulation Before Construction

Debugging Skills:" Improving the testability of the design

" Formulating a testing plan and choosing test cases

" Hypothesizing about the cause of the problem

" Isolating portions of the implementation for testing

" Effective use of laboratory instruments for troubleshooting



Digital Hardware Systems

Digital Systems

Digital vs. Analog Waveforms

Analog: values vary over a broad range continuously

Digital: only assumes discrete values

+5

V

–5

T ime

+5

V

–5

1 0 1

T ime




Analog systems: slight error in input yields large error in output

Digital systems more accurate and reliable Readily available as self-contained, easy to cascade building blocks

Computers use digital circuits internally

Interface circuits (i.e., sensors & actuators) often analog

This course is about logic design, not system design (processor architecture), not circuit design (transistor level)

Advantages of Digital Systems




" Two discrete values: yes, on, 5 volts, current flowing, magnetized North, "1" no, off, 0 volts, no current flowing, magnetized South, "0"

" Advantage of binary systems: rigorous mathematical foundation based on logic

the three preconditions must be true to imply the conclusion

IF the garage door is openAND the car is runningTHEN the car can be backed out of the garage

both the door must be open and the carrunning before I canback out

IF N-S is greenAND E-W is redAND 45 seconds has expired since the last light changeTHEN we can advance to the next light configuration

Digital Binary Systems




Algebra: variables, values, operations

In Boolean algebra, the values are the symbols 0 and 1 If a logic statement is false, it has value 0 If a logic statement is true, it has value 1

Operations: AND, OR, NOT

Boolean Algebra and Logical Operators

0 0 1 1

X Y X AND Y

0 1 0 1

0 0 0 1

X Y X OR Y

0 0 1 1

0 1 0 1

0 1 1 1

X NOT X

0 1

1 0




IF the garage door is openAND the car is runningTHEN the car can be backed out of the garage

door open? car running? back out car?false/0false/0true/1true/1

false/0true/1false/0true/1

false/0false/0false/0TRUE/1

Hardware Systems and Logical Operators




Physical electronic components are continuous, not discrete!

These are the building blocks of all digital components!

Transition from logic 1 to logic 0does not take place instantaneouslyin real digital systems

Intermediate values may be visiblefor an instant

Boolean algebra useful for describing the steady state behavior of digital systems

Be aware of the dynamic, time varying behavior too!

The Real World

+5

V

0

Logic 1

Logic 0




Integrated circuit technology choice of conducting, non-conducting, sometimes conducting ("semiconductor") materials

whether or not their interaction allows electrons to flow forms the basis for electrically controlled switches

Digital Circuit Technologies

Main technologies

MOS: Metal-Oxide-Silicon

Bipolar Transistor-Transistor Logic Emitter Coupled Logic




Transistorbasic electrical switch

three terminal switch: gate, source, drain

voltage between gate and source exceeds threshold switch is conducting or "closed" electrons flow between source and drain

when voltage is removed, the switch is "open" or non-conductingconnection between source and drain is broken

MOS Technology

Gate

Drain Source




Circuit that implements logical negation (NOT)

1 at input yields 0 at output0 at input yields 1 at output

Inverter behavior as a function of input voltage input ramps from 0V to 5V output holds at 5V for some range of small input voltages then changes rapidly, but not instantaneously!

remember distinction betweensteady state and dynamic behavior

V Out

+5

0 +5 V In

Logic 0 Input V oltage

Logic 1 Input V oltage




Combinational logic no feedback among inputs and outputs outputs are a pure function of the inputs e.g., full adder circuit: (A, B, Carry In) mapped into (Sum, Carry Out)

Network implemented from switching elements or logicgates. The presence of feedback distinguishes between sequentialand combinational networks.

Combinational vs. Sequential Logic

- - -

X 1 X 2 X n

Switching Network

Z 1 Z 2 Z m

- - -

A B Cin

Full Adder

Sum Cout




Sequential logic

inputs and outputs overlap outputs depend on inputs and the entire history of execution!

network typically has only a limited number of unique configurations these are called states e.g., traffic light controller sequences infinitely through four states

new component in sequential logic networks: storage elements to remember the current state

output and new state is a function of the inputs and the old state i.e., the fed back inputs are the state!

Synchronous systemsperiod reference signal, the clock, causes the storage elements to accept new values and to change state

Asynchronous systemsno single indication of when to change state




Traffic Light Example

Next State LogicMaps currentstate and alarmevents into thenext state

Current StateStorage elementsreplaced by next statewhen the clock signalarrives

Output LogicCurrent state mappedinto control signalsto change the lightsand to start the eventtimersIF controller in state N-S green, E-W red

AND the 45 second timer alarm is assertedTHEN the next state becomes N-S yellow,E-W red when the clk signal is next asserted

Combinational vs Sequential Logic

T raffic Light Controller

Current T raffic Light Controller Configuration

Other Inputs, Like T imer Alarms

New T raffic Light Controller Configuration

Next State Combinational

Logic

S T A T E

Output Combinational

Logic

Clock T imer Alarms

Current State

Detailed Light Control Signals



Representations of a Digital Design

Switches

A switch connects two points under control signal.

when the control signal is 0 (false), the switch is open

when it is 1 (true), the switch is closed

when control is 1 (true), switch is open

when control is 0 (false), switch is closed

Normally Closed

Normally Open

Open Switch

Control

Normally Open Switch

Closed Switch

T rue

False

Open Switch

Control

Normally Closed Switch

Closed Switch

T rue

False



Representations of a Digital Design: Switches

Examples: routing inputs to outputs through a maze

Floating nodes: what happens if the car is not running? outputs are floating rather than forced to be false

Under all possible control signal settings (1) all outputs must be connected to some input through a path (2) no output is connected to more than one input through any path

EXAMPLE: IF car in driveway OR (car in garage AND NOT garage door closed) AND car running THEN can back out car

Car in garage Car

running

True

True

Car can back out

Garage door closed

Car in driveway

EXAMPLE: IF car in garage AND garage door open AND car running THEN back out car

T rue Car can back out

Garage door open

Car running

Car in garage ��

��

��

��



Representations of a Digital Design: Switches

Implementation of AND and OR Functions with Switches

A

False

T rue

output

B

��

��

A

False

T rue

output

B

��

��

��

��

��

AND functionSeries connection to TRUE

OR functionParallel connection to TRUE




Truth Tablestabulate all possible input combinations and their associated output values

Example: half adder adds two binary digits to form Sum and Carry

Example: full adder adds two binary digits and Carry in to form Sum and Carry Out

NOTE: 1 plus 1 is 0 with a carry of 1 in binary

A B

0 0 1 1

0 1 0 1

Sum Carry

0 1 1 0

0 0 0 1

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C in 0 1 0 1 0 1 0 1

S um 0 1 1 0 1 0 0 1

C out 0 0 0 1 0 1 1 1



Representations of a Digital DesignBoolean Algebra

NOT X is written as XX AND Y is written as X & Y, or sometimes X YX OR Y is written as X + Y

values: 0, 1variables: A, B, C, . . ., X, Y, Zoperations: NOT, AND, OR, . . .

A

0011

B

0101

Sum

0110

Carry

0001

Sum = A B + A B

Carry = A B

OR'd together product terms for each truth table

row where the function is 1

if input variable is 0, it appears in complemented form;

if 1, it appears uncomplemented

Deriving Boolean equations from truth tables:



Representations of a Digital Design: Boolean Algebra

A

00001111

B

00110011

Cin

01010101

Sum

01101001

Cout

00010111

Another example:

Sum = A B Cin + A B Cin + A B Cin + A B Cin

Cout = A B Cin + A B Cin + A B Cin + A B Cin



Representations of a Digital Design: Boolean Algebra

Reducing the complexity of Boolean equations

Laws of Boolean algebra can be applied to full adder's carry out function to derive the following simplified expression:

Cout = A Cin + B Cin + A B

Verify equivalence with the original Carry Out truth table:

place a 1 in each truth table row where the product term is true

each product term in the above equation covers exactly two rows in the truth table; several rows are "covered" by more than one term

A 0 0 0 0 1 1 1 1

C in 0 1 0 1 0 1 0 1

��

��

��

��

B 0 0 1 1 0 0 1 1

C out 0 0 0 1 0 1 1 1

B C in

A C in

A B



Representations of a Digital DesignGates

most widely used primitive building block in digital system design

StandardLogic Gate

RepresentationHalf Adder Schematic

Netlist: tabulation of gate inputs & outputs and the nets they are connected to

Net: electrically connected collection of wires

Inverter

AND

OR

Net 1

Net 2

A

B

CARR Y

SUM

��

��

��

��

��

��



Representations of a Digital Design: Gates

Full Adder Schematic

Fan-in: number of inputs to a gateFan-out: number of gate inputs an output is connected to

Technology "Rules of Composition" place limits on fan-in/fan-out

Cin B A \Cin \ B \ A

A

B

Cin SUM

Cout

A B

B C in

A C in

C out



Representations of a Digital DesignWaveforms

dynamic behavior of a circuitreal circuits have non-zero delays

Timing Diagram of the Half Adder

sumpropagation

delay

circuit hazard: 1 plus 0 is 1, not 0!

sumpropagation

delay

Output changes are delayed from input changes

The propagation delay is sensitive to paths in the circuit

Outputs may temporarily change from the correct value to the wrong value back again to the correct value: this is called a glitch or hazard

100 200

A B SUM CARR Y



Representations of a Digital Design: Waveforms

Tracing the Delays: A=0,B=0 to A=0,B=1

(i) Initial conditions (ii) Y changes from 0 to 1

10 time unitsof delay

(iii) Output of top AND gatechanges after 10 time units

(iv) Output of OR gatechanges after 10 time units

0

0 1 0

1 0 A

1 0

B 0 0

SUM

CARR Y

1 0

0

0 1 0

1 0 A

1 0

B 0 0

SUM

CARR Y

1 1

0

1 1 0

1 0

A

1 0

B 0 0

SUM

CARR Y

0 1

1

1 1 0

1 0 A

1 0

B 0 0

SUM

CARR Y

0 1



Representations of a Digital DesignBlocks

structural organization of the design

black boxes with input and output connections

corresponds to well defined functions

concentrates on how the components are composed by wiring

Full Adder realized in terms ofcomposition of half adder blocks

Block diagram representationof the Full Adder

Sum

Cout

A

B

Cin

A

B

Sum

Carry HA

A

B

Sum

Carry HA

Sum

Cout

A

B

Cin

A

Cin

Sum

Cout

F A B



Glitch 100 200

A B Cin Sum Cout

��

��


Waveform Verification

Does the composed full adder behave the same as the full gate implementation?

Sum, Cout waveforms lag input changes in time

How many time units after input change is it safe to examine the outputs?



Representation of a Digital Design: Behaviors

ABEL Hardware Description Language

MODULE half_adder;

a, b, sum, carry PIN 1, 2, 3, 4;

TRUTH_TABLE {[a, b] -> [sum, carry]}

[0, 0] -> [0, 0];

[0, 1] -> [1, 0];

[1, 0] -> [1, 0];

[1, 1] -> [0, 1];

END half_adder;

MODULE half_adder;

a, b, sum, carry PIN 1, 2, 3, 4;

EQUATIONS

SUM = (A & !B) # (!A & B);

CARRY = A & B;

END half_adder;

Truth TableSpecification

EquationSpecification

AND OR NOT



Representations of a Digital DesignBehaviors

-- ***** inverter gate model *****-- external portsENTITY inverter_gate; PORT (a: IN BIT; z: OUT BIT);END inverter_gate;

-- internal behaviorARCHITECTURE behavioral OF inverter_gate ISBEGIN z <= NOT a AFTER 10 ns;END behavioral;

-- ***** and gate model *****-- external portsENTITY and_gate; PORT (a, b: IN BIT; z: OUT BIT);END and_gate;

-- internal behaviorARCHITECTURE behavioral OF and_gate ISBEGIN z <= a AND b AFTER 10 ns;END behavioral;

Black Box Viewas seen by outside

world

Internal BehaviorNote delay statement

Hardware description languages structure and function of the digital design

Example: Half Adder in VHDL




-- ***** or gate model *****-- external portsENTITY or_gate; PORT (a, b: IN BIT; z: OUT BIT);END or_gate;

-- internal behaviorARCHITECTURE behavioral OF or_gate ISBEGIN z <= a OR b AFTER 10 ns;END behavioral;

-- ***** half adder model *****-- external portsENTITY half_adder; PORT (a_in, b_in: INPUT; sum, c_out: OUTPUT);END half_adder;

-- internal structureARCHITECTURE structural of half_adder IS -- component types to use COMPONENT inverter_gate PORT (a: IN BIT; z: OUT BIT); END COMPONENT; COMPONENT and_gate PORT (a, b: IN BIT; z: OUT BIT); END COMPONENT; COMPONENT or_gate PORT (a, b: IN BIT; z: OUT BIT); END COMPONENT;

-- internal signal wires SIGNAL s1, s2, s3, s4: BIT;

AND, OR, NOT modelstypically included in a

library

Particular componentsto be used within the

model of the half adder




BEGIN -- one line for each gate, describing its type and connections i1: inverter_gate PORT MAP (a_in, s1); i2: inverter_gate PORT MAP (b_in, s2); a1: and_gate PORT MAP (b_in, s1, s3); a2: and_gate PORT MAP (a_in, s2, s4); o1: or_gate PORT MAP (s3, s4, sum);END structural;

Textual description of the netlist

This VHDL specification corresponds to the following labeled schematic

A

SUM

Carry

s4

s3 a1

a2

a3

o1

i1

i2 s2

s1

B



Rapid Electronic System Prototyping

quick construction of digital systems to prove concept

rapid exploration of alternative design approaches

performance traded off for faster path to implementation

Goals:

Techniques:computer-aided design tools simulation: find out how the design will behave before constructing it synthesis: generate detailed descriptions, like schematics, from high level descriptions, like Boolean equations

quick turnaround implementation technologies programmable logic



Rapid Electronic System Prototyping:

Computer-Aided Design

Synthesis tools

create a portion of the design from other portions

map more abstract representation to more physical representation

BehavioralSynthesis

VHDL BooleanEquations

LogicSynthesis

GateLibraries

Schematics

map a representation into a more optimized form of that representation, e.g., espresso

ABEL




Simulation

program which dynamically executes an abstract design description

obtain verification of functional correctness and some timing information before the design is physically constructed

easier to probe and debug a simulation than an implemented design

simulation cannot guarantee that a design will work only as good as the test cases attempted does not check electrical errors abstracts away some of the realities of a real system

Logic Simulation

design described in terms of logic gatesvalues are 0, 1 (plus others to be introduced)good for truth table verification

Timing Simulationwaveform inputs and outputsmodel of gate delaysare the waveform shapes what was expected?identification of performance bottlenecks



Rapid Electronic System ImplementationRapid Implementation Technologies

the function and interconnect of a component can be "personalized"

alternative to discrete logic gates and wires

reduces wiring complexity and parts count

facilitates more rapid design changes and enhancements

Programming with 1's and 0's

component function configured through truth table

interconnect among internal modules also configured in this way selectively blown fuses programmable switching matrix configured by 1's and 0's




Example: Read-Only Memorieshardware implementation of a two dimensional array

inputs form the index into the array

the binary word at the indexed memory location contains the output values

contents are programmed once, read many times

Half Adder Realized as a ROM: Full Adder Realized as a ROM:

Half adder

Index contents 0 0 1 1

0 1 0 1

0 1 1 0

0 0 0 1

A B S

U M

C A R R Y

Full adder

Index contents 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 0 1 0 0 1

0 0 0 1 0 1 1 1

A B Cin

S U M

C o u t

0 0 0 0 1 1 1 1



Chapter Review

We have introduced:

" the process of design:

functional decomposition and design by assembly

" the kinds of systems we will be designing:

combinational and sequential logic binary digital systems implemented in MOS and bipolar technology

" the many levels of design representation:

from switches to behavioral descriptions

" the changing technological landscape:

rapid electronic system implementation facilitated by computer-aided design tools (in particular, synthesis and simulation tools) and programmable logic devices

Contemporary Logic DesignTwo-Level Logic


Chapter #2: Two-Level Combinational Logic



May 1993



Motivation

" Rapid prototyping technology

Use of computer aided design tools: espresso

" Design Techniques that Spanning Multiple Technologies

Transistor-Transistor Logic (TTL)

Complementary Metal on Oxide Silicon (CMOS)

" Multiple Design Representations

Truth Tables

Static gate descriptions

Dynamic waveform descriptions

Further Amplification on the Concepts of Chapter #1:



Chapter Overview

" Logic Functions and Switches

Not, AND, OR, NAND, NOR, XOR, XNOR

" Gate Logic

Laws and Theorems of Boolean Algebra

Two Level Canonical Forms

Incompletely Specified Functions

" Two Level Simplification

Boolean Cubes

Karnaugh Maps

Quine-McClusky Method

Espresso Methos



Logic Functions: Boolean Algebra

Algebraic structure consisting of:

set of elements B

binary operations {+, "}

unary operation {'}

such that the following axioms hold:

1. B contains at least two elements, a, b, such that a b

2. Closure a,b in B, (i) a + b in B (ii) a " b in B

3. Commutative Laws : a,b in B, (i) a + b = b + a (ii) a " b = b " a

4. Identities : 0, 1 in B (i) a + 0 = a (ii) a " 1 = a

5. Distributive Laws : (i) a + (b " c) = (a + b) " (a + c) (ii) a " (b + c) = a " b + a " c

6. Complement : (i) a + a' = 1 (ii) a " a' = 0



Logic Functions: Boolean AlgebraB = {0,1}, + = OR, " = AND, ' = NOT is a Boolean Algebra

must verify that the axioms hold:E.g., Commutative Law:

0 + 1 = 1 + 0?1 = 1

0 " 1 = 1 " 0?0 = 0

Theorem: any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using ', +, "

Reviewfrom

Chapter 1

Description Z = 1 if X and Y are both 1

Gates Truth Table SwitchesXY Z

Y 0 1 0 1

X 0 0 1 1

Z 0 0 0 1

X Y

X • Y

false

true

NOT

AND

OR

Description If X = 0 then X ' = 1 If X = 1 then X ' = 0

Switches Gates

X

X X 0 1

X 1 0

T ruth T able

X T rue

False X

Description Z = 1 if X or Y (or both) are 1

Gates T ruth T able Switches X Y Z X

0 0 1 1

Y 0 1 0 1

Z 0 1 1 1

X Y

X + Y

False

T rue



Logic Functions: From Expressions to Gates

More than one way to map an expression to gates

E.g., Z = A' " B' " (C + D) = (A' " (B' " (C + D)))

T1

T2

Literal : each appearance of a variable or its complement in an expression

E.g., Z = A B' C + A' B + A' B C' + B' C

use of 3-input gate

3 variables, 10 literals

A

B

C

D T

2

T 1

Z

Z

A

B

C

D



F0 0 0 0 0

F1 0 0 0 1

F2 0 0 1 0

F3 0 0 1 1

F4 0 1 0 0

F5 0 1 0 1

F6 0 1 1 0

F7 0 1 1 1

F8 1 0 0 0

F9 1 0 0 1

F10 1 0 1 0

F1 1 1 0 1 1

F12 1 1 0 0

F13 1 1 0 1

F14 1 1 1 0

F15 1 1 1 1

X 0 0 1 1

Y 0 1 0 1

0 X • Y X Y X + Y X Y

1

Logic Functions: NAND, NOR, XOR, XNOR

16 functions of two variables:

X, X', Y, Y', X"Y, X+Y, 0, 1 only half of the possible functions

NAND

NOR

Description Z = 1 if X is 0 or Y is 0

Gates T ruth T able Switches

X Y

X • Y

False

T rue X 0 0 1 1

Y 0 1 0 1

Z 1 1 1 0

X Y

Z

Description Z = 1 if both X and Y are 0

Gates T ruth T able Switches X

Y Z X

0 0 1 1

Y 0 1 0 1

Z 1 0 0 0

X Y

X + Y False

T rue



Logic Functions: NAND, NOR Implementation

NAND, NOR gates far outnumber AND, OR in typical designs

easier to construct in the underlying transistor technologies

Any Boolean expression can be implemented by NAND, NOR, NOT gates

In fact, NOT is superfluous (NOT = NAND or NOR with both inputs tied together)

X0

1

Y0

1

X NOR Y1

0

X0

1

Y0

1

X NAND Y1

0



Logic Functions: XOR, XNOR

XOR: X or Y but not both ("inequality", "difference")XNOR: X and Y are the same ("equality", "coincidence")

X ⊕⊕⊕⊕ Y = X Y' + X' Y X ⊕⊕⊕⊕ Y = X Y + X' Y'

(a) XOR (b) XNOR

Description Z = 1 if X has a different value than Y

Gates

T ruth T able

X

Y Z

X 0 0 1 1

Y 0 1 0 1

Z 0 1 1 0

Description Z = 1 if X has the same value as Y

Gates

T ruth T able

X

Y Z

X 0 0 1 1

Y 0 1 0 1

Z 1 0 0 1



Logic Functions: Waveform View



Logic Functions: Rationale for Simplification

Logic Minimization: reduce complexity of the gate level implementation

" reduce number of literals (gate inputs)

" reduce number of gates

" reduce number of levels of gates

fewer inputs implies faster gates in some technologies

fan-ins (number of gate inputs) are limited in some technologies

fewer levels of gates implies reduced signal propagation delays

minimum delay configuration typically requires more gates

number of gates (or gate packages) influences manufacturing costs

Traditional methods: reduce delay at expense of adding gates

New methods: trade off between increased circuit delay and reduced gate count



Logic Functions: Alternative Gate Realizations

Two-Level Realization(inverters don't count)

Multi-Level RealizationAdvantage: Reduced Gate

Fan-ins

Complex Gate: XORAdvantage: Fewest Gates

TTL Package Counts: Z1 - three packages (1x 6-inverters, 1x 3-input AND, 1x 3-input OR) Z2 - three packages (1x 6-inverters, 1x 2-input AND, 1x 2-input OR) Z3 - two packages (1x 2-input AND, 1x 2-input XOR)

0 1 0 1 0 1

A B C

0

0

Z 1

Z 2

Z 3

0

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Z 0 1 0 1 0 1 1 0



Logic Functions: Waveform Verification

Under the same input stimuli, the three alternative implementations have essentially the same waveform behavior.

Slight variations due to differences in number of gate levels

The three implementations are equivalent



Gate Logic: Laws of Boolean Algebra

Duality: a dual of a Boolean expression is derived by replacing AND operations by ORs, OR operations by ANDs, constant 0s by 1s, and 1s by 0s (literals are left unchanged).

Any statement that is true for an expression is also true for its dual!

Useful Laws/Theorems of Boolean Algebra:Operations with 0 and 1:

Idempotent Law:

Involution Law:

Laws of Complementarity:

Commutative Law:

1. X + 0 = X2. X + 1 = 1

1D. X " 1 = X2D. X " 0 = 0

3. X + X = X 3D. X " X = X

4. (X')' = X

5. X + X' = 1 5D. X " X' = 0

6. X + Y = Y + X 6D. X " Y = Y " X



Gate Logic: Laws of Boolean Algebra ( cont )

Distributive Laws:

Simplification Theorems:

DeMorgan's Law:

Duality:

Theorems for Multiplying and Factoring:

Consensus Theorem:

8. X " (Y+ Z) = (X " Y) + (X " Z) 8D. X + (Y" Z) = (X + Y) " (X + Z)

9. X " Y + X " Y' = X10. X + X " Y = X11. (X + Y') " Y = X " Y

9D. (X + Y) " (X + Y') = X10D. X " (X + Y) = X11D. (X " Y') + Y = X + Y

12. (X + Y + Z + ...)' = X' " Y' " Z' " ...13. {F(X1,X2,...,Xn,0,1,+,")}' = {F(X1',X2',...,Xn',1,0,",+)}

12D. (X " Y " Z " ...) ' = X' + Y' + Z' + ...

14. (X + Y + Z + ...) = X " Y " Z " ...

15. {F(X1,X2,...,Xn,0,1,+,")} = {F(X1,X2,...,Xn,1,0,",+)}

D

D

14D. (X "FY " Z " ...) = X + Y + Z + ...D

16. (X + Y) " (X' + Z) = X " Z + X' " Y 16D. X " Y + X' " Z = (X + Z) " (X' + Y)

17. (X " Y) + (Y " Z) + (X' " Z) = X " Y + X' " Z

17D. (X + Y) " (Y + Z) " (X' + Z) = (X + Y) " (X' + Z)

Associative Laws:7. (X + Y) + Z = X + (Y + Z) = X + Y + Z

7D. (X " Y) " Z = X " (Y " Z) = X " Y " Z



Gate Logic: Laws of Boolean AlgebraProving theorems via axioms of Boolean Algebra:

E.g., prove the theorem: X " Y + X " Y' = X

E.g., prove the theorem: X + X " Y = X



Gate Logic: Laws of Boolean AlgebraProving theorems via axioms of Boolean Algebra:

E.g., prove the theorem: X " Y + X " Y' = X

X " Y + X "Y' = X " (Y + Y')

X " (Y + Y') = X " (1)

X " (1) = X

distributive law (8)

complementary law (5)

identity (1D)

E.g., prove the theorem: X + X " Y = X

X + X " Y = X " 1 + X " Y

X " 1 + X " Y = X " (1 + Y)

X " (1 + Y) = X " (1)

X " (1) = X

identity (1D)

distributive law (8)

identity (2)

identity (1)




DeMorgan's Law

(X + Y)' = X' " Y'

(X " Y)' = X' + Y'

NOR is equivalent to ANDwith inputs complemented

NAND is equivalent to ORwith inputs complemented

Example:Z = A' B' C + A' B C + A B' C + A B C'

Z' = (A + B + C') " (A + B' + C') " (A' + B + C') " (A' + B' + C)

DeMorgan's Law can be used to convert AND/OR expressionsto OR/AND expressions

X 0 0 1 1

Y 0 1 0 1

X 1 1 0 0

Y 1 0 1 0

X + Y 1 0 0 0

X•Y 1 0 0 0

X 0 0 1 1

Y 0 1 0 1

X 1 1 0 0

Y 1 0 1 0

X + Y 1 1 1 0

X•Y 1 1 1 0




Apply the laws and theorems to simplify Boolean equations

Example: full adder's carry out function

Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin




Apply the laws and theorems to simplify Boolean equations

Example: full adder's carry out function

Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin

= A' BCont + A B' Cin + A B Cin' + A B Cin + A B Cin

= A' B Cin + A B Cin + A B' Cin + A B Cin' + A B Cin

= (A' + A) B Cin + A B' Cin + A B Cin' + A B Cin

= (1) B Cin + A B' Cin + A B Cin' + A B Cin

= B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin

= B Cin + A B' Cin + A B Cin + A B Cin' + A B Cin

= B Cin + A (B' + B) Cin + A B Cin' + A B Cin

= B Cin + A (1) Cin + A B Cin' + A B Cin

= B Cin + A Cin + A B (Cin' + Cin)

= B Cin + A Cin + A B (1)

= B Cin + A Cin + A B

identity

associative



A + 0 = A A + 1 = 1

A A

0

=

A 1

=

1

Gate Logic: Switching Equivalents

Idempotent Laws Identity Laws

Complementarity Laws Simplification Theorems

A • A = A

A A

A

A

A

A + A = A

= =

A

A + A = 1 A • A = 0

A

A

=

1

A A

=

0

X Y + X Y = X X + X Y = X

X Y

X Y

X Y

X

= =

X X



Gate Logic: 2-Level Canonical Forms

Truth table is the unique signature of a Boolean function

Many alternative expressions (and gate realizations) may have the same truth table

Canonical form: standard form for a Boolean expression provides a unique algebraic signature

Sum of Products Formalso known as disjunctive normal form, minterm expansion

F = A' B C + A B' C' + A B' C + A B C' + A B C0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

F' = A' B' C' + A' B' C + A' B C'

F 0 0 0 1 1 1 1 1

F 1 1 1 0 0 0 0 0

C 0 1 0 1 0 1 0 1

B 0 0 1 1 0 0 1 1

A 0 0 0 0 1 1 1 1



Gate Logic: Two Level Canonical Forms

Sum of Products

Shorthand Notation forMinterms of 3 Variables

product term / minterm:ANDed product of literals in which eachvariable appears exactly once, in true orcomplemented form (but not both!)

F in canonical form:

F(A,B,C) = ΣΣΣΣm(3,4,5,6,7)= m3 + m4 + m5 + m6 + m7= A' B C + A B' C' + A B' C + A B C' + A B C

canonical form/minimal formF = A B' (C + C') + A' B C + A B (C' + C)

= A B' + A' B C + A B

= A (B' + B) + A' B C

= A + A' B C

= A + B C2-Level AND/OR

Realization F = (A + B C)' = A' (B' + C') = A' B' + A' C'

B

C

A

F

A B C = m 1 A B C = m 2 A B C = m 3 A B C = m 4 A B C = m 5 A B C = m 6 A B C = m 7

A

0 0 0 0 1 1 1 1

B

0 0 1 1 0 0 1 1

C

0 1 0 1 0 1 0 1

Minterms

A B C = m 0



Gate Logic: 2 Level Canonical Forms

Product of Sums / Conjunctive Normal Form / Maxterm Expansion

Maxterm Shorthand Notationfor a Function of Three Variables

Maxterm:ORed sum of literals in which eachvariable appears exactly once in eithertrue or complemented form, but not both!

Maxterm form:Find truth table rows where F is 00 in input column implies true literal1 in input column implies complemented literal

F(A,B,C) = ΠΠΠΠM(0,1,2)= (A + B + C) (A + B + C') (A + B' + C)

F’(A,B,C) = ΠΠΠΠM(3,4,5,6,7)= (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Maxterms A + B + C = M 0 A + B + C = M 1 A + B + C = M 2 A + B + C = M 3 A + B + C = M 4 A + B + C = M 5 A + B + C = M 6 A + B + C = M 7



Gate Logic: Two Level Canonical FormsSum of Products, Products of Sums, and DeMorgan's Law

F' = A' B' C' + A' B' C + A' B C'

Apply DeMorgan's Law to obtain F:

(F')' = (A' B' C' + A' B' C + A' B C')'

F = (A + B + C) (A + B + C') (A + B' + C)

F' = (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')

(F')' = {(A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')}'

F = A' B C + A B' C' + A B' C + A B C' + A B C

Apply DeMorgan's Law to obtain F:



Gate Logic: Two-Level Canonical Forms

Four Alternative Implementations of F:

Canonical Sum of Products

Minimized Sum of Products

Canonical Products of Sums

Minimized Products of Sums

A

B

F 2

F 3

F 4

F 1 C



Gate Logic: Two-Level Canonical Forms

Waveform Verification of the Three Alternatives

Eight Unique Combinationsof Three Inputs

Except for timing glitches ,output waveforms of the

three implementations areessentially identical

100 200

A

B

C

F 1

F 2

F 3



Gate Logic: Two-Level Canonical FormsMapping Between Forms

1. Minterm to Maxterm conversion: rewrite minterm shorthand using maxterm shorthand replace minterm indices with the indices not already used

E.g., F(A,B,C) = ΣΣΣΣm(3,4,5,6,7) = ΠΠΠΠM(0,1,2)

2. Maxterm to Minterm conversion:rewrite maxterm shorthand using minterm shorthandreplace maxterm indices with the indices not already used

E.g., F(A,B,C) = ΠΠΠΠM(0,1,2) = ΣΣΣΣm(3,4,5,6,7)

3. Minterm expansion of F to Minterm expansion of F':in minterm shorthand form, list the indices not already used in F

E.g., F(A,B,C) = ΣΣΣΣm(3,4,5,6,7) F'(A,B,C) = ΣΣΣΣm(0,1,2) = ΠΠΠΠM(0,1,2) = ΠΠΠΠM(3,4,5,6,7)

4. Minterm expansion of F to Maxterm expansion of F':rewrite in Maxterm form, using the same indices as F

E.g., F(A,B,C) = ΣΣΣΣm(3,4,5,6,7) F'(A,B,C) = ΠΠΠΠM(3,4,5,6,7) = ΠΠΠΠM(0,1,2) = ΣΣΣΣm(0,1,2)



Gate Logic: Positive vs. Negative Logic

Normal Convention: Postive Logic/Active HighLow Voltage = 0; High Voltage = 1

Alternative Convention sometimes used: Negative Logic/Active Low

Behavior in termsof Electrical Levels

Two Alternative InterpretationsPositive Logic ANDNegative Logic OR

Dual Operations

Negative Logic Positive Logic V oltage T ruth T able

F low low low high

F 0 0 0 1

F 1 1 1 0

A low low high high

B low high low high

B 0 1 0 1

A 0 0 1 1

A 1 1 0 0

B 1 0 1 0

F



Gate Logic: Positive vs. Negative Logic

Conversion from Positive to Negative Logic

Positive Logic NOR: A + B = A " B

Negative Logic NAND: A " B = A + B

Dual operations: AND becomes OR, OR becomes AND Complements remain unchanged

Negative Logic Positive Logic V oltage T ruth T able

F high low low low

F 1 0 0 0

F 0 1 1 1

A low low high high

B low high low high

B 0 1 0 1

A 0 0 1 1

A 1 1 0 0

B 1 0 1 0

F



(c)

Change Request

(active low)

T imer Expired

(active low)

Change Lights

(active low)

Bubble Mismatch

(d)

(a)

Change Request

(active high)

T imer Expired

(active high)

Change Lights

(active high)

Active High

(b)

Change Request

(active low)

T imer Expired

(active low)

Change Lights

(active low)

Active Low

Change Request

(active low)

T imer Expired

(active low)

Change Lights

(active low)

Bubble Match

Gate Logic: Positive vs. Negative LogicPractical Example

Mismatch betweeninput and outputlogic polarities

Use NAND w/ invertedinputs if negative logic

Use OR gate if inputpolarities are neg. logic

Use AND gateif active high



A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

W 0 0 0 0 0 0 0 1 1 0 X X X X X X

X 0 0 0 1 1 1 1 0 0 0 X X X X X X

Y 0 1 1 0 0 1 1 0 0 0 X X X X X X

Z 1 0 1 0 1 0 1 0 1 0 X X X X X X

Gate Logic: Incompletely Specified Functions

n input functions have 2 possible input configurations

for a given function, not all input configurations may be possible

this fact can be exploited during circuit minimization!

E.g., Binary Coded Decimal Digit Increment by 1BCD digits encode the decimal digits 0 - 9 in the bit patterns 0000 - 1001

n

2 2

These input patterns shouldnever be encountered in practise

associated output values are"Don't Cares"

Off-set of W

On-set of W

Don't care (DC) set of W



Gate Logic: Incompletely Specified FunctionsDon't Cares and Canonical Forms

Z = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 + d15

Z = ΣΣΣΣm(0, 2, 4, 6, 8) + d(10, 11, 12 ,13, 14, 15)

Z = M1 " M3 " M5 " M7 " M9 " D10 " D11 " D12 " D13 " D14 " D15

Z= ΠΠΠΠM(1, 3, 5, 7, 9) " D(10, 11, 12, 13, 14 ,15)

Canonical Representations of the BCD Increment by 1 Function:



Gate Logic: Two-Level Simplification

Algebraic Simplification:

not an algorithm/systematic procedure

how do you know when the minimum realization has been found?

Computer-Aided Tools:

precise solutions require very long computation times, especially for functions with many inputs (>10)

heuristic methods employed — "educated guesses" to reduce the amount of computation good solutions not best solutions

Still Relevant to Learn Hand Methods:

insights into how the CAD programs work, and their strengths and weaknesses

ability to check the results, at least on small examples

don't have computer terminals during exams



A 0 0 1 1

B 0 1 0 1

G 1 0 1 0

A 0 0 1 1

B 0 1 0 1

F 0 0 1 1


Key Tool: The Uniting Theorem — A (B' + B) = A

F = A B' + A B = A (B' + B) = A

A's values don't change within the on-set rows

B's values change within the on-set rows

G = A' B' + A B' = (A' + A) B' = B'

B's values stay the same within the on-set rows

A's values change within the on-set rows

B is eliminated, A remains

A is eliminated, B remains

Essence of Simplification:find two element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!



Gate Logic: Two-Level SimplificationBoolean Cubes

Visual technique for identifying when the Uniting Theorem can be applied

Just another way torepresent the truth table

n input variables =n dimensional "cube"

2-cube 3-cube

4-cube

XYZ

X

011

010

000

001

111

110

100

101 Y Z

WXYZ

0111 0011

0010

0000

0001

0110

1010

0101

0100 1000

1011

1001

1110

1111

1101

1100

Y Z

W

X

XY

1-cube

X

X

01

00

11

10

Y

0 1




Mapping Truth Tables onto Boolean Cubes

ON-set = filled-in nodes

OFF-set = empty nodes

DC-set = X'd nodes

F

G

A asserted and unchanged

B varies within loop

A varies within loop

B complemented and unchanged

Cube of n-1 dimensions

Reduced expression contains n-1 variables

01 11

10 00

B

A

01 11

10 00

A

B



A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A

B

Cin 0 1 0 1 0 1 0 1

Cout 0 0 0 1 0 1 1 1

011 111

010 110

001

000 100

101 Cin

Gate Logic: Two-Level SimplificationThree variable example: Full Adder Carry Out

(A' + A) B Cin

A B (Cin' + Cin)

A (B + B') Cin

Cout = B Cin + A B + A Cin

The ON-set is coveredby the OR of the subcubes

of lower dimensionality



011 111

101

100

110 010

001

000

B

C

A


Subcubes of Higher Dimensions than 2

F(A,B,C) = ΣΣΣΣm(4,5,6,7)

On-set forms a rectangle, i.e., a cube of two dimensions

represents an expression in one variable i.e., 3 dimensions - 2 dimensions

A is asserted and unchangedB and C vary

This subcube represents theliteral A




In a 3-cube:

a 0-cube, i.e., a single node, yields a term in three literals

a 1-cube, i.e., a line of two nodes, yields a term in two literals

a 2-cube, i.e., a plane of four nodes, yields a term in one literal

a 3-cube, i.e., a cube of eight nodes, yields a constant term "1"

In general,

an m-subcube within an n-cube (m < n) yields a term with n - m literals



A B 0 1

0

1

0

1

2

3

0

1

2

3

6

7

4

5

AB C

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

A

B

AB

CD

A

00 01 11 10

0

1

00 01 11 00

00

01

11

10 C

B

D

Gate Logic: Two-Level SimplificationKarnaugh Map Method

hard to draw cubes of more than 4 dimensions

K-map is an alternative method of representing the truth table that helps visualize adjacencies in up to 6 dimensions

Beyond that, computer-based methods are needed

2-variableK-map

3-variableK-map

4-variableK-map

Numbering Scheme: 00, 01, 11, 10Gray Code — only a single bit changes from code word to next code word



Gate Logic: Two-Level SimplificationKarnaugh Map Method

Adjacencies in the K-Map

Wrap from first to last column

Top row to bottom row

000

001

010

01 1

1 10

1 1 1

100

101

00 01 11 10

0

1

AB C

A

B

011

010

000

001

100

110

101

111

B

C

A



Gate Logic: Two-Level SimplificationK-Map Method Examples

F =

A asserted, unchangedB varies

G =

B complemented, unchangedA varies

Cout = F(A,B,C) =

A

B 0 1

0 1

0 1

0

1

A

B 0 1

1 1

0 0

0

1

A B A

B

Cin 00 01 11 10

0

1

0

0

0

1

1

1

0

1

AB C

A

00 01 11 10

0

1

0

0

0

0

1

1

1

1

B



Gate Logic: Two-Level SimplificationK-Map Method Examples

F = A

A asserted, unchangedB varies

G = B'

B complemented, unchangedA varies

Cout = A B + B Cin + A Cin F(A,B,C) = A

A

B 0 1

0 1

0 1

0

1

A

B 0 1

1 1

0 0

0

1

A B A

B

Cin 00 01 11 10

0

1

0

0

0

1

1

1

0

1

AB C

A

00 01 11 10

0

1

0

0

0

0

1

1

1

1

B




More K-Map Method Examples, 3 Variables

F(A,B,C) = ΣΣΣΣm(0,4,5,7)

F =

F'(A,B,C) = ΣΣΣΣm(1,2,3,6)

F' =

F' simply replace 1's with 0's and vice versa

00 C

AB 01 11 10

1 0 0 1

1 1 0 0

A

B

0

1

00 C

AB

01 11 10

0 1 1 0

0 0 1 1

A

B

0

1




More K-Map Method Examples, 3 Variables

F(A,B,C) = ΣΣΣΣm(0,4,5,7)

F = B' C' + A C

In the K-map, adjacency wraps from left to rightand from top to bottom

F'(A,B,C) = ΣΣΣΣm(1,2,3,6)

F' = B C' + A' C

Compare with the method of using DeMorgan's Theorem and Boolean Algebra to reduce the complement!

F' simply replace 1's with 0's and vice versa

00 C

AB 01 11 10

1 0 0 1

1 1 0 0

A

B

0

1

00 C

AB

01 11 10

0 1 1 0

0 0 1 1

A

B

0

1




K-map Method Examples: 4 variables

F(A,B,C,D) = ΣΣΣΣm(0,2,3,5,6,7,8,10,11,14,15)

F =

AB 00 01 11 10

1 0 0 1

0 1 0 0

1 1 1 1

1 1 1 1

00

01

11

10 C

CD

A

D

B




K-map Method Examples: 4 variables

F(A,B,C,D) = ΣΣΣΣm(0,2,3,5,6,7,8,10,11,14,15)

F = C + A' B D + B' D'

K-map Corner AdjacencyIllustrated in the 4-Cube

Find the smallest numberof the largest possible

subcubes that cover theON-set

AB 00 01 11 10

1 0 0 1

0 1 0 0

1 1 1 1

1 1 1 1

00

01

11

10 C

CD

A

D

B

0011

D

0010

0000

0111

0110

0001 C

A

B 0100 1000

1100

1101

1111

1110

1001

1011

1010

0101




K-map Method: Circling Zeros

AB 00 01 11 10

1 0 0 1

0 1 0 0

1 1 1 1

1 1 1 1

00

01

11

10 C

CD

A

D

B

F = (B + C + D) (A + C + D) (B + C + D)

F = B C D + A C D + B C D

F = B C D + A C D + B C D

F = (B + C + D) (A + C + D) (B + C + D)

Replace F by F, 0’s become 1’s and vice versa




K-map Example: Don't Cares

F(A,B,C,D) = ΣΣΣΣm(1,3,5,7,9) + ΣΣΣΣd(6,12,13)

F = w/o don't cares

F = w/ don't cares

Don't Cares can be treated as 1's or 0's if it is advantageous to do so

AB 00 01 11 10

0 0 X 0

1 1 X 1

1 1 0 0

0 X 0 0

00

01

11

10 C

CD

A

D

B




K-map Example: Don't Cares

F(A,B,C,D) = ΣΣΣΣm(1,3,5,7,9) + ΣΣΣΣd(6,12,13)

F = A'D + B' C' D w/o don't cares

F = C' D + A' D w/ don't cares

Don't Cares can be treated as 1's or 0's if it is advantageous to do so

By treating this DC as a "1", a 2-cubecan be formed rather than one 0-cube

AB 00 01 11 10

0 0 X 0

1 1 X 1

1 1 0 0

0 X 0 0

00

01

11

10 C

CD

A

D

B AB

00 01 11 10

0 0 X 0

1 1 X 1

1 1 0 0

0 X 0 0

00

01

11

10 C

CD

A

D

B

In PoS form: F = D (A' + C')

Same answer as above, but fewer literals



Gate Logic: Two-Level SimplificationDesign Example: Two Bit Comparator

Block Diagramand

Truth Table

A 4-Variable K-mapfor each of the 3output functions

F 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

F 2 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

F 3 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

B 0 1 0 1

A 0 0 1 1

=, >, < F 1 A B = C D F 2 A B < C D F 3 A B > C D

A B

C D

N 1

N 2



Gate Logic: Two-Level SimplificationDesign Example: Two Bit Comparator

F1 =

F2 =

F3 =

AB 00 01 11 10

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

00

01

11

10 C

CD

A

D

B

K-map for F 1

AB 00 01 11 10

0 0 0 0

1 0 0 0

1 1 0 1

1 1 0 0

00

01

11

10 C

CD

A

D

B

K-map for F 2

AB 00 01 11 10

0 1 1 1

0 0 1 1

0 0 0 0

0 0 1 0

00

01

11

10 C

CD

A

D

B

K-map for F 3



Gate Logic:Two-Level SimplificationDesign Example: Two Bit Comparator

F1 = A' B' C' D' + A' B C' D + A B C D + A B' C D'

F2 = A' B' D + A' C

F3 = B C' D' + A C' + A B D'

A xnor B xnor C xnor D

AB 00 01 11 10

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

00

01

11

10 C

CD

A

D

B

K-map for F 1

AB 00 01 11 10

0 0 0 0

1 0 0 0

1 1 0 1

1 1 0 0

00

01

11

10 C

CD

A

D

B

K-map for F 2

AB 00 01 11 10

0 1 1 1

0 0 1 1

0 0 0 0

0 0 1 0

00

01

11

10 C

CD

A

D

B

K-map for F 3




Design Example: Two Bit Adder

Block Diagramand

Truth Table

A 4-variable K-mapfor each of the 3output functions

+ N 3

X 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1

Y 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1

Z 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

B 0 1 0 1

A 0 0 1 1

A B

C D

N 1

N 2

X Y Z



Gate Logic: Two-Level SimplificationDesign Example (Continued)

X =

Z =

Y =

AB 00 01 11 10

0 0 0 0

0 0 1 0

0 1 1 1

0 0 1 1

00

01

11

10 C

CD

A

D

B

K-map for X

AB 00 01 11 10

0 0 1 1

0 1 0 1

1 0 1 0

1 1 0 0

00

01

11

10 C

CD

A

D

B

K-map for Y

AB 00 01 11 10

0 1 1 0

1 0 0 1

1 0 0 1

0 1 1 0

00

01

11

10 C

CD

A

D

B

K-map for Z




X = A C + B C D + A B D

Z = B D' + B' D = B xor D

Y = A' B' C + A B' C' + A' B C' D + A' B C D' + A B C' D' + A B C D

= B' (A xor C) + A' B (C xor D) + A B (C xnor D)

= B' (A xor C) + B (A xor B xor C)gate countreduced if

XOR available

1's on diagonal suggest XOR!Y K-Map not minimal as drawn

AB 00 01 11 10

0 0 0 0

0 0 1 0

0 1 1 1

0 0 1 1

00

01

11

10 C

CD

A

D

B

K-map for X

AB 00 01 11 10

0 0 1 1

0 1 0 1

1 0 1 0

1 1 0 0

00

01

11

10 C

CD

A

D

B

K-map for Y

AB 00 01 11 10

0 1 1 0

1 0 0 1

1 0 0 1

0 1 1 0

00

01

11

10 C

CD

A

D

B

K-map for Z



\ D \ A \ C

Y 1

A

C

D

\ B

B

Y 2


Two alternativeimplementations of Ywith and without XOR

Note: XOR typicallyrequires 4 NAND gates

to implement!

X XOR Y

X

Y



Gate Logic: Two-Level SimplificationDesign Example: BCD Increment By 1

W =

X =

Y =

Z =

AB 00 01 11 10

0 0 X 1

0 0 X 0

0 1 X X

0 0 X X

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

0 1 X 0

0 1 X 0

1 0 X X

0 1 X X

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

0 0 X 0

1 1 X 0

0 0 X X

1 1 X X

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

1 1 X 1

0 0 X 0

0 0 X X

1 1 X X

00

01

11

10 C

CD

A

D

B

Z Y

X W




W = B C D + A D'

X = B C' + B D' + B' C D

Y = A' C' D + C D'

Z = D'

AB 00 01 11 10

0 0 X 1

0 0 X 0

0 1 X X

0 0 X X

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

0 1 X 0

0 1 X 0

1 0 X X

0 1 X X

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

0 0 X 0

1 1 X 0

0 0 X X

1 1 X X

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

1 1 X 1

0 0 X 0

0 0 X X

1 1 X X

00

01

11

10 C

CD

A

D

B

Z Y

X W



Gate Logic: Two Level SimplificationDefinition of Terms

implicant : single element of the ON-set or any group of elements that can be combined together in a K-map

prime implicant : implicant that cannot be combined with another implicant to eliminate a term

essential prime implicant : if an element of the ON-set is covered by a single prime implicant, it is an essential prime

Objective:

grow implicants into prime implicants

cover the ON-set with as few prime implicants as possible

essential primes participate in ALL possible covers



Gate Logic: Two Level Simplication

Examples to Illustrate Terms

6 Prime Implicants:

A' B' D, B C', A C, A' C' D, A B, B' C D

essential

Minimum cover = B C' + A C + A' B' D

5 Prime Implicants:

B D, A B C', A C D, A' B C, A' C' D

essential

Essential implicants form minimum cover

AB 00 01 11 10

0 1 1 0

1 1 1 0

1 0 1 1

0 0 1 1

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

0 0 1 0

1 1 1 0

0 1 1 1

0 1 0 0

00

01

11

10 C

CD

A

D

B



Gate Logic: Two Level Simplification

More Examples

Prime Implicants:

B D, C D, A C, B' C

essential

Essential primes form the minimum cover

AB 00 01 11 10

0 0 0 0

0 1 1 0

1 1 1 1

1 0 1 1

00

01

11

10 C

CD

A

D

B



Gate Logic: Two-Level SimplificationAlgorithm: Minimum Sum of Products Expression from a K-Map

Step 1: Choose an element of ON-set not already covered by an implicant

Step 2: Find "maximal" groupings of 1's and X's adjacent to that element.Remember to consider top/bottom row, left/right column, andcorner adjacencies. This forms prime implicants (always a powerof 2 number of elements).

Repeat Steps 1 and 2 to find all prime implicants

Step 3: Revisit the 1's elements in the K-map. If covered by single primeimplicant, it is essential , and participates in final cover. The 1's itcovers do not need to be revisited

Step 4: If there remain 1's not covered by essential prime implicants, thenselect the smallest number of prime implicants that cover theremaining 1's



Gate Logic: Two Level SimplificationExample: ƒ(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)

Initial K-map

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B




Initial K-map Primes aroundA' B C' D'

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B




Initial K-map Primes aroundA' B C' D'

Primes aroundA B C' D

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B



Gate Logic: Two-Level SimplificationExample Continued


AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B




Primes aroundA B' C' D'


AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B




Primes aroundA B' C' D'


AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B

AB 00 01 11 10

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1

00

01

11

10 C

CD

A

D

B

Essential Primeswith Min Cover




5-Variable K-maps

ƒ(A,B,C,D,E) = ΣΣΣΣm(2,5,7,8,10,13,15,17,19,21,23,24,29 31)

=

BC DE

BC DE

A =0

A =1

00 01 11 10 00

01

11

10

00 01 11 10 00

01

11

10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

16 20 28 24

17 21 29 25

19 23 31 27

18 22 30 26

1

00

1

10

1

10 BC

DE 00 01 11

00

01

11

10

A=0

BC DE 00 01 11

01

11

10

A=1

1 1

1

1 1

1

1 1

1 1 1




5-Variable K-maps

ƒ(A,B,C,D,E) = ΣΣΣΣm(2,5,7,8,10,13,15,17,19,21,23,24,29 31)

= C E + A B' E + B C' D' E' + A' C' D E'

BC DE 00 01 11 10

00

01

11

10

A=0

BC DE 00 01 11 10

00

01

11

10

A=1

1 1

1

1

1 1

1

1

1 1 1

1 1 1

BC DE

BC DE

A =0

A =1

00 01 11 10 00

01

11

10

00 01 11 10 00

01

11

10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

16 20 28 24

17 21 29 25

19 23 31 27

18 22 30 26



Gate Logic: Two Level Simplification6- Variable K-Maps

ƒ(A,B,C,D,E,F) =ΣΣΣΣm(2,8,10,18,24,

26,34,37,42,45,50,53,58,61)

=

CD EF

CD EF

AB =00

AB =01

00 01 11 10 00

01

11

10

00 01 11 10 00

01

11

10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

16 20 28 24

17 21 29 25

19 23 31 27

18 22 30 26

CD EF

AB =11

00 01 11 10 00

01

11

10

48 52 60 56

49 53 61 57

51 55 63 59

50 54 62 58

CD EF

AB =10

00 01 11 10 00

01

11

10

32 36 44 40

33 37 45 41

35 39 47 43

34 38 46 42

CD EF

CD EF

AB =00

AB =01

00 01 11 10 00

01

11

10

00 01 11 10 00

01

11

10

CD EF

AB =11

00 01 11 10 00

01

11

10

CD EF

AB =10

00 01 11 10 00

01

11

10

1

1 1

1

1 1

1 1

1 1

1 1

1 1



Gate Logic: Two Level Simplification6- Variable K-Maps

ƒ(A,B,C,D,E,F) =ΣΣΣΣm(2,8,10,18,24,

26,34,37,42,45,50,53,58,61)

= D' E F' + A D E' F+ A' C D' F'

CD EF

CD EF

AB =00

AB =01

00 01 11 10 00

01

11

10

00 01 11 10 00

01

11

10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

16 20 28 24

17 21 29 25

19 23 31 27

18 22 30 26

CD EF

AB =11

00 01 11 10 00

01

11

10

48 52 60 56

49 53 61 57

51 55 63 59

50 54 62 58

CD EF

AB =10

00 01 11 10 00

01

11

10

32 36 44 40

33 37 45 41

35 39 47 43

34 38 46 42

CD EF

CD EF

AB =00

AB =01

00 01 11 10 00

01

11

10

00 01 11 10 00

01

11

10

CD EF

AB =11

00 01 11 10 00

01

11

10

CD EF

AB =10

00 01 11 10 00

01

11

10

1

1 1

1

1 1

1 1

1 1

1 1

1 1



Gate Logic: CAD Tools for SimplificationQuine-McCluskey Method

Tabular method to systematically find all prime implicants

Implication Table

Column I 0000 0100 1000 0101 0110 1001 1010 0111 1101

1111

ƒ(A,B,C,D) = ΣΣΣΣm(4,5,6,8,9,10,13) + ΣΣΣΣd(0,7,15)

Step 1: Fill Column 1 with ON-set and DC-set minterm indices. Group by number of 1's.

Stage 1: Find all prime implicants





Implication Table

Column I Column II 0000 ¦ 0-00 -000 0100 ¦ 1000 ¦ 010- 01-0 0101 ¦ 100- 0110 ¦ 10-0 1001 ¦ 1010 ¦ 01-1 -101 0111 ¦ 011- 1101 ¦ 1-01

1111 ¦ -111 11-1



Step 2: Apply Uniting Theorem— Compare elements of group w/ N 1's against those with N+1 1's. Differ by one bit implies adjacent. Eliminate variable and place in next column.

E.g., 0000 vs. 0100 yields 0-00 0000 vs. 1000 yields -000

When used in a combination, mark with a check. If cannot be combined, mark with a star. These are the prime implicants.

Repeat until no further combinations can be made.






Implication Table

Column I Column II Column III 0000 ¦ 0-00 * 01-- * -000 * 0100 ¦ -1-1 * 1000 ¦ 010- ¦ 01-0 ¦ 0101 ¦ 100- * 0110 ¦ 10-0 * 1001 ¦ 1010 ¦ 01-1 ¦ -101 ¦ 0111 ¦ 011- ¦ 1101 ¦ 1-01 *

1111 ¦ -111 ¦ 11-1 ¦



Step 2: Apply Uniting Theorem— Compare elements of group w/ N 1's against those with N+1 1's. Differ by one bit implies adjacent. Eliminate variable and place in next column.

E.g., 0000 vs. 0100 yields 0-00 0000 vs. 1000 yields -000

When used in a combination, mark with a check. If cannot be combined, mark with a star. These are the prime implicants.

Repeat until no further combinations can be made.




Gate Logic: CAD Tools for SimplificationQuine-McCluskey Method Continued

Prime Implicants:

0-00 = A' C' D'

100- = A B' C'

1-01 = A C' D

-1-1 = B D

-000 = B' C' D'

10-0 = A B' D'

01-- = A' B

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1



Gate Logic: CAD Tools for SimplificationQuine-McCluskey Method Continued

Prime Implicants:

0-00 = A' C' D'

100- = A B' C'

1-01 = A C' D

-1-1 = B D

-000 = B' C' D'

10-0 = A B' D'

01-- = A' B

Stage 2: find smallest set of prime implicants that cover the ON-set

recall that essential prime implicants must be in all covers

another tabular method– the prime implicant chart

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

X 1 0 1

0 1 1 1

0 X X 0

0 1 0 1



Gate Logic: CAD Tools for Simplification

rows = prime implicantscolumns = ON-set elementsplace an "X" if ON-set element is covered by the prime implicant

Prime Implicant Chart




rows = prime implicantscolumns = ON-set elementsplace an "X" if ON-set element is covered by the prime implicant

Prime Implicant Chart

If column has a single X, than theimplicant associated with the rowis essential. It must appear inminimum cover



Gate Logic: CAD Tools for SimplificationPrime Implicant Chart (Continued)

Eliminate all columns covered byessential primes



Gate Logic: CAD Tools for SimplificationPrime Implicant Chart (Continued)

Eliminate all columns covered byessential primes

Find minimum set of rows thatcover the remaining columns

ƒ = A B' D' + A C' D + A' B



Gate Logic: CAD Tools for SimplificationESPRESSO Method

Problem with Quine-McCluskey: the number of prime implicants grows rapidly with the number of inputs

upper bound: 3 /n, where n is the number of inputsn

finding a minimum cover is NP-complete, i.e., a computational expensive process not likely to yield to any efficient algorithm

Espresso: trades solution speed for minimality of answer

don't generate all prime implicants (Quine-McCluskey Stage 1)

judiciously select a subset of primes that still covers the ON-set

operates in a fashion not unlike a human finding primes in a K-map




Espresso Method: Overview

1. Expands implicants to their maximum sizeImplicants covered by an expanded implicant are removed from further considerationQuality of result depends on order of implicant expansionHeuristic methods used to determine orderStep is called EXPAND

Irredundant cover (i.e., no proper subset is also a cover) is extracted from the expanded primesJust like the Quine-McCluskey Prime Implicant ChartStep is called IRREDUNDANT COVER

Solution usually pretty good, but sometimes can be improvedMight exist another cover with fewer terms or fewer literalsShrink prime implicants to smallest size that still covers ON-setStep is called REDUCE

Repeat sequence REDUCE/EXPAND/IRREDUNDANT COVER to find alternative prime implicantsKeep doing this as long as new covers improve on last solution

A number of optimizations are tried, e.g., identify and remove essential primes early in the process

2.

3.

4.

5.



Gate Logic: CAD Tools for SimplificationEspresso Inputs and Outputs

.i 4

.o 1

.ilb a b c d

.ob f

.p 100100 10101 10110 11000 11001 11010 11101 10000 -0111 -1111 -.e

-- # inputs-- # outputs-- input names-- output name-- number of product terms-- A'BC'D'-- A'BC'D-- A'BCD'-- AB'C'D'-- AB'C'D-- AB'CD'-- ABC'D-- A'B'C'D' don't care-- A'BCD don't care-- ABCD don't care-- end of list

ƒ(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0,7,15)

Espresso Input Espresso Output

.i 4

.o 1

.ilb a b c d

.ob f

.p 31-01 110-0 101-- 1.e

ƒ = A C' D + A B' D' + A' B




Espresso: Why Iterate on Reduce, Irredundant Cover, Expand?

Initial Set of Primes found bySteps1 and 2 of the Espresso

Method

4 primes, irredundant cover,but not a minimal cover!

Result of REDUCE:Shrink primes while still

covering the ON-set

Choice of order in which to perform shrink is important

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 0 0

1 1 1 1

0 0 1 1

1 1 1 1

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 0 0

1 1 1 1

0 0 1 1

1 1 1 1



Gate Logic: CAD Tools for SimplificationEspresso Iteration (Continued)

Second EXPAND generates adifferent set of prime implicants

IRREDUNDANT COVER found byfinal step of espresso

Only three prime implicants!

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 0 0

1 1 1 1

0 0 1 1

1 1 1 1

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 0 0

1 1 1 1

0 0 1 1

1 1 1 1



Two-Level Logic: Summary

Primitive logic building blocksINVERTER, AND, OR, NAND, NOR, XOR, XNOR

Canonical FormsSum of Products, Products of Sums

Incompletely specified functions/don't cares

Logic MinimizationGoal: two-level logic realizations with fewest gates and fewest number of gate inputs

Obtained via Laws and Theorems of Boolean Algebra

or Boolean Cubes and the Uniting Theorem

or K-map Methods up to 6 variables

or Quine-McCluskey Algorithm

or Espresso CAD Tool

Contemporary Logic DesignMulti-Level Logic


Chapter # 3: Multi-Level Combinational Logic



June 1993



Chapter Overview

" Multi-Level Logic

Conversion to NAND-NAND and NOR-NOR Networks

DeMorgan's Law and Pushing Bubbles

AND-OR-Invert Building Blocks

CAD Tools for Multi-Level Optimization

" Time Response in Combinational Networks

Gate Delays and Timing Waveforms

Hazards/Glitches and How To Avoid Them



Multi-Level Logic: Advantages

Reduced sum of products form:

x = A D F + A E F + B D F + B E F + C D F + C E F + G

6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires)

1

2

3

4

5

6

7

1

2 3 4

A

A

A

B

B

B

C

C

C

D

D

D

D

E

E

E

E

F

F

F

F

F

F

F

G

G

x x

Factored form:

x = (A + B + C) (D + E) F + G

1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)



Multi-Level Logic: Conversion of Forms

NAND-NAND and NOR-NOR Networks

DeMorgan's Law: (A + B)' = A' " B'; (A " B)' = A' + B'

Written differently: A + B = (A' " B')'; (A " B) = (A' + B')'

In other words, OR is the same as NAND with complemented inputs AND is the same as NOR with complemented inputs NAND is the same as OR with complemented inputs NOR is the same as AND with complemented inputs

OR/NANDEquivalence

A A B B

A 0 0 1 1

A 1 1 0 0

B 0 1 0 1

B 1 0 1 0

A + B 0 1 1 1

A • B 0 1 1 1 A A

B B

A + B 1 1 1 0

A • B 1 1 1 0

≡

≡

OR OR

Nand Nand



Mult -Level Logic: Conversion Between Forms

AND/NOREquivalence

It is possible to convert from networks with ANDs and ORs to networks with NANDs and NORs by introducing the appropriate inversions ("bubbles")

To preserve logic levels, each introduced "bubble" must be matched with a corresponding "bubble"

A A B B

A 0 0 1 1

A 1 1 0 0

B 0 1 0 1

B 1 0 1 0

A • B 0 0 0 1

A + B 0 0 0 1 A A

B B

A • B 1 0 0 0

A + B 1 0 0 0

≡

≡

AND AND

NOR NOR



A A B B

C C D D

A B

C D

A B

C D


Example: Map AND/OR network to NAND/NAND network

NAND

NAND

NAND

AND

AND

OR

NAND

NAND

NAND

(A)

(C)

(B)

(D)




Example: Map AND/OR network to NAND/NAND network

Z = [(A"B)' (C"D)']'

= [(A' + B') (C' + D')]'

= [(A' + B')' " (C' + D')']

= (A " B) + (C " D) ¦

Verify equivalenceof the two forms

This is the easy conversion!

NAND

NAND

NAND

AA

BB

CC

DD

ZZ



Multi-Level Logic: Mapping Between FormsExample: Map AND/OR network to NOR/NOR network

Step 1 Step 2

NOR

NOR

Conserve"Bubbles"

NOR

NOR

NOR

Conserve"Bubbles"


Z =

A \A

B\B

C

\CD

\D

ZZ



Multi-Level Logic: Mapping Between FormsExample: Map AND/OR network to NOR/NOR network

Step 1 Step 2Conserve"Bubbles"

Conserve"Bubbles"


Z = {[(A' + B')' + (C' + D')']'}'

= {(A' + B') " (C' + D')}'

= (A' + B')' + (C' + D')'

= (A " B) + (C " D) ¦

This is the hard conversion! AND/OR to NAND/NAND more natural

NOR

NOR

NOR

NOR

NOR

A \A

B\B

C

\CD

\D

ZZ



Multi-Level Logic: Mapping Between Forms

Example: Map OR/AND network to NOR/NOR network

NOR

NOR

NOR

ConserveBubbles


Z =




Example: Map OR/AND network to NOR/NOR network

NOR

NOR

NOR

ConserveBubbles


Z = [(A + B)' + (C + D)']'

= {(A + B)'}' " {(C + D)'}'

= (A + B) " (C + D) ¦

This is the easy conversion!




Example: Map OR/AND network to NAND/NAND network

Step 1 Step 2

Nand

NandNand

Nand

Nand

ConserveBubbles!

ConserveBubbles!


Z =




Example: Map OR/AND network to NAND/NAND network

This is the hard conversion! OR/AND to NOR/NOR more natural

Step 1 Step 2

Nand

NandNand

Nand

Nand

ConserveBubbles!

ConserveBubbles!


Z = {[(A' " B')' " (C' " D')']'}'

= {(A' " B') + (C' " D')}'

= (A' " B')' " (C' " D')'

= (A + B) " (C + D) ¦



Multi-Level Logic: More than Two Levels

ƒ = A (B + C D) + B C'

OriginalAND-OR Network

Introduction and Conservation of Bubbles

Redrawn in termsof conventional

NAND Gates

C

Level 1 Level 2 Level 3 Level 4

G1 D

B

A F G5 G4

G3

B G2 \ C

C G1 D

B

A

F G5 G4 G3

B G2 \ C

C G1 D

\B A

F G5 G4 G3

B G2 \ C



Multi-Level Logic: More than Two Levels

Same beginning networkafter introduction of

bubbles

Final network, redrawnin NOR-only form

C

Level 1 Level 2 Level 3 Level 4

G1 D

B

A

F G5 G4 G3

\B

C G2

\ C G1 \ D

B \ A

F G5 G4 G3

B \ C

G2



A

B C

D

F

A

B C

\D

F

X

\ X

(a) (b)

A

B C

D

F X

(d)

A

B C

\ D

F

(c)

\ X

X

Multi-Level Logic: More than Two-LevelsConversion Example

Original circuit Add double bubbles at inputs

Distribute bubblessome mismatches

Insert inverters to fix mismatches



Multi-Level Logic: AND-OR-Invert Block

AOI Function: Three stage logic— AND, OR, Invert Multiple gates "packaged" as a single circuit block

AND OR Invert

logical concept possible switch implementation

two-input two-stack

&

&

+2x2 AOI SchematicSymbol

&

&

+3x2 AOI SchematicSymbol

A B

C D

Z

T rue A C

B D Z

False

A B

C D



Multi-Level Logic: AND-OR-Invert

Example: XOR implementation

A xor B = A' B + A B'

= ( ? )'

(A' B + A B')'

(A + B') (A' + B)

(A B + A' B')

AOI form

General procedure to place in AOI form:

Compute the complement in Sum of Products form by circling the 0's in the K-map!

ƒ = (A' B' + A B)'



Multi-Level Logic: AND-OR-Invert

F = B C' + A C' + A B

F' = A' B' + A' C + B' C

Implemented by 2-input 3-stack AOI gate

F = (A + B) (A + C') (B + C')

F' = (B' + C) (A' + C) (A' + B')

Implemented by 2-input 3-stack OAI gate

Example:

Example:4-bit Equality Function

Z = (A0 B0 + A0' B0') (A1 B1 + A1' B1') (A2 B2 + A2' B2') (A3 B3 + A3' B3')

Each implemented in single 2x2 AOI gate

10

1

1

0 0 0

0 1 1

B

11 01 00 AB A

C 0

1

F' K-map



Multi-Level Logic: AND-OR-InvertExample: AOI Implementation of a 4-Bit Equality Tester

High if A0 ° B0, Low if A0 = B0A = B active low

NOR

If all inputs are low (asserted in negative logic) then Ai = Bi, i=0,...,3Output Z asserted

Conservation of bubbles



Multi-Level Logic: CAD Tools for Simplification

Multi-Level Optimization:1. Factor out common sublogic (reduce fan-in, increase gate levels), subject to timing constraints

2. Map factored form onto library of gates

3. Minimize number of literals (correlates with number of wires)

Factored Form:sum of products of sum of products . . .

X = (A B + B' C) (C + D (E + A C')) + (D + E)(F G)

A

B B

C C

D

E

A

C

F

G D

E

F 1

F 2

F 5 F 4

F 3

X

+

+

+

+

+

•

• • •

•

• •




Operations on Factored Forms:" Decompostion

" Extraction

" Factoring

" Substitution

" Collapsing

Manipulate network by interactivelyissuing the appropriate instructions

There exists no algorithm that guarantees"optimal" multi-level network will be obtained



Multi-Level Logic: CAD Tools for SimplificationDecomposition:

Take a single Boolean expression and replace with collection of new expressions:

F = A B C + A B D + A' C' D' + B' C' D'

F rewritten as:

F = X Y + X' Y' X = A B Y = C + D

(12 literals)

(4 literals)

Before Decomposition After Decomposition

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Extraction: common intermediate subfunctions are factored out

F = (A + B) C D + EG = (A + B) E'H = C D E

can be re-written as:

F = X Y + EG = X E'H = Y EX = A + BY = C D

(11 literals)

(7 literals)

"Kernels": primary divisors

Before Extraction After Extraction

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Multi-Level Logic: CAD Tools for SimplificationFactoring: expression in two level form re-expressed in multi-level form

F = A C + A D + B C + B D + E

can be rewritten as:

F = (A + B) (C + D) + E

(9 literals)

(5 literals)

Before Factoring After Factoring

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Substitution: function G into function F, express F in terms of G

F = A + B C G = A + B

F rewritten in terms of G:

F = G (A + C)

Collapsing: reverse of substitution; use to eliminate levels to meet timing constraints

F = G (A + C) = (A + B) (A + C) = A A + A C + A B + B C = A + B C ¦

(5 literals)

(2 literals)




Key to implementing these operations: "division" over Boolean functions

F = P Q + R

divisor quotient remainder

example:X = A C + A D + B C + B D + EY = A + B

X "divided" by Y is—X = Y (C + D) + E

Complexity: finding suitable divisorsF = A D + B C D + EG = A + B

G does not divide F under algebraic division rulesG does divide F under Boolean rules (very large number of these!)

F/G = (A + C) D F = [G (A + C) D] + E = (A + B) (A + C) D + E = (A A + A C + A B + B C) D + E = (A + B C) D + E = A D + B C D + E ¦

F written as G Q + R




misII Session with the Full Adder

% misIIUC Berkeley, MIS Release #2.1 (compiled 3-Mar-89 at 5:32 PM)misII> re full.addermisII> p {co} = a b ci + a b ci' + a b' ci + a' b ci {sum} = a b ci + a b' ci' + a' b ci' + a' b' cimisII> pf {co} = a b' ci + b (ci (a' + a) + a ci') {sum} = ci (a' b' + a b) + ci' (a b' + a' b)misII> sim1 *misII> p {co} = a b + a ci + b ci {sum} = a b ci + a b' ci' + a' b ci' + a' b' cimisII> pf {co} = ci (b + a) + a b {sum} = ci (a' b' + a b) + ci' (a b' + a' b)misII> gd *misII> pf {co} = a [2] + b ci {sum} = a' [3]' + a [3] [2] = ci + b [3] = b' ci' + b ci

read eqntott equations

two level minimization

good decomposition

technology independent up to this point




misII> rlib msu.genlibmisII> mapmisII> pf [361] = b' ci' + a' [328] = b' [329] = ci' {co} = [328]' [329]' + [361]' [3] = b ci' + b' ci {sum} = [3] a' + [3]' amisII> pg[361] 1890:physical 32.00[328] 1310:physical 16.00[329] 1310:physical 16.00{co} 1890:physical 32.00[3] 2310:physical 40.00{sum} 2310:physical 40.00 misII> pat ... using library delay model{sum} : arrival=( 2.2 2.2) {co} : arrival=( 2.2 2.2) [328] : arrival=( 1.2 1.2) [361] : arrival=( 1.2 1.2) [329] : arrival=( 1.2 1.2) [3] : arrival=( 1.2 1.2) ci : arrival=( 0.0 0.0) b : arrival=( 0.0 0.0) a : arrival=( 0.0 0.0) misII> quit%

read library & perform technology mapping

gates that implement thevarious nodes and their

relative areas

timing simulationunit delay plus 0.2 time units

per fan-out




misII and the MSU gate libraryVLSI Standard Cells

Number Name Function1310 inv A'

1120 nor2 (A+B)'1130 nor3 (A+B+C)'1140 nor4 (A+B+C+D)'

1220 nand2 (A"B)'1230 nand3 (A"B"C)'1240 nand4 (A"B"C"D)'

1660 and2/nand2 [A"B, (A"B)']1670 and3/nand3 [A"B"C, (A"B"C)']1680 and4/nand4 [A"B"C"D, (A"B"C"D)']

1760 or2/nor2 [A+B, (A+B)']1770 or3/nor3 [A+B+C, (A+B+C)']1780 or4 (A+B+C+D)

1870 aoi22 (A"B + C"D)'1880 aoi21 (A + B"C)'1860 oai22 [(A + B)(C + D)]'1890 oai21 [A (B + C)]'

1970 ao22 A"B + D"E1810 ao222 A"B + C"D + E"F1910 ao2222 A"B + C"D + E"F + G"H1930 ao33 A"B"C + D"E"F

2310 xor2 A"B' + A'"B2350 xnor2 A"B + A'"B'

NOTE: OR-AND-INVERTequivalent to INVERT-AND-OR

B CI

[3]

2310

SUM

CO

1890

+ &

[361]

1890

& +

A

A

B CI

[328]

[329] 1310

1310

B

CI

2310



Multi-Level Logic: CAD Tools for SimplificationMore Examples

mis with standard simplification script:

misII -f script -t pla <espresso truth table file>

Full Adder:.model full.adder.inputs a b ci.outputs sum co.names a b ci co sum1--0 1-1-0 1--10 1111- 1.names a b ci co11- 11-1 1-11 1.end

mis pla style outputs

input variables

output variable

SUM = A CO' + B CO' + CI CO' + A B CI (9 literals)

CO = A B + A CI + B CI (6 literals)

Note that A xor B xor CI = A' B' CI + A B' CI' + A' B CI' + A B CI (12 literals!)




Multilevel Implementation of Full Adder: 5 Logic Levels!

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A

A

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Multi-Level Logic: Tools for SimplicationTwo-bit Adder

.inputs a b c d

.outputs x y z

.names a c z [22] x---1 111-- 1-10- 1.names a b c d x z [22] y1---0-- 1--1---1 1-11-0-- 1--110-- 1---100- 1.names a b c d z-0-1 1-1-0 10-10 1.names a d z [22]110 1.end

Z = B' D + B D' + A' C D'

[22] = A D Z'

X = [22] + A C + C Z'

Y = A X + C [22] + B C X' + C D X' + D X' Z'

8 logic levels!

Mis Output

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B

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C

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Multi-Level Logic: CAD Tools for Simplication

BCD Increment By 1

.model bcd.increment

.inputs a b c d

.outputs w x y z

.names a b c d z w1---1 10111- 1.names a b c w z x01-0- 10-100 1.names a c z y-11 1000 1.names a b c d z0--0 1-000 1.end

Mis Output

Z = A' D' + B' C' D'

Y = C Z + A' C' Z'

W = A Z + A' B C D

X = A' B W' + A' C W' Z'

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Time Response in Combinational Networks

" emphasis on timing behavior of circuits

" waveforms to visualize what is happening

" simulation to create these waveforms

" momentary change of signals at the outputs: hazards can be useful— pulse shaping circuits can be a problem — glitches: incorrect circuit operation

Terms:

gate delay— time for change at input to cause change at output minimum delay vs. typical/nominal delay vs. maximum delay careful designers design for the worst case!

rise time— time for output to transition from low to high voltage

fall time— time for output to transition from high to low voltage



Time Response in Combinational NetworksPulse Shaping Circuit

A' " A = 0

F is not always 0!

3 gate delays

D remains high forthree gate delays after

A changes from low to high



Time Response in Combinational NetworksAnother Pulse Shaping Circuit

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Hazards/Glitches and How to Avoid Them

Unwanting switching at the outputs

Occur because delay paths through the circuit experience different propagation delays

Danger if logic "makes a decision" while output is unstable OR hazard output controls an asynchronous input (these respond immediately to changes rather than waiting for a synchronizing signal called a clock )

Usual solutions: wait until signals are stable (by using a clock)

never, never, never use circuits with asynchronous inputs

design hazard-free circuits

Suggest that first two approaches be used, but we'll tell you about hazard-free design anyway!



Time Response in Combinational NetworksHazards/Glitches and How to Avoid Them

Kinds of Hazards

Input change causes output to go from 1 to 0 to 1

Input change causes output to go from 0 to 1 to 0

Input change causes a double change from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0

Static 0-hazard

Dynamic hazards

Static 1-hazard

1 1

0

1

0 0

1

0 0

1

1 1

0 0



Time Response in Combinational CircuitsGlitch Example

F = A' D + A C'

input change within product term

input change that spans product termsoutput changes from 1 to 0 to 1

G1

G2

G3

A\C

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G1

G2

G3

A\C

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�� F

1

1

1

1

0

0

0

1

1

1

1

0

0

0

ABCD = 1100 ABCD = 1101

G1

G2

G3

A\C

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G1

G2

G3

A\C

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�� F

0

1

0

0

1

0

0

1

1

1

1

1

0

0

ABCD = 1101 ABCD = 0101 (A is still 0)

G1

G2

G3

A\C

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�� F

0

1

0

1

1

1

1

ABCD = 0101 (A is 1)

A AB

00 01 11 10

0 0 1 1

1 1 1 1

1 1 0 0

0 0 0 0

00

01

11

10 C

CD

D

B



Time Response in Combinational NetworksGlitch Example

General Strategy: add redundant terms

F = A' D + A C' becomes A' D + A C' + C' D

This eliminates 1-hazard? How about 0-hazard?

Re-express F in PoS form:

F = (A' + C')(A + D)

Glitch present!

Add term: (C' + D)

This expression is equivalentto the hazard-free SoP form of F

A AB

00 01 11 10

0 0 1 1

1 1 1 1

1 1 0 0

0 0 0 0

00

01

11

10 C

CD

D

B



Time Response in Combinational NetworksGlitch Example

Start with expression that is free of static 1-hazards

F = A C' + A' D + C' D

F' = (A C' + A' D + C' D)'

= (A' + D) (A + D') (C + D')

= A C + A C D' + C D' + A' C D' + A' D'

= A C + C D' + A' D'

covers all the adjacent 0's in the K-map

free of static-1 and static-0 hazards!

Work with complement:



Time Response in Combinational NetworksDetecting Static Hazards in Multi-Level Circuits

Calculate transient output function

variables and complements are treated as independent variables

cannot use X + X' = 1 or X " X' = 0 for simplifications

F = A B C + (A + D) (A' + C')

F1 = A B C + A A' + A C' + A' D + C' D

Example:

2-level form

ABCD: 1111 to 1110, covered by term ABC, so no 1-hazard present

ABCD: 1110 to 1100, term ABC goes low while term AC' goes high

some static hazards are present!

A AB

00 01 11 10

0 0 1 1

1 1 1 1

1 1 1 0

0 0 1 0

00

01

11

10 C

CD

D

B



100

A B C D F F 2


Static 1-hazards

Solution:

Add redundant terms to insure all adjacent transitions are covered by terms

F2 = A C' + A' D + C' D + A B + B D

1's hazards in Fcorrected in F2



Time Response in Combinational NetworksStatic 0-Hazards

Similar to previous case, but work with the complement of F

If terms of the transient output function cover all 0 transitions, then no 0-hazards are present

F = [A B C + (A + D) (A' + C')]'

= (A' + B' + C') (A' D' + A C)

= A' D' + A' B D' + A' C D' + A B' C

= A' D' + A B' C

0-hazard on transition from1010 to 0010

+ B' C D'

F = (A + D) (A' + B + C') (B + C' + D)

0-hazard free

equivalent to F2 on last slide

A AB

00 01 11 10

0 0 1 1

1 1 1 1

1 1 1 0

0 0 1 0

00

01

11

10 C

CD

D

B



100

A B C D F F 3


Static 0-Hazards

0-HazardCorrected in F3



Time Response in Combinational NetworksDesigning Networks for Hazard-free operation

Simply place transient output function in a form that guarantees that all adjacent ones are covered by a term

no term of the transient output function contains both a variable and its complement

F(A,B,C,D) = m(1,3,5,7,8,9,12,13,14,15)

F = A B + A' D + B D + A C' + C' D

= (A' + B + C') D + A (B + C')

(factored by distributive law, which does notintroduce hazards since it does not depend onthe complementarity laws for its validity)

A AB

00 01 11 10

0 0 1 1

1 1 1 1

1 1 1 0

0 0 1 0

00

01

11

10 C

CD

D

B



Time Response in Combinational NetworksDynamic Hazards

Example with Dynamic Hazard

Three different paths from B or B' to output

ABC = 000, F = 1 to ABC = 010, F = 0

different delays along the paths: G1 slow, G4 very slow

Handling dynamic hazards very complex

Beyond our scope

G1

G2

G3

G5

G4

\A B

\B

\B \C

F

A

0 1

1

1 0

1

0 1

1 0

1 0 1

1 0 0

1 0

1 0 1 0

Slow

V ery slow



Chapter Review

" Transition from Simple Gates to more complex gate building blocks

" Conversion from AND/OR, OR/AND to NAND/NAND, NOR/NOR

" Multi-Level Logic: Reduced gate count, fan-ins, but increased delay

" Use of misII to optimize multi-level logic and to perform mappings

" Time Response in Combinational Logic:Gate Delay, Rise Time, Fall TimeHazards and Hazard-free Design

Contemporary Logic DesignProg. & Steering Logic


Chapter # 4: Programmable andSteering Logic



June 1993



Chapter Overview

" PALs and PLAs

" Non-Gate Logic Switch Logic Multiplexers/Selecters and Decoders Tri-State Gates/Open Collector Gates ROM

" Combinational Logic Design Problems Seven Segment Display Decoder Process Line Controller Logical Function Unit Barrel Shifter



PALs and PLAs

Pre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of AND gates Product

terms

Dense array of OR gates

Outputs



PALs and PLAs

Example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

Equations

Personality Matrix

Key to Success: Shared Product Terms

1 = asserted in term0 = negated in term- = does not participate

1 = term connected to output0 = no connection to output

Input Side:

Output Side:

Outputs Inputs Product t erm

Reuse of

t erms

A 1 - 1 - 1

B 1 0 - 0 -

C - 1 0 0 -

F 0 0 0 0 1 1

F 1 1 0 1 0 0

F 2 1 0 0 1 0

F 3 0 1 0 0 1

A B B C A C B C A



PALs and PLAs

Example Continued

All possible connections are availablebefore programming



PALs and PLAs

Example Continued

Unwanted connections are "blown"

Note: some array structureswork by making connections

rather than breaking them



PALs and PLAsAlternative representation for high fan-in structures

Short-hand notationso we don't have todraw all the wires!

Notation for implementingF0 = A B + A' B'F1 = C D' + C' D



PALs and PLAs

ABC

A

B

C

A

B

C

ABC

ABC

ABC

ABC

ABC

ABC

ABC

F1 F2 F3 F4 F5 F6

Design Example

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A xor B xor C

F6 = A xnor B xnor C

Multiple functions of A, B, C



PALs and PLAs

What is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)?

PAL concept — implemented by Monolithic Memories constrained topology of the OR Array

A given column of the OR arrayhas access to only a subset of

the possible product terms

PLA concept — generalized topologies in AND and OR planes



PALs and PLAsDesign Example: BCD to Gray Code Converter

Truth Table K-maps

W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'

Minimized Functions:

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

W 0 0 0 0 0 1 1 1 1 1 X X X X X X

X 0 0 0 0 1 1 0 0 0 0 X X X X X X

Y 0 0 1 1 1 1 1 1 0 0 X X X X X X

Z 0 1 1 0 0 0 0 1 1 0 X X X X X X

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

0 1 X 1

0 1 X X

0 1 X X

K-map for W

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

0 0 X X

0 0 X X

K-map for X

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

1 1 X X

1 1 X X

K-map for Y

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

1 0 X 0

0 1 X X

1 0 X X

K-map for Z



PALs and PLAs

Programmed PAL:

4 product terms per each OR gate

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PALs and PLAs

Code Converter Discrete Gate Implementation

4 SSI Packages vs. 1 PLA/PAL Package!

B

\ B C

C

A

D

\ D

D W

X

Y B

B

B

B

C

C

A

D

\ A

\ C

\ B

\B \C

\A

\ D

2

2

1 1: 7404 hex inverters 2,5: 7400 quad 2-input NAND 3: 7410 t ri 3-input NAND 4: 7420 dual 4-input NAND

4

4

3

3

5

Z

1

3

2 1

2

D 1

1

4

2



PALs and PLAsAnother Example: Magnitude Comparator

EQ NE LT GT

ABCD

ABCD

ABCD

ABCD

AC

AC

BD

BD

ABD

BCD

ABC

BCD

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

K-map for EQ

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 1 1

1 0 1 1

1 1 0 1

1 1 1 0

K-map for NE

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 0 0

1 0 0 0

1 1 0 1

1 1 0 0

K-map for L T

AB

CD 00 01 11 10

00

01

11

10

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A

0 1 1 1

0 0 1 1

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Non-Gate Logic

AND-OR-InvertPAL/PLA

Generalized Building BlocksBeyond Simple Gates

Introduction

Kinds of "Non-gate logic":

" switching circuits built from CMOS transmission gates

" multiplexer/selecter functions " decoders

" tri-state and open collector gates

" read-only memories



Steering Logic: SwitchesVoltage Controlled Switches

Gate

OxideSource Drain

Silicon Bulk

Channe lRegion

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Diffusion regions: negatively charged ions driven into Si surface

Si Bulk: positively charged ions

By "pulling" electrons to the surface, a conducting channel isformed

"n-Channel MOS"

n-type Si

p-type Si



Steering LogicVoltage Controlled Switches

Logic 0 on gate,Source and Drain connected

Gate

Source Drain

Gate

Source Drain

nMOS Transistor

pMOS Transistor

Logic 1 on gate,Source and Drain connected



Steering LogicLogic Gates from Switches

+5V

A A

+5VA B

A B

+5VA B

A + B

Inverter NAND Gate NOR Gate

Pull-up network constructed from pMOS transistors

Pull-down network constructed from nMOS transistors



Steering Logic

Inverter Operation

+5V

"1" "0"

+5V

"0" "1"

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Input is 1Pull-up does not conductPull-down conductsOutput connected to GND

Input is 0Pull-up conductsPull-down does not conductOutput connected to VDD



Steering Logic

NAND Gate Operation

A = 1, B = 1Pull-up network does not conductPull-down network conductsOutput node connected to GND

A = 0, B = 1Pull-up network has path to VDDPull-down network path brokenOutput node connected to VDD

+5V"1" "1"

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Steering Logic

NOR Gate Operation

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A = 1, B = 0Pull-up network brokenPull-down network conductsOutput node at GND



Steering LogicCMOS Transmission Gate

nMOS transistors good at passing 0's but bad at passing 1's

pMOS transistors good at passing 1's but bad at passing 0's

perfect "transmission" gate places these in parallel:

In Out

Control

Control

In Out

Control

Control

In Out

Control

Control

Switches Transistors Transmission or"Butterfly" Gate



Steering LogicSelection Function/Demultiplexer Function with Transmission Gates

S

S

I 0

I 1

S

S

Z

Selector: Choose I0 if S = 0 Choose I1 if S = 1

S

S

0

I

1

S

S

Z

Z

Demultiplexer: I to Z0 if S = 0 I to Z1 if S = 1



Steering Logic

Use of Multiplexer/Demultiplexer in Digital Systems

So far, we've only seen point-to-point connections among gates

Mux/Demux used to implement multiple source/multiple destination interconnect

A

B Z

Y

Multiplexers Demultiplexers

A

B Z

Y

Multiplexers Demultiplexers



Steering LogicWell-formed Switching Networks

Problem with the Demux implementation: multiple outputs, but only one connected to the input!

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"

0

I

S

S

Z

S

1Z

"0"

S

S

S

"0"



Steering Logic

Complex Steering Logic Example

N Input Tally Circuit: count # of 1's in the inputs

Conventional Logicfor 1 Input Tally

Function "0"

Zero

I1

One"0"

"1"

Zero

One

"0"

"0"

"1"

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Diagonal

Switch Logic Implementationof Tally Function

I 01

Zero 1 0

One 0 1

1

I1 Zero

One



Steering LogicComplex Steering Logic Example

Operation of the 1 Input Tally Circuit

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Zero

One"0"

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Steering Logic

Complex Steering Logic Example Operation of 1 input Tally Circuit

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Extension to the 2-input case

Conventional logic implementation

I 1

0 0 1 1

Zero

1 0 0 0

One

0 1 1 0

T wo

0 0 0 1

I 2

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I 1

I 2

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Steering Logic

Complex Steering Logic Example

Switch Logic Implementation: 2-input Tally Circuit

"0"

Zero

I1

One"0"

"1"

"0"

Zero

One

I2

"0" Two

Cascade the 1-input implementation!

Zero

One

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"1"

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One

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Operation of 2-input implementation

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One

"0"

"0"

"1"

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Multiplexers /Selectors

Use of Multiplexers/Selectors

Multi-point connections

MUX MUX

DEMUX

A B

Sum

A0 A1 B0 B1

Sa Sb

Ss

S0 S1

Multiple input sources

Multiple output destinations



I 1 0 0 0 0 1 1 1 1

I 0 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Z 0 0 1 0 0 1 1 1

A 0 1

Z I 0 I 1


2 data inputs, n control inputs, 1 output

used to connect 2 points to a single point

control signal pattern form binary index of input connected to output

n

n

Two alternative formsfor a 2:1 Mux Truth Table

Z = A' I + A I0 1

Functional form

Logical form

General Concept




Z = A' I + A I0 1

Z = A' B' I0 + A' B I1 + A B' I2 + A B I3

Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7

In general, Z = ΣΣΣΣ m I2 -1n

k=0 k kin minterm shorthand form for a 2 :1 Muxn

2:1 mux

I 0

I 1

A

Z

I 0

A

I 1

I 2

I 3

B

Z 4:1 mux

I 0

A

I 1

I 2 I 3

B

Z 8:1

mux

C

I 4 I 5

I 6

I 7




Gate LevelImplementation

of 4:1 Mux

Transmission GateImplementation of

4:1 Mux

thirty six transistors twenty transistors

I3

I0

I2

I1

A B

Z

Alternative Implementations



Multiplexer /SelectorLarge multiplexers can be implemented by cascaded smaller ones

Control signals B and C simultaneouslychoose one of I0-I3 and I4-I7

Control signal A chooses which of theupper or lower MUX's output to gate to Z

0

1 S

0

1 S

0

1 S

0

1 S

0

1

S1

2

3 S0

C

A B

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

C

C

C

ZAlternative 8:1 Mux Implementation

4:1 mux

4:1 mux

8:1 mux

2:1 mux

0 1 2 3

0 1 2 3

S

S 1 S 0

S 1 S 0

Z

A C B

I 0

I 1

I 2

I 3

I 4

I 5

I 6 I 7

0

1



Multiplexer /Selector

Multiplexers/selectors as a general purpose logic block

2 :1 multiplexer can implement any function of n variables

n-1 control variables; remaining variable is a data input to the mux

n-1

Example:

F(A,B,C) = m0 + m2 + m6 + m7

= A' B' C' + A' B C' + A B C' + A B C

= A' B' (C') + A' B (C') + A B' (0) + A B (1)

8:1 MUX

1 0 1 0 0 0 1 1

0 1 2 3 4 5 6 7 S2 S1 S0

A B C

F

"Lookup Table"

S1 S0

A B

4:1 MUX

0 1 2 3

CC01

F

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 1 0 1 0 0 0 1 1

C

C

0

1



I 1

1 1

1

1 0

I n

0 1

I n

0 0

0

… F I 2 I n

0

1 …

Multiplexer /SelectorGeneralization

n-1 Mux control variables

single Muxdata variable

Four possibleconfigurations

of the truth table rows

Can be expressed asa function of In, 0, 1

Example:G(A,B,C,D) can be implemented by an 8:1 MUX:

K-mapChoose A,B,C

as control variables

MultiplexerImplementation

TTL package efficientMay be gate inefficient

G 8:1 mux

0 1 2 3 4 5 6 7

A B C

S 2 S 1 S 0

1 D 0 1 D D D D



Decoders/ Demultiplexers

Decoder: single data input, n control inputs, 2 outputs

control inputs (called select S) represent Binary index of output to which the input is connected

data input usually called "enable" (G)

n

1:2 Decoder:

O0 = G " S; O1 = G " S

2:4 Decoder:

O0 = G " S0 " S1

O1 = G " S0 " S1

O2 = G " S0 " S1

O3 = G " S0 " S1

3:8 Decoder:O0 = G " S0 " S1 " S2

O1 = G " S0 " S1 " S2

O2 = G " S0 " S1 " S2

O3 = G " S0 " S1 " S2

O4 = G " S0 " S1 " S2

O5 = G " S0 " S1 " S2

O6 = G " S0 " S1 " S2

O7 = G " S0 " S1 " S2



Decoders/ DemultiplexersAlternative Implementations

1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable

2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable

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Decoders/ DemultiplexersSwitch Logic Implementations

Select

SelectSelect

Select

G Output0

Select

Select

Output1

Select

Select

"0"

"0"

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Select

G Output

Output

0

1

Naive, Incorrect Implementation

All outputs not driven at all times

Correct 1:2 Decoder Implementation



Decoders/ DemultiplexersSwitch Implementation of 2:4 Decoder

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S0 = 0, S1 = 0

one straight thru path

three diagonal paths



Decoder/ Demultiplexer

Decoder Generates AppropriateMinterm based on Control Signals

Decoder as a Logic Building Block

Example Function:

F1 = A' B C' D + A' B' C D + A B C DF2 = A B C' D' + A B CF3 = (A' + B' + C' + D')

3:8 dec

0 1

2 3 4 5 6 7

A B C

Enb

ABC ABC ABC ABC ABC ABC

ABC ABC S 2 S 1 S 0



A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D

A B C D A B C D A B C D A B C D

F 1

F 3

0 1 2 3 4 5 6 7 8 9

10 1 1 12 13 14 15

A

S 3 S 2 S 1 S 0

4:16 dec

Enb

B C D

F 2

Decoder/ Demultiplexer

Decoder as a Logic Building Block

If active low enable, then use NAND gates!



Multiplexers /Decoders

Alternative Implementations of 32:1 Mux

Multiplexer Only Multiplexer + Decoder

EN76543210CBA

151

WY

4321

15

14

11

10

9

65

B1B2B3

B0

A3A2A1A0

153GA

GB

YA

YB

S1SO

65431

10111213

15 142

7

9

EN76543210CBA

151

WY

4321

15

14

11

10

9

65

EN76543210CBA

151

WY

4321

15

14

13

11

10

9

65

EN76543210

151

WY1 6

5

S2 S1 S0

I7

F(A, B, C, D, E)

I0

I15

I23

I31

I6I5I4I3I2I1

A B

C D E

1Y21Y11Y0

1Y3139

2Y12Y0

2Y3

6543210CBA

4321

1514

11109

EN76543210

151

WY

4321

1514

11109

7

65

S2 S1 S0

I31

I0

I5I4I3I2I1

C D E

1G

1B1A2G2B2A

4567

23

1

1211109

1413

152Y2

6543210CBA

4321

1514

11109

EN76543210

151

WY

4321

1514

11109

7

65

S2 S1 S0

I23

I0

I5I4I3I2I1

C D E

6543210CBA

4321

1514

11109

EN76543210

151

WY

4321

1514

11109

7

65

S2 S1 S0

I15

I0

I5I4I3I2I1

C D E

6543210CBA

4321

1514

11109

EN76543210

151

WY

7

65

S2 S1 S0

I7

I0

I6I5I4I3I2I1

C D E

A B

F(A, B, C, D, E)



Multiplexers /Decoders5:32 Decoder

5:32 Decoder

Subsystem

\EN

S4 S3 S2 S1 S0

.

.

.

\Y31

\Y0

2Y2

1Y11Y0

1Y31Y2

2Y12Y0

2Y3

1G

1B1A

139

2G

2B2A

S4 S3

G1G2AG2B

C

BA

Y7Y6Y5Y4

Y1Y0

Y3Y2

138

G1G2AG2B

CBA

Y7Y6Y5Y4

Y1Y0

Y3Y2

138

G1G2AG2B

CBA

Y7Y6Y5Y4

Y1Y0

Y3Y2

138

G1G2AG2B

CBA

Y7Y6Y5Y4

Y1Y0

Y3Y2

138

\EN

S2 S1 S0

S2 S1 S0

S2 S1 S0

S2 S1 S0

\Y31\Y30\Y29\Y28\Y27\Y26\Y25\Y24

\Y23\Y22\Y21\Y20\Y19\Y18\Y17\Y16

\Y15\Y14\Y13\Y12\Y11\Y10\Y9\Y8

\Y7\Y6\Y5\Y4\Y3\Y2\Y1\Y0



A

OE

F

100

Tri -State and Open-Collector

Logic States: "0", "1"Don't Care/Don't Know State: "X" (must be some value in real circuit!)

Third State: "Z" — high impedance — infinite resistance, no connection

Tri-state gates: output values are "0", "1", and "Z" additional input: output enable (OE)

When OE is high, this gate is a non-inverting "buffer"

When OE is low, it is as though the gate was disconnected from the output!

This allows more than one gate to be connected to the same output wire, as long as only one has its output enabled at the same time

Non-inverting buffer'stiming waveform

"Z" "Z"

The Third State

AX01

OE011

FZ01



Tri -state and Open Collector

Using tri-state gates to implement an economical multiplexer:

When SelectInput is asserted high Input1 is connected to F

When SelectInput is driven low Input0 is connected to F

This is essentially a 2:1 Mux

OE

OE

Input 0

Input 1

SelectInput

F



Tri -state and Open CollectorAlternative Tri-state Fragment

Active low tri-state enablesplus inverting tri-state buffers

Switch Level Implementationof tri-state gate

Input 0

Input 1

SelectInput

OE

OE

F

F I

OE

1

0



Tri -State and Open Collector4:1 Multiplexer, Revisited

Decoder + 4 tri-state Gates

1G

1B1A

1Y11Y0

1Y31Y2139

2G

2B2A

2Y12Y0

2Y32Y2

S1 S0

\EN

D3

D2

D1

D0

1

32

15

1314

7654

9101112



+5 V

F

A B

0 V

Open-collector NAND gate

Pull-up resistor

Tri -State and Open Collector

Open Collectoranother way to connect multiple gates to the same output wire

gate only has the ability to pull its output low; it cannot actively drive the wire high

this is done by pulling the wire up to a logic 1 voltage through a resistor

Wired AND:If A and B are "1", output is actively pulled lowif C and D are "1", output is actively pulled lowif one gate is low, the other high, then low winsif both gates are "1", the output floats, pulled high by resistorHence, the two NAND functions are AND'd together!

OC NAND gates



Tri -State and Open Collector4:1 Multiplexer

+5VG

BA

Y1Y0

Y3Y2139

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Read-Only Memories

ROM: Two dimensional array of 1's and 0's

Row is called a "word"; index is called an "address"

Width of row is called bit-width or wordsize

Address is input, selected word is output

Dec

0 n-1

Address

2 -1n

0

+5V +5V +5V +5V

Word Line 0011 Word Line 1010

Bit Lines

j

i

Internal Organization



Read-Only Memories

Example: Combination Logic Implementation

F0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'

address outputs

ROM 8 w ords ¥

4 bits

A B C F 0 F 1 F 2 F 3

B 0 0 1 1 0 0 1 1

Address W ord Contents A 0 0 0 0 1 1 1 1

C 0 1 0 1 0 1 0 1

F 0 0 1 0 0 1 1 0 0

F 1 0 1 1 0 0 0 0 1

F 2 1 1 0 0 1 0 0 0

F 3 0 0 0 1 1 0 1 0

by



Read-Only Memories

Not unlike a PLAstructure with afully decoded

AND array!

ROM vs. PLA:ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions

ROM problem: size doubles for each additional input, can't use don't cares

PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions

PAL problem: constrained fan-ins on OR planes

Memory array

2 n words by m bits

m output lines

n address lines

Decoder 2 n word lines



Read-Only Memories

2764 EPROM8K x 8

16K x 16 Subsystem

2764

A0A1A2A3A4A5A6A7A8A9

O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12


O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

++2764


O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

2764


O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

2764


O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

2764


O0O1O2O3O4O5O6O7

OECS

PGMVPP

A10A11A12

+ +

A13/OE

A12:A0

D7:D0D15:D8

U3 U2

U1 U0



Combinational Logic Word Problems

General Design Procedure

1. Understand the Problem what is the circuit supposed to do? write down inputs (data, control) and outputs draw block diagram or other picture

2. Formulate the Problem in terms of a truth table or other suitable design representation truth table or waveform diagram

3. Choose Implementation Target ROM, PAL, PLA, Mux, Decoder + OR, Discrete Gates

4. Follow Implementation Procedure K-maps, espresso, misII



Combinational Logic Word ProblemsProcess Line Control Problem

Statement of the Problem

Rods of varying length (+/-10%) travel on conveyor beltMechanical arm pushes rods within spec (+/-5%) to one sideSecond arm pushes rods too long to other sideRods too short stay on belt

3 light barriers (light source + photocell) as sensors

Design combinational logic to activate the arms

Understanding the Problem

Inputs are three sensors, outputs are two arm control signals

Assume sensor reads "1" when tripped, "0" otherwise

Call sensors A, B, C

Draw a picture!



Combinational Logic Word ProblemsProcess Control Problem

Where to place the light sensors A, B, and C to distinguish among the three cases?

Assume that A detects the leading edge of the rod on the conveyor

Spec

+ 5%

+10%

Too Long

ROD

Spec

+ 5%

- 5%

Within Spec

ROD

Spec

- 5%

- 10%

Too Short

ROD

��

��

��

��

��

��

��




A

B

C

Spectification - 5%

Specification + 5%

Too Long

Too Short

Within Spec

A to B distance place apart at specification - 5%

A to C distance placed apart at specification +5%




Truth table and logic implementation now straightforward

"too long" = A B C (all three sensors tripped)

"in spec" = A B C' (first two sensors tripped)

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Function X X X X

too short X

in spec too long




BCD to 7 Segment Display Controller

Understanding the problem:

input is a 4 bit bcd digit

output is the control signals for the display

4 inputs A, B, C, D

7 outputs C0 — C6

Block Diagram

C 5

C 0

C 6

C 3

C 4

C 1

C 2

C 0

C 1

C 2

C 3

C 4

C 5

C 6

BCD-to-7-segment control signal

decoder

7-Segment display

C 0 C 1 C 2 C 3 C 4 C 5 C 6

A B C D



Combinational Logic Word ProblemsBCD to 7 Segment Display Controller

Formulate the problem in terms of a truth table

Choose implementation target:

if ROM, we are done

don't cares imply PAL/PLA may be attractive

Follow implementation procedure:

hand reduced K-maps

vs.

espresso




C0 = A + B D + C + B' D'C1 = A + C' D' + C D + B'C2 = A + B + C' + D

C3 = B' D' + C D' + B C' D + B' CC4 = B' D' + C DC5 = A + C' D' + B D' + B C'C6 = A + C D' + B C' + B' C14 Unique Product Terms

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 X 1

0 1 X 1

1 1 X X

1 1 X X

K-map for C 0

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 X 1

1 0 X 1

1 1 X X

1 0 X X

K-map for C 1

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 X 1

1 1 X 1

1 1 X X

0 1 X X

K-map for C 2

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 X 1

0 1 X 0

1 0 X X

1 1 X X

K-map for C 3

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 0 X 1

0 0 X 0

0 0 X X

1 1 X X

K-map for C 4

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

1 1 X 1

0 1 X 1

0 0 X X

0 1 X X

K-map for C 5

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 1

0 1 X 1

1 0 X X

1 1 X X

K-map for C 6



Combinational Logic Word ProblemsBCD to 7 Segment Display Controller 0

32 64 96

128 160 192 224

First fuse numbers

1

19

2

0 4 8 12 16 20 24 28

256 288 320 352 384 416 448 480

18

3

512 544 576 608 640 672 704 736

17

4

768 800 832 864 896 928 960 992

16

5

1024 1056 1088 1120 1152 1184 1216 1248

15

6

1280 1312 1344 1376 1408 1440 1472 1504

14

7

1536 1568 1600 1632 1664 1696 1728 1760

13

8

1792 1824 1856 1888 1920 1952 1984 2016

12

9 11

Increment

Note: Fuse number = first fuse number + increment

16H8PALCan Implementthe function




14H8PALCannot Implementthe function

1

2 23

First fuse numbers

0 28 56 84

3

4

14

13

5

6

7

8

9

10

11

21 112 140

20 168 196

19 224 252

18 280 308

17 336 364

16 392 420

1 22

448 476 504 532

15

0 1 2 3 4 8 10 12 14 16 18 20 24 27

Note: Fuse number = first fuse number + increment

Increment



Combinational Logic Word ProblemsBCD to7 Segment Display Controller

.i 4

.o 7

.ilb a b c d

.ob c0 c1 c2 c3 c4 c5 c6

.p 160000 11111100001 01100000010 11011010011 11110010100 01100110101 10110110110 10111110111 11100001000 11111111001 11100111010 -------1011 -------1100 -------1101 -------1110 -------1111 -------.e

.i 4

.o 7

.ilb a b c d

.ob c0 c1 c2 c3 c4 c5 c6

.p 9-10- 0000001-01- 0001001-0-1 0110000-101 1011010--00 0110010--11 1110000-0-0 11011001--- 1000011-110 1011111.e

espressoinput

espressooutput

C0 = B C' D + C D + B' D' + B C D' + AC1 = B' D + C' D' + C D + B' D'C2 = B' D + B C' D + C' D' + C D + B C D'C3 = B C' D + B' D + B' D' + B C D'C4 = B' D' + B C D'C5 = B C' D + C' D' + A + B C D'C6 = B' C + B C' + B C D' + A

9 Unique Product Terms!

63 Literals, 20 Gates




PLA Implementation



Combinational Logic Word ProblemsBCD to7 Segment Display Controller

Multilevel Implementation

X = C' + D'

Y = B' C'

C0 = C3 + A' B X' + A D Y

C1 = Y + A' C5' + C' D' C6

C2 = C5 + A' B' D + A' C D

C3 = C4 + B D C5 + A' B' X'

C4 = D' Y + A' C D'

C5 = C' C4 + A Y + A' B X

C6 = A C4 + C C5 + C4' C5 + A' B' C

52 literals

33 gates

Ineffective use of don't cares




Logical Function Unit

Statement of the Problem:

3 control inputs: C0, C1, C22 data inputs: A, B1 output: F




Logical Function Unit

��

��

��

��

��

��

��

��

Formulate as a truth table

Choose implementation technology 5-variable K-map espresso multiplexor implementation

4 TTL packages:4 x 2-input NAND4 x 2-input NOR2 x 2-input XOR8:1 MUX

A B

A

B

A B

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

+ 5 V C 2

C 1

C 0

F

E N

S 0 S 1 S 2

Q O



Combinational Logic Word ProblemsLogical Function Unit

Follow implementation procedure

F = C2' A' B' + C0' A B' + C0' A' B + C1' A B

5 gates, 5 inverters

Also four packages: 4 x 3-input NAND 1 x 4-input NAND

Alternative: 32 x 1-bit ROM

single package

A B C 1 C 2

00 01 11 10 00

01

11

10

C 0 =0

A B C 1 C 2

00 01 11 10 00

01

11

10

C 0 =1

1 1

1 1 1 1

1 1 1 1

1 1

1 1

1 1



Combinational Logic Word Problems8-Input Barrel Shifter

Specification:

Inputs: D7, D6, &, D0Outputs: O7, O6, &, O0Control: S2, S1, S0

shift input the specified numberof positions to the right

D7D6D5D4D3D2D1D0

O7O6O5O4O3O2O1O0

.

.

.

S2, S1, S0 = 0 0 0

D7D6D5D4D3D2D1D0

O7O6O5O4O3O2O1O0

.

.

.

S2, S1, S0 = 0 0 1

D7D6D5D4D3D2D1D0

O7O6O5O4O3O2O1O0

.

.

.

S2, S1, S0 = 0 1 0

Understand the problem:



Combinational Logic Word Problems8-Input Barrel Shifter

Boolean equations

O7 = S2' S1' S0' D7 + S2' S1' S0 D6 + & + S2 S1 S0 D0

O6 = S2' S1' S0' D6 + S2' S1' S0 D5 + & + S2 S1 S0 D7

O5 = S2' S1' S0' D5 + S2' S1' S0 D4 + & + S2 S1 S0 D6

O4 = S2' S1' S0' D4 + S2' S1' S0 D3 + & + S2 S1 S0 D5

O3 = S2' S1' S0' D3 + S2' S1' S0 D2 + & + S2 S1 S0 D4

O2 = S2' S1' S0' D2 + S2' S1' S0 D1 + & + S2 S1 S0 D3

O1 = S2' S1' S0' D1 + S2' S1' S0 D0 + & + S2 S1 S0 D2

O0 = S2' S1' S0' D0 + S2' S1' S0 D7 + & + S2 S1 S0 D1

O7 D7 D6 D5 D4 D3 D2 D1 D0

O6 D6 D5 D4 D3 D2 D1 D0 D7

O5 D5 D4 D3 D2 D1 D0 D7 D6

O4 D4 D3 D2 D1 D0 D7 D6 D5

O3 D3 D2 D1 D0 D7 D6 D5 D4

O2 D2 D1 D0 D7 D6 D5 D4 D3

O1 D1 D0 D7 D6 D5 D4 D3 D2

O0 D0 D7 D6 D5 D4 D3 D2 D1

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

Function Table




8-Input Barrel Shifter

Straightforward gate logic implementation OR

8 by 8:1 multiplexer (wiring mess!) OR

Switch logic

O7 O6 O5 O4 O3 O2 O1 O0

D7

D6

D5

D4

D3

D2

D1

D0

��

��

��

��

S000

S001S001

O7 O6 O5 O4 O3 O2 O1 O0

D7

D6

D5

D4

D3

D2

D1

D0

S000

S001 S001

S010 S010

S011

S100

S101

S110

S111

S011

S100

S101

S110

S111

Crosspoint switches Fully Wired crosspoint switch



Chapter Review

" Non-Simple Gate Logic Building Blocks:

" Combinational Word Problems:

PALs/PLAs

Multiplexers/Selecters

Decoders

ROMs

Tri-state, Open Collector

Understand the Problem

Formulate in terms of a Truth Table

Choose implementation technology

Implement by following the design procedure

Contemporary Logic DesignArithmetic Circuits


Chapter # 5: Arithmetic Circuits



June 1993



Motivation

Arithmetic circuits are excellent examples of comb. logic design

" Time vs. Space Trade-offs

Doing things fast requires more logic and thus more space

Example: carry lookahead logic

" Arithmetic Logic Units

Critical component of processor datapath Inner-most "loop" of most computer instructions



Chapter Overview

" Binary Number Representation Sign & Magnitude, Ones Complement, Twos Complement

" Binary Addition Full Adder Revisted

" ALU Design

" BCD Circuits

" Combinational Multiplier Circuit

" Design Case Study: 8 Bit Multiplier



Number Systems

Representation of Negative Numbers

Representation of positive numbers same in most systems

Major differences are in how negative numbers are represented

Three major schemes:

sign and magnitude

ones complement

twos complement

Assumptions:

we'll assume a 4 bit machine word

16 different values can be represented

roughly half are positive, half are negative



Number SystemsSign and Magnitude Representation

0000

0111

0011

1011

11111110

1101

1100

1010

1001

10000110

0101

0100

0010

0001

+0+1

+2

+3

+4

+5

+6

+7-0

-1

-2

-3

-4

-5

-6

-7

0 100 = + 4 1 100 = - 4

+

-

High order bit is sign: 0 = positive (or zero), 1 = negative

Three low order bits is the magnitude: 0 (000) thru 7 (111)

Number range for n bits = +/-2 -1

Representations for 0

n-1



Number SystemsSign and Magnitude

Cumbersome addition/subtraction

Must compare magnitudes to determine sign of result

Ones Complement

N is positive number, then N is its negative 1's complement

N = (2 - 1) - Nn

Example: 1's complement of 7

2 = 10000

-1 = 00001

1111

-7 = 0111

1000 = -7 in 1's comp.Shortcut method:

simply compute bit wise complement

0111 -> 1000

4



Number SystemsOnes Complement

Subtraction implemented by addition & 1's complement

Still two representations of 0! This causes some problems

Some complexities in addition

0000

0111

0011

1011

11111110

1101

1100

1010

1001

10000110

0101

0100

0010

0001

+0+1

+2

+3

+4

+5

+6

+7-7

-6

-5

-4

-3

-2

-1

-0

0 100 = + 4 1 011 = - 4

+

-



Number RepresentationsTwos Complement

0000

0111

0011

1011

11111110

1101

1100

1010

1001

10000110

0101

0100

0010

0001

+0+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1

0 100 = + 4 1 100 = - 4

+

-

Only one representation for 0

One more negative number than positive number

like 1's compexcept shiftedone positionclockwise



Number SystemsTwos Complement Numbers

N* = 2 - Nn

Example: Twos complement of 7

2 = 10000

7 = 0111

1001 = repr. of -7

Example: Twos complement of -7

4

2 = 10000

-7 = 1001

0111 = repr. of 7

4

sub

sub

Shortcut method:

Twos complement = bitwise complement + 1

0111 -> 1000 + 1 -> 1001 (representation of -7)

1001 -> 0110 + 1 -> 0111 (representation of 7)



Number RepresentationsAddition and Subtraction of Numbers

Sign and Magnitude

4

+ 3

7

0100

0011

0111

-4

+ (-3)

-7

1100

1011

1111

result sign bit is thesame as the operands'sign

4

- 3

1

0100

1011

0001

-4

+ 3

-1

1100

0011

1001

when signs differ,operation is subtract,sign of result dependson sign of number withthe larger magnitude



Number SystemsAddition and Subtraction of Numbers

Ones Complement Calculations

4

+ 3

7

0100

0011

0111

-4

+ (-3)

-7

1011

1100

10111

1

1000

4

- 3

1

0100

1100

10000

1

0001

-4

+ 3

-1

1011

0011

1110

End around carry

End around carry



Number Systems

Addition and Subtraction of Binary Numbers

Ones Complement Calculations

Why does end-around carry work?

Its equivalent to subtracting 2 and adding 1n

M - N = M + N = M + (2 - 1 - N) = (M - N) + 2 - 1n n

(M > N)

-M + (-N) = M + N = (2 - M - 1) + (2 - N - 1)

= 2 + [2 - 1 - (M + N)] - 1

n n

n nM + N < 2

n-1

after end around carry:

= 2 - 1 - (M + N)n

this is the correct form for representing -(M + N) in 1's comp!



Number SystemsAddition and Subtraction of Binary Numbers

Twos Complement Calculations

4

+ 3

7

0100

0011

0111

-4

+ (-3)

-7

1100

1101

11001

4

- 3

1

0100

1101

10001

-4

+ 3

-1

1100

0011

1111

If carry-in to sign =carry-out then ignorecarry

if carry-in differs fromcarry-out then overflow

Simpler addition scheme makes twos complement the most commonchoice for integer number systems within digital systems



Number Systems

Addition and Subtraction of Binary Numbers

Twos Complement Calculations

Why can the carry-out be ignored?

-M + N when N > M:

M* + N = (2 - M) + N = 2 + (N - M)n n

Ignoring carry-out is just like subtracting 2n

-M + -N where N + M < or = 2 n-1

-M + (-N) = M* + N* = (2 - M) + (2 - N)

= 2 - (M + N) + 2n n

After ignoring the carry, this is just the right twos compl.representation for -(M + N)!

n n



Number Systems

Overflow Conditions

Add two positive numbers to get a negative number

or two negative numbers to get a positive number

5 + 3 = -9 -7 - 2 = +7

0000

0001

0010

0011

1000

0101

0110

0100

1001

1010

1011

1100

1101

0111

1110

1111

+0

+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1

0000

0001

0010

0011

1000

0101

0110

0100

1001

1010

1011

1100

1101

0111

1110

1111

+0

+1

+2

+3

+4

+5

+6

+7-8

-7

-6

-5

-4

-3

-2

-1



Number Systems

Overflow Conditions

5

3

-8

0 1 1 1 0 1 0 1

0 0 1 1

1 0 0 0

-7

-2

7

1 0 0 0 1 0 0 1

1 1 0 0

1 0 1 1 1

5

2

7

0 0 0 0 0 1 0 1

0 0 1 0

0 1 1 1

-3

-5

-8

1 1 1 1 1 1 0 1

1 0 1 1

1 1 0 0 0

Overflow Overflow

No overflow No overflow

Overflow when carry in to sign does not equal carry out



Networks for Binary AdditionHalf Adder

With twos complement numbers, addition is sufficient

Ai 0 0 1 1

Bi 0 1 0 1

Sum 0 1 1 0

Carry 0 0 0 1

AiBi

0 1

0

1

0 1

1 0

Sum = Ai Bi + Ai Bi

= Ai + Bi

AiBi

0 1

0

1

0 0

10

Carry = Ai Bi

Half-adder Schematic

Carry

Sum A i

B i



Networks for Binary Addition

Full Adder

+

A3 B3

S3

+

A2 B2

S2

+

A1 B1

S1

+

A0 B0

S0C1C2C3

Cascaded Multi-bit Adder

usually interested in adding more than two bits

this motivates the need for the full adder




Full Adder

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

CI 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

CO 0 0 0 1 0 1 1 1

A BCI

0

1

00 01 11 10

0

1

1

0

1

0

0

1

A BCI

0

1

00 01 11 10

0

0

0

1

0

1

1

1

S

CO

S = CI xor A xor B

CO = B CI + A CI + A B = CI (A + B) + A B




Full Adder/Half Adder

��

A

AA

��

B

BB

��

��

��

CI��

CI

��S

��

��

CO

Alternative Implementation: 5 Gates

Half Adder

A

B

Half Adder

A + B

CI

A + B + CIS S

COCO CI (A + B)A B

S

CO

A B + CI (A xor B) = A B + B CI + A CI

Standard Approach: 6 Gates

+




Adder/Subtractor

A - B = A + (-B) = A + B + 1

A B

CO

S

+ CI

A B

CO

S

+ CI

A B

CO

S

+ CI

A B

CO

S

+ CI

0 1

Add/Subtract

A 3 B 3 B 3

0 1

A 2 B 2 B 2

0 1

A 1 B 1 B 1

0 1

A 0 B 0 B 0

Sel Sel Sel Sel

S 3 S 2 S 1 S 0

Overflow




Carry Lookahead Circuits

Critical delay: the propagation of carry from low to high order stages

��

A

A

��B

B ��CI

��

��

CO

@0@0

@0@0

@N

@1

@1

@N+1

@N+2

latearrivingsignal

two gate delaysto compute CO

4 stageadder

final sum andcarry

A 0

B 0

C 0

S 0 @2

A 1

B 1

C 1 @2

S 1 @3

A 2

B 2

C 2 @4

S 2 @5

A 3

B 3

C 3 @6

S 3 @7

C 4 @8

0

1

2

3




Carry Lookahead Circuits

Critical delay: the propagation of carry from low to high order stages

1111 + 0001worst case

addition

T0: Inputs to the adder are valid

T2: Stage 0 carry out (C1)




2 delays to compute sum

but last carry not ready until 6 delays later

T0 T2 T4 T6 T8

S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid




Carry Lookahead Logic

Carry Generate Gi = Ai Bi must generate carry when A = B = 1

Carry Propagate Pi = Ai xor Bi carry in will equal carry out here

Si = Ai xor Bi xor Ci = Pi xor Ci

Ci+1 = Ai Bi + Ai Ci + Bi Ci

= Ai Bi + Ci (Ai + Bi)

= Ai Bi + Ci (Ai xor Bi)

= Gi + Ci Pi

Sum and Carry can be reexpressed in terms of generate/propagate:





Reexpress the carry logic as follows:

C1 = G0 + P0 C0

C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0

C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0

C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

Each of the carry equations can be implemented in a two-level logic network

Variables are the adder inputs and carry in to stage 0!




Carry Lookahead Implementation

Adder with Propagate and Generate Outputs

Increasingly complex logic

��

��

�� Pi @ 1 gate delay

��

��Ci Si @ 2 gate delays

��

��

�

��

Bi

��

��

��

��

��

Ai

��

Gi @ 1 gate delay

C0C0

C0

C0P0P0

P0

P0

G0G0

G0

��

G0

C1

P1

P1

P1

P1

P1

P1

��

��

G1

G1

��

G1

C2P2

P2

P2

P2

P2

P2

��

��

��

��

G2

��

��

G2

C3

P3

P3

P3

P3

��

��

��

��

��

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��

��

��

��

G3

C4





Cascaded Carry Lookahead

Carry lookaheadlogic generatesindividual carries

sums computedmuch faster

A 0

B 0

C 0

S 0 @2

A 1

B 1

C 1 @3

S 1 @4

A 2

B 2

C 2 @3

S 2 @4

A 3

B 3

C 3 @3

S 3 @4

C 4 @3





Cascaded Carry Lookahead

4 bit adders with internal carry lookahead

second level carry lookahead unit, extends lookahead to 16 bits

4-bit Adder

4 4

4

A [15-12] B [15-12] C 12 C 16

S [15-12]

P G 4-bit Adder

4 4

4

A [1 1-8] B [1 1-8] C 8

S [1 1-8]

P G 4-bit Adder

4 4

4

A [7-4] B [7-4] C 4

S [7-4]

P G 4-bit Adder

4 4

4

A [3-0] B [3-0] C 0

S [3-0]

P G

Lookahead Carry Unit C 0

P 0 G 0 P 1 G 1 P 2 G 2 P 3 G 3 C 3 C 2 C 1

C 0

P 3-0 G 3-0

C 4

@3 @2

@0

@4

@4 @3 @2 @5

@7

@3 @2 @5

@8 @8

@3 @2

@5

@5 @3

@0

C 16



Networks for Binary AdditionCarry Select Adder

Redundant hardware to make carry calculation go faster

compute the high order sums in parallel

one addition assumes carry in = 0

the other assumes carry in = 1

4-Bit Adder [3:0]

C 0 C 4

4-Bit Adder [7:4]

0 C 8

1 C 8

4 ¥ 2:1 Mux

0 1 0 1 0 1

4-Bit Adder [7:4]

C 8 S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0

0 1

C 4

Adder High

Adder Low



Arithmetic Logic Unit Design

Sample ALU

S1 0 0 1 1

S0 0 1 0 1

Function Fi = Ai

Fi = not Ai Fi = Ai xor Bi

Fi = Ai xnor Bi

Comment Input Ai transferred to output Complement of Ai transferred to output Compute XOR of Ai, Bi Compute XNOR of Ai, Bi

M = 0, Logical Bitwise Operations

M = 1, C0 = 0, Arithmetic Operations0 0 1 1

0 1 0 1

F = A F = not A

F = A plus B F = (not A) plus B

Input A passed to output Complement of A passed to output Sum of A and B Sum of B and complement of A

M = 1, C0 = 1, Arithmetic Operations

0 0 1 1

0 1 0 1

F = A plus 1 F = (not A) plus 1

F = A plus B plus 1 F = (not A) plus B plus 1

Increment A Twos complement of A Increment sum of A and B B minus A

Logical and Arithmetic Operations

Not all operations appear useful, but "fall out" of internal logic




Sample ALU

Traditional Design Approach

Truth Table & Espresso

23 product terms!

Equivalent to 25 gates

.i 6

.o 2

.ilb m s1 s0 ci ai bi

.ob fi co

.p 23111101 10110111 101-0100 101-1110 1010010- 1010111- 10-10001 10010-01 10-11011 10011-11 10--1000 100-1-00 10--0010 100-0-10 10-0100- 10001-0- 10-0001- 10000-1- 10-1-1-1 01--1-01 01--0-11 01--110- 01--011- 01.e

M 0

1

1

S1 0

0

1

1

0

0

1

1

0

0

1

1

S0 0

1

0

1

0

1

0

1

0

1

0

1

Ci X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Ai 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 01 0 1 0 0 1 1 0 0 1 1

Bi X X X X 0 1 0 1 0 1 0 1 X X X X 0 1 0 1 0 1 0 1 X X X X 0 1 0 1 0 1 0 1

Fi 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0

Ci+1 X X X X X X X X X X X X X X X X 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 1 1 0 1




Sample ALU

Multilevel Implementation.model alu.espresso.inputs m s1 s0 ci ai bi.outputs fi co.names m ci co [30] [33] [35] fi110--- 1-1-11- 1--01-1 1--00-0 1.names m ci [30] [33] co-1-1 1--11 1111- 1.names s0 ai [30]01 110 1.names m s1 bi [33]111 1.names s1 bi [35]0- 1-0 1.end 12 Gates

\S1

\Bi

[35]

[35] M

M

MS1Bi

[33][33]

[33]

[33]

S0Ai

[30]

[30]

[30]

[30]

[30]

Ci

Ci

Ci

Ci

��

��

Co

\Co

\Co

\Co

\[30]\[35]

Fi

��

��

��

��

��




Clever Multi-level Logic Implementation

Sample ALU

8 Gates (but 3 are XOR)

S1 = 0 blocks BiHappens when operations involve Ai only

Same is true for Ci when M = 0

Addition happens when M = 1

Bi, Ci to Xor gates X2, X3

S0 = 0, X1 passes A

S0 = 1, X1 passes A

Arithmetic Mode:

Or gate inputs are Ai Ci and Bi (Ai xor Ci)

Logic Mode:

Cascaded XORs form output from Ai and Bi

��Bi

��S1

��

Ai

��

S0 ��Ci

��M

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

Fi

��

��

Ci+1

X1

X2

X3

A1 A2

A3 A4

O1




74181 TTL ALU

S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Logic Function F = not A F = A nand B F = (not A) + B F = 1 F = A nor B F = not B F = A xnor B F = A + not B F = (not A) B F = A xor B F = B F = A + B F = 0 F = A (not B) F = A B F = A

Cn = 0 F = A minus 1 F = A B minus 1 F = A (not B) minus 1 F = minus 1 F = A plus (A + not B) F = A B plus (A + not B) F = A minus B minus 1 F = A + not B F = A plus (A + B) F = A plus B F = A (not B) plus (A + B) F = (A + B) F = A F = A B plus A F= A (not B) plus A F = A

Cn = 1 F = A F = A B F = A (not B) F = zero F = A plus (A + not B) plus 1 F = A B plus (A + not B) plus 1 F = (A + not B) plus 1 F = A minus B F = (A + not B) plus 1 F = A plus (A + B) plus 1 F = A (not B) plus (A + B) plus 1 F = (A + B) plus 1 F = A plus A plus 1 F = AB plus A plus 1 F = A (not B) plus A plus 1 F = A plus 1

Selection M = 1 M = 0, Arithmetic Functions



Arithmetic Logic Unit Design74181 TTL ALU

Note that the sense of the carry in and out are OPPOSITE from the input bits

Fortunately, carry lookahead generatormaintains the correct sense of the signals

181A3A2A1A0B3B2B1B0

CnM

S3 S2 S1 S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

16

17

18

19

20

21

22

23182

P3P2P1P0G3G2G1G0

Cn

Cn+z

Cn+x

PG

Cn+y

13

31

14542

156

12119

107




16-bit ALU with Carry Lookahead

182P3P2P1P0G3G2G1G0Cn

Cn+z

Cn+x

PG

Cn+y

1331

14542

156

12119

107

181A3A2A1A0B3B2B1B0CnM

S3S2S1S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23


S3S2S1S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23


S3S2S1S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23


S3S2S1S0

F3F2F1F0

A=B

GP

Cn+41

2

3 4 5 6

78

9101113

14

15

1617

18

19

20

21

22

23

C0

C16



BCD Addition

BCD Number Representation

Decimal digits 0 thru 9 represented as 0000 thru 1001 in binary

Addition:

5 = 0101

3 = 0011

1000 = 8

5 = 0101

8 = 1000

1101 = 13!

Problemwhen digit

sum exceeds 9

Solution: add 6 (0110) if sum exceeds 9!

5 = 0101

8 = 1000

1101

6 = 0110

1 0011 = 1 3 in BCD

9 = 1001

7 = 0111

1 0000 = 16 in binary

6 = 0110

1 0110 = 1 6 in BCD



BCD Addition

Adder Design

Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

F A F A F A F A

F A F A

Cin

A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0

Cout S 3 S 2 S 1 S 0

0

CO CI

S

CO CI

S

CO CI

S

CO CI

S

CO CI

S

CO CI

S

1 1XX A1

A2 1X1X



Combinational MultiplierBasic Concept

multiplicand

multiplier

1101 (13)

1011 (11)

1101

1101

0000

1101

*

10001111 (143)

Partial products

product of 2 4-bit numbersis an 8-bit number



Combinational Multiplier

Partial Product Accumulation

A0

B0

A0 B0

A1

B1

A1 B0

A0 B1

A2

B2

A2 B0

A1 B1

A0 B2

A3

B3

A2 B0

A2 B1

A1 B2

A0 B3

A3 B1

A2 B2

A1 B3

A3 B2

A2 B3A3 B3

S6 S5 S4 S3 S2 S1 S0S7



Combinational MultiplierPartial Product Accumulation

Note use of parallel carry-outs to form higher order sums

12 Adders, if full adders, this is 6 gates each = 72 gates

16 gates form the partial products

total = 88 gates!

A 0 B 0 A 1 B 0 A 0 B 1 A 0 B 2 A 1 B 1 A 2 B 0 A 0 B 3 A 1 B 2 A 2 B 1 A 3 B 0 A 1 B 3 A 2 B 2 A 3 B 1 A 2 B 3 A 3 B 2 A 3 B 3

HA

S 0 S 1

HA

F A

F A

S 3

F A

F A

S 4

HA

F A

S 2

F A

F A

S 5

F A

S 6

HA

S 7



Combinational MultiplierAnother Representation of the Circuit

A3 B0

SC

A2 B0

SC

A1 B0

SC

A0 B0

SC

A3 B1

SC

A2 B1

SC

A1 B1

SC

A0 B1

SC

A3 B2

SC

A2 B2

SC

A1 B2

SC

A0 B2

SC

A3 B3

SC

A2 B3

S

A1 B3

S

A0 B3

S

B0

B1

B2

B3

P7 P6 P5 P4 P3 P2 P1 P0

A3 A2 A1 A0

Building block: full adder + and

4 x 4 array of building blocks

F A

X

Y

A B

S CI CO

Cin Sum In

Sum Out Cout



Case Study: 8 x 8 Multiplier

TTL Multipliers

Two chip implementation of 4 x 4 multipler

2 8 4

A 3

A 2

A 1

A 0

B 3

B 2

B 1

B 0

Y 7

Y 6

Y 5

Y 4

G A

G B 2

8 5

A 3

A 2

A 1

A 0

B 3

B 2

B 1

B 0

Y 3

Y 2

Y 1

Y 0

G A

G B

7 7

A 2

13 14 13 14 5 5

A 0

6 6

A 1

4 4

A 3

3 15

B 0

2 1

B 1

1 2

B 2

15 3

B 3

12

Y 4

9

Y 3

9

Y 7

10

Y 6

1 1

Y 5

12

Y 0

1 1

Y 1

10

Y 2



Case Study: 8 x 8 MultiplierProblem Decomposition

How to implement 8 x 8 multiply in terms of 4 x 4 multiplies?

A7-4

B7-4

A3-0

B3-0*

A3-0 * B3-0

A7-4 * B3-0

A3-0 * B7-4

A7-4 * B7-4

= PP0

= PP1

= PP2

= PP3

P15-12 P11-8 P7-4 P3-0

8 bit products

P3-0 = PP0

P7-4 = PP0 + PP1 + PP2

P11-8 = PP1 + PP2 + PP3

P15-12 = PP3

3-0

3-0 3-0 3-0

7-4 7-4 3-0

7-4

+ Carry-in

+ Carry-in

+ Carry-in




Calculation of Partial Products

Use 4 74284/285 pairs to create the 4 partial products

4 x 4 Multiplier 74284/285

A7A6

A5A4

B7B6

B5B4

PP37-4

PP33-0


A3A2

A1A0

B7B6

B5B4

PP27-4

PP23-0


A7A6

A5A4

B3B2

B1B0

PP17-4

PP13-0


A3A2

A1A0

B3B2

B1B0

PP07-4

PP03-0




Three-At-A-Time Adder

Clever use of the Carry Inputs

Sum A[3-0], B[3-0], C[3-0]:

Two Level Full Adder Circuit

Note: Carry lookahead schemes also possible!

FA

FA

A0 B0

C0

0

S0

FA

FA

A1 B1

S1

C1FA

FA

A2 B2

C2

S2

FA

A3 B3

S3

C3



Case Study: 8 x 8 MultiplierThree-At-A-Time Adder with TTL Components

Full Adders(2 per package)

Standard ALU configured as 4-bitcascaded adder

(with internal carry lookahead)

Note the off-set in the outputs

B3 A3 B2 A2 B1 A1 B0 A0

F3 F2 F1 F0

CnGPCn+4

74181

+

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

S0

S1S2S3

A0B0C0A1B1C1A2B2C2A3B3C3




Accumulation of Partial Products

Just a case of cascaded three-at-a-time adders!

B3 A3 B2 A2 B1 A1 B0 A0

F3 F2 F1 F0

CnGPCn+4

74181

+

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

P4

P5P6P7

PP04

PP10

PP20

PP05

PP11PP2

1PP0

6

PP12

PP22

PP07

PP13PP2

3

B3 A3 B2 A2 B1 A1 B0 A0

F3 F2 F1 F0

CnGPCn+4

74181

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

Cn B A

Cn+1 S74183

P8

P9P10P11

PP14

PP24

PP30

PP15

PP25PP3

1PP1

6

PP22

PP32

PP17

PP27PP3

3

B3 A3 B2 A2 B1 A1 B0 A0

F3 F2 F1 F0

CnGPCn+4

74181

P13

P14P15

P12

PP34PP35PP36PP37




The Complete System

Partial Product Calculation 4 x 74284, 74285

8

A7-0

8

B7-0

4

PP37-4

4

PP33-0

4

PP27-4

4

PP23-0

4

PP17-4

4

PP13-0

4

PP07-4

4

PP03-0

P3-0

+

P4

P5P6P7P

8

GPCn+4

Cn

2 x 74183

74181

P9P10P11P

12

GPCn+4

Cn

2 x 74183

74181

P13P14P15

GPCn+4

Cn74181

4 4 4 4 44

0 PP34

PP3PP3PP37 56

Cn+xCn74182

G0P0G1P1G2P2G3P3

Cn+yCn+z

+



Case Study: 8 x 8 MultiplierPackage Count and Performance

4 74284/74285 pairs = 8 packages4 74183, 3 74181, 1 74182 = 8 packages 16 packages total

Partial product calculation (74284/285) = 40 ns typ, 60 ns max

Intermediate sums (74183) = 9 ns/20ns = 15 ns average, 33 ns max

Second stage sums w/carry lookahead

74LS181: carry G and P = 20 ns typ, 30 ns max

74182: second level carries = 13 ns typ, 22 ns max

74LS181: formations of sums = 15 ns typ, 26 ns max

103 ns typ, 171 ns max



Chapter Review

We have covered:

" Binary Number Representation positive numbers the same difference is in how negative numbers are represented twos complement easiest to handle: one representation for zero, slightly complicated complementation, simple addition

" Binary Networks for Additions basic HA, FA carry lookahead logic

" ALU Design specification and implementation

" BCD Adders Simple extension of binary adders

" Multipliers 4 x 4 multiplier: partial product accumulation extension to 8 x 8 case

chapter # 1: introductionkrerk/courses/2110251/part1.pdf · contemporary logic design introduction...

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