chapter 2 _cmos_process supplement ii
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Chapter 2CMOS Processing/Layout Supplement (II)
Twin-tub CMOS process1. Provide separate optimization of the n-type and p-type transistors2. Make it possible to optimize "Vt", "Body effect", and the "Gain" of n, p
devices, independently.3. Steps:
A. Starting material: an n+ or p+ substrate with lightly doped ->"epitaxial" or "epi" layer -> to protect "latch up"
B. Epitaxy"
a. Grow high-purity silicon layers of controlled thicknessb. With accurately determined dopant concentrationsc. Electrical properties are determined by the dopant and its
concentration in SiC. Process sequence
a. Tub formationb. Thin-Oxide constructionc. Source & drain implantations
d. Contact cut definitione. Metallization
Balanced performance of n and p devices can be constructed.(Substrate contacts are included in Fig.3.10)
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Form n-island(for p-device)
Form p-island(for n-device)
Anisotropic Etch
(7~8um)
or SiO2 ( )
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3.3 CMOS Process Enhancement (Interconnection)
3.3.1 Metal Interconnect
CMOS circuit =
CMOS logic process + Signal/Power/Clock-routing layers
- Contact: Metal1 (M1) to Poly or Diffusions (n+ , p+)
- Second-layer of metal (VIA1=M1 to M2)
- Note: M1 must be involved in any contact to underlying areas
EtchIsolationlayerForm aVIA
Contact
- such as polysilicon and diffusion (n+, p+)
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Layout Examples:
(A) Inverters
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(1) Vertical
diffusion(2) Horizontal
diffusion
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* Other Routing methods
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* Increase Beta Value (W/L)
- Increase W
- Place transistor back-to-back (2 beta)
- Round transistor (Donut connection) (4 beta)
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Layout of Transmission Gate
S
S
A B
Layout of 2-to1 Multiplexor
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3.4 Layout Design Rules
- Function: obtain a circuit with optimum yield in an area as well aspossible
- Performance yield
* Conservative design rules Functional circuit
Good yield
* Aggressive design rules Bad yield
Compact circuit/layout forlow cost and high speed
(A) Line width/spacing
Small open circuit
Close short circuit
(B) Spacing between two independent layers
- In process:
(a) Geometric features for mask-making and lithographical
(b) Interactions between different layers (e.g., poly + diffusion)
- Rules:a. Micro( )-based rules Industry (submicron)
b. Lambda-based rules: e.g.,, 1 =0.6um for 1.2 umCMOS process) for 4-1.2um Scalable CMOSprocess. 2 is the minimum channel length (L).
- See Table 3.2 and figures (next four pages)
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ayout Design Rules:L
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Contact Rules: There are several generally available contacts:
- Metal to p-active (p-diffusion)
- Metal to n-active (n-diffusion)
- Metal to Polysilicon
- VDD and V SS substrate contacts
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.4.5 Layer assignment (Table3.4)
- Split (Substrate contacts)
3
- CIF: Caltech Intermediate Form
- GDSII Format
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3.5 Latchup- Latchup : Shorting of VDD and Vss lines Chip breakdown
- Latchup Equivalent Circuit:
Vertical : pnp- p = source/drain of p device (Emitter)- n = n-well (Base)- p = p-substrate (Collector)
Lateral : npn- n = source/drain of n device (Emitter)- p= p-substrate (Base)
- n= n-well (Collector)
Rsubstrate, Rwell
- Parasitic devices and resistors
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* Observation to prevent latchup:
1. Reduce the resistor values
2. Reduce the gain of the parasitic devices
- Approach:
1. Latchup-resistant CMOS process
2. Layout techniques (see Section 3.5.4,3.5.5 of Neil WesteTextbook, or the supplement in next 3 pages)
* Technology-related CAD tools
- Design Rule Check (DRC): On-line DRC and Off-line (Dracula)(3.6.1)
- Circuit extraction (Layout Parameter Extraction, LPE) (3.6.2)
- CMOS process simulator (Process Input Description Language(PIDL))(Sec.3.9) and SUPREME by Stanford University.
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*Latch-up prevention (layout approach)
Prevent the diode from being forward biasedBy adding well ties and substrate Ties
The more well tie-downs you place, the less chance there is for thePN diode to become forward biased.
* Rule of thumb: There is no such thing as too many tie-downs.
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