chapter 2 switching algebra and logic circuits. switching algebra ( 开关代数 ) boolean algebra (...

Chapter 2Chapter 2Switching Algebra Switching Algebra

and and

Logic CircuitsLogic Circuits

Switching Algebra ( 开关代数 )

Boolean Algebra ( 布尔代数 )

Logic Circuits ( 逻辑电路 )

Logic Function ( 逻辑函数 )

OR ( 或 )

AND ( 与 )

NOT ( 非 )

NAND ( 与非 )

NOR ( 或非 )

EXCLUSIVE-OR ( 异或 )

Key wordsKey words

Complement ( 补 )

Product of Sums ( 或与 )

Truth Table ( 真值表 )

Karnaugh Map ( 卡诺图 )

Chapter 2 - SubjectsChapter 2 - Subjects

2.1 Definition of Switching Algebra 2.2 Basic Properties of Switching Algebra 2.3 Manipulation of Algebra Functions 2.4 Implementation of Functions with AND,

OR and NOT Gates 2.5 From the Truth Table to Algebraic

Expressions 2.6 Introduction to the Karnaugh Map 2.7 The Complement and Product of Sums 2.8 NAND, NOT, and Exclusive-OR Gates

2.9 Simplification of Algebra Expressions 2.10 Manipulation of Algebraic Functions

and NAND Gate Implementions 2.12 Solved Problems 2.13 Exercises

2.1 Definition of Switching Algebra2.1 Definition of Switching Algebra

Switching algebra is binary, that is, all variables( 变量） and constants （常量） take on one of two values, 0 and 1.

Quantities （量值） are not naturally binary must then be coded into binary format.

Gate : a gate is a circuit with one output that implement one of the basic functions.

such as OR, AND , NOT.

2.1 Definition of Switching Algebra2.1 Definition of Switching Algebra 1 Three Operators of switching algebra: (1) OR (+) a+b (read as a or b)

symbol:

EE

AA

BBFF

A

BF

国外常用符号国外常用符号

国内符号国内符号

Truth tableTruth table

A B F

0 0 0

0 1 1

1 0 1

1 1 1

运算规则：运算规则：有有 11 出出 11 ，全，全 00 为为00


A B F

0 0 0

0 1 0

1 0 0

1 1 1

(2) AND (•) ab (read as a AND b)

symbol:

EE

AA BB

FF国外常用符号国外常用符号


Ttruth tableTtruth table

&A

BF

运算规则：运算规则：有有 00 出出 00 ，全，全 11 为为11


1A F

(3) NOT (’) a ’ (read as NOT a)

symbol:

EE

AA

RRFF国外常用符号国外常用符号



A F(A’)

0 1

1 0

• 2 First Group of Properties:

P1a a+b=b+a

P1b ab=ba

P2a a+(b+c)=(a+b)+c

P2b a(bc)=(ab)c

Commutative property 交换律

Associative law 结合律

The deduction of OR and ANDThe deduction of OR and AND

We can extend the definition of OR to

a + b + c + d +… is 1 if any of the operands ( 操作数） (a, b, c , d… ) is 1;

is 0 only if all is 0

and the definition of AND extends to

a b c d… is 1 if all of the operands are 1 and is 0 if any is 0.

The Order of PrecedenceThe Order of Precedence

When evaluating expression without parentheses( 括号） , the order of precedence is

NOT

AND

OR

Example: ab’+c’d

=(a(b’))+((c’)d)

P3a a+0=a P3b a·1=a P4a a+1=1 P4b a·0=0 P5a a+a’=1 P5b a·a’= 0 P3aa 0+a=a P3bb 1·a=a P4aa 1+a=1 P4bb 0·a=0 P5aa a’+a=1 P5bb a’·a= 0 P6a a+a=a P6b a·a=a P7 (a’)’= a P8a a(b+c)=ab+ac P8b a+bc=(a+b)(a+c)

2.2 Basic Properties of Switching Algebra2.2 Basic Properties of Switching Algebra

P8bP8b 证明过程证明过程

Literal （字母） : is the appearance of a variable or its complement a , b’, c, c’

(1) Product term ( 与项 ): ab’ bc’d a’d e’

(2) Standard product term (minterm) ( 标准与项；最小项 ):

is a product term that includes each variable of the problem, either uncomplemented or complemented.

such as: w’xyz wxy’z x’zyw

(3) SOP: Sum of Products form ( 积之和式 / 与或式） is one or more product terms connected by OR opera

tors.

2.3 Manipulation of Algebraic Functions2.3 Manipulation of Algebraic Functions

(4) Canonical sum /sum of standard product terms

（标准和 / 标准与项和；最小项标准式 ; 最小项之和）

Is a sum of products expression where all of terms are standard product terms

ex. abc+a’bc+ab’c’

(5) Minimum sum of products:( 最简与或式 )

① fewest number of product terms

② fewest number of literals

(1) x’yz’ + x’yz + xy’z’ +xy’z + xyz

(2)x’y+xy’+xyz

(3) x’y+xy’+xz

(4) x’y+xy’+yz

判断上面属于哪种形式？判断这些函数是否相等？


P9a ab+ab’=a P9b (a+b)(a+b’)=a

利用上面的公式可完成（利用上面的公式可完成（ 11 ）到（）到（ 22 ）的证明）的证明

利用利用 P6aP6a 可完成（可完成（ 11 ）到（）到（ 33 ）（）（ 44 ）的证明）的证明

（ 2）到 (3) (4)的证明给出下面的公式 P10a a+a’b=a+b P10b a(a’+b)=ab

a+a’b=(a+a’)(a+b) P8b =1 (a+b) = a+b

(6) Sum term ( 或项 ) ： a+b’+c , b’ (just one literal)(7) Standard sum term (maxtern) ( 标准或项；最大项 ) ： is a sum term that includes each variable of the problem, either u

ncomplemented or complemented. such as: w’+x+y+z , w+x+y’+z , x’+z+y+w (8) POS: Product of sums ( 和之积式 / 或与式）


(9) Canonical product /product of standard sum terms

( 标准与 / 标准或与项；最大项标准式 )

is a product of sums expression where all of the terms are standard sum terms.

(10) Minimum product of sum ( 最简或与式 )

①fewest number of sum terms

②fewest number of literals

Ex.Ex.

(1) a’b+ad

(2) (a+b) (c+a’d)

(3) a’+b’

(4) (a+b’)(b+c)(a’+c+d)

(5) abcd+a’b’c’d+abc’d

(6) (a+b+c+d’)(a’+b’+c+d)(a+b’+c+d)

2.4 Implementation of functions with AND, OR, 2.4 Implementation of functions with AND, OR, and NOT Gatesand NOT Gates

1 Block diagram of f in sum of standard products form f=x’yz’+x’yz+xy’z’ +xy’z+xyz

OR

x'yz'x'yzxy'z'xy'zxyz

f

This implementation assumes that all of the inputs are avThis implementation assumes that all of the inputs are availabe both ailabe both uncomplemented uncomplemented and and complementedcomplemented..

This is an example of a This is an example of a two-level circuittwo-level circuit. . The numThe number of levelsber of levels is the maximum number of gates is the maximum number of gates through through whichwhich a signal must pass from the input to the output. a signal must pass from the input to the output. When inputs are available both uncomplemented aWhen inputs are available both uncomplemented and complemented, implementations of nd complemented, implementations of both sum of prodboth sum of product and product of sum expressionsuct and product of sum expressions result in result in two-level ctwo-level circuitsircuits..

The same function f can be manipulated to a sum of products expression (SOP Form):

f=x’yz’+x’yz+xy’z’+xy’z+xyz+xy’z =x’y(z’+z)+xy’(z’+z)+xz(y+y’) =x’y+xy’+xz

f=x’yz’+x’yz+xy’z’ +xy’z+xyz

x'y

xy'

xz

f

The The simplest definitionsimplest definition of minimum for a gate network is of minimum for a gate network is minimum number of gatesminimum number of gates and, among those with the same nu and, among those with the same number of gates, mber of gates, minimum number of gate inputsminimum number of gate inputs. .

a+a=aa+a=a

Here,Here,a=xy’za=xy’z

complementedcomplemented

2 A product of sums expression (POS) corresponds to a two-level OR-AND network.

f=(x+y)(x’ +y’ +z)

ORxy

x'y'z

f

3 neither SOP nor POS form:

h=z’+wx’ y+v(xz+w’)

ORxzw'v

wx'y

h

z'

The resulting circuits are more than two levels.

4 not complement4 not complement

If complemented inputs are not available, then an inverter (a not gate) is needed for each input that required to be complemented.

xy

z

f

Show a block diagram of a circuit using AND and OR gates for each side of P8b:

a + b c = (a + b) (a + c)

a

b

c

a(a+b)(a+c)

a

bc

a+bc

Gates are typically available in Gates are typically available in dual in-line dual in-line packagespackages (DIPs).(DIPs). These packages are often These packages are often referred to as referred to as chipschips..

Integrated circuits Integrated circuits (ICs)(ICs) can be categorized as: can be categorized as:SSI:SSI: Small-scale integration Small-scale integration

MSI:MSI: Medium-scale integration Medium-scale integration LSI:LSI: Large-scale integration Large-scale integration

VLSI: VLSI: Very large-scale integrationVery large-scale integration

Transistor-Transistor Logic (TTL)Transistor-Transistor Logic (TTL)

Common AND, OR and NOT integrated circuits: 7404 6(Hex) NOT gates 7408 4(quadruple) two-input AND gates 7411 3(triple) three-input AND gates 7421 2(dual) four-input AND gates 7432 4(quadruple) two-input OR gates

1 2 3 4 5 6 7

891011121314

GND

VCC

7404

ExampleExample

7.Show a block diagram of a system using AND,OR and NOT gate to implement the following function. Assume that variable are available only uncomplemented.

F=(A(B+C)’+BDE)(A’+CE)

B

C

A

BDE

CE

A

F

8. For each of the following circuits

I find an algebraic expression

II put it in sum of product form.

a.

a.I g=(d+e)c’+cde’

II g=c’d+c’e+cde’

de

c

c

de

g

2.5 From the truth table to algebraic expressions2.5 From the truth table to algebraic expressions

A two-variable truth table

There are 4 possible combinations of inputs.

a b f0 0 0

0 1 1

1 0 1

1 1 1

f = a’b+ab’+ab

f = m1+m2+m3

=∑m(1,2,3)

f is 1 if a=0 and b=1 or

if a=1 and b=0 or

if a=1 and b=1

f is 1 if a=0 and b=1 or

if a=1 and b=0 or

if a=1 and b=1

What the table says is that:

This is the same as saying:

f is 1 if a’=1 and b=1 or

if a =1 and b’=1 or

if a=1 and b=1

This is the same as saying:

f is 1 if a’=1 and b=1 or

if a =1 and b’=1 or

if a=1 and b=1

11 1

11 0

10 1

00 0

fa b

Each rowEach row of the truth table corresponds to a of the truth table corresponds to a product termproduct term. .

A sum of products expressionA sum of products expression is formed by is formed by ORingORing those produ those product terms ct terms corresponding to rows of the truth table for which the functcorresponding to rows of the truth table for which the function is 1ion is 1. Each . Each product termproduct term has each variable included, with that va has each variable included, with that variable riable complementedcomplemented when the entry in the input column for that va when the entry in the input column for that variable contains a riable contains a 00 and and uncomplementeduncomplemented when it contains a when it contains a 11..

These product terms include all of the variables,These product terms include all of the variables, they are they are mintermsminterms. . MintermsMinterms are oftern referred t are oftern referred to by o by numbernumber, by just , by just converting the binary number converting the binary number in the input row of the truth table to decimalin the input row of the truth table to decimal..

m77ABC111

m66ABC’110

m55AB’C101

m44AB’C’100

m33A’BC011

m22A’BC’010

m11A’B’C001

m00A’B’C’000

markednumberMintermabc

For a For a three-variablethree-variable function, the minterms and minterm function, the minterms and minterm numbers that are used for all functions of three variables.numbers that are used for all functions of three variables.

Minterms Minterms (( 最小项最小项 ))

Example 2.2Example 2.2ABC

000001010011100101110111

f f’

0 11 01 01 01 01 00 10 1

We should write the function of We should write the function of ff and its complement and its complement f ’.f ’.


f(f(A,B,CA,B,C)=∑m(1,2,3,4,5))=∑m(1,2,3,4,5)

=A’B’C+A’BC’+A’BC+AB’C’+AB’C=A’B’C+A’BC’+A’BC+AB’C’+AB’C

f f ’’((A,B,CA,B,C)=∑m(0,6,7))=∑m(0,6,7)=A’B’C’+ABC’+ABC=A’B’C’+ABC’+ABC

Note that: Note that: The two sum of minterm forms are sum of product expThe two sum of minterm forms are sum of product expressions. ressions. ButBut in most casesin most cases, including this one, , including this one, the sum of minterms ethe sum of minterms expressionxpression is not a is not a minimum sum of products expressionminimum sum of products expression..

is the simplest way to is the simplest way to specify the functionsspecify the functions

f(A,B,C)= ∑m(1,2,3,4,5) =a’b’c+a’bc’+a’bc+ab’c’+ab’c =a’b’c+a’b+ab’ =a’c+a’b+ab’ =b’c+a’b+ab’

minimum sum of products expression:minimum sum of products expression:


Example 2.3Example 2.3 If the function includes If the function includes don’t caresdon’t cares, then those , then those terms are included in a terms are included in a separate sumseparate sum ( (∑).∑).

What is don’t care?What is don’t care?

abc

000001010011100101110111

f

×11

× 0100

In some systems, the value of the output is specified for only In some systems, the value of the output is specified for only some some of the input conditionsof the input conditions. (Such functions are sometimes referred to . (Such functions are sometimes referred to as as incompletely specified functionsincompletely specified functions.) For the remaining input .) For the remaining input combinations, it does not matter what the output is, that is, we combinations, it does not matter what the output is, that is, we don’t caredon’t care. .

In truth table, don’t care are indicated by an In truth table, don’t care are indicated by an “x”“x”

Don’t care(Don’t care( 无关项）无关项）无关项： 1 、约束项：在某些系统中，输入变

量的取值不是任意的，也就是说某些输入变量的组合不存在。

2 、任意项：输入变量取值后，输出既可以是 0 ，也可以是 1 ，对最终的输出不影响。这种情况多存在于中间过程中。

Ex.Ex. 约束项：三个逻辑变量 A,B,C 表示一台电机的正

转，反转和停止。 A=1 表示正转， B ＝ 1 表示反转，C ＝ 1 表示停止。因为电动机任何时候只能执行一个命令，所以两个变量不能同时为 1 ，即： ABC=001,010,100, 不能为 000 ， 011 ， 101 ， 110 ， 111 。可表示为：

a’b’c’+a’bc+ab’c+abc’+abc=0 任意项：多存在于中间系统中。

a

b

csystem1

j

kz

system2


Example 2.3Example 2.3 If the function includes If the function includes don’t caresdon’t cares, then those , then those terms are included in a terms are included in a separate sumseparate sum ( (∑).∑).

abc

000001010011100101110111

f

×11

× 0100

f(f(a,b,ca,b,c)=∑m(1,2,5))=∑m(1,2,5)+∑d(0,3)+∑d(0,3)

We can writeWe can write

Example:Example:

3 人表决器 truth table

A B C F

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Algebraic expressionAlgebraic expressionf=a’bc+ab’c+abc’+abcf=a’bc+ab’c+abc’+abc

f(a,b,c)=∑m(3,5,6,7)f(a,b,c)=∑m(3,5,6,7)

Example Example

举重裁判电路 :A B C F

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

F=AB’C+ABC’+ABCF=AB’C+ABC’+ABC

F=∑m(5,6,7)F=∑m(5,6,7)

Ex.Ex.A system to do 1 bit of binary addition, it has three inputA system to do 1 bit of binary addition, it has three inputs(the 2 bits to be added plus the carry from the next order s(the 2 bits to be added plus the carry from the next order bit) and prouces two outputs, a sum bit and a carry to the bit) and prouces two outputs, a sum bit and a carry to the next higher order position.next higher order position.

a b Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

CCoutout=a’bc+ab’c+abc’+abc=a’bc+ab’c+abc’+abc

S=a’b’c+a’bc’+ab’c’+abcS=a’b’c+a’bc’+ab’c’+abc

2.6 Introduction to the 2.6 Introduction to the KarnaughKarnaugh map map

The Karnaugh map consists of The Karnaugh map consists of one squareone square for for each peach possible mintermossible minterm in a function. in a function. Thus, a two-variable map has 4(2Thus, a two-variable map has 4(222) squares, a three-) squares, a three-variable map has 8(2variable map has 8(233) squares, and a four-variable map ) squares, and a four-variable map has 16(2has 16(244) squares.) squares.

Two-variable Karnaugh map

ABA’B1

AB’A’B’0

10BA

m3m11

m2m00

10BA

2.6 Introduction to the 2.6 Introduction to the KarnaughKarnaugh map (Con.) map (Con.)

Three-variable karnaugh map

A’BC

A’BC’

01

ABC

ABC’

11 1000

AB’CA’B’C1

AB’C’A’B’C’0

ABC

m3

m2

01

m7

m6

11 1000

m5m11

m4m00

ABC

Note: Note: the last two columns are not in numeric order, by organizthe last two columns are not in numeric order, by organizing the map with ing the map with gray codesgray codes, the minterms in , the minterms in adjacent squaresadjacent squares can can

always be combined usingalways be combined usingP9a. ab+ab’=a(b+b’)=aP9a. ab+ab’=a(b+b’)=a

gray codegray code

Four-variable karnaugh map


AB’CD’ABCD’A’BCD’A’B’CD’10

AB’CDABCDA’BCDA’B’CD11

AB’C’DABC’DA’BC’DA’B’C’D01

AB’C’D’ABC’D’A’BC’DA’B’C’D’00

10110100ABCD

m10m14m6m210

m11m15m7m311

m9m13m5m101

m8m12m4m000

10110100ABCD

gray codesgray codes

gray codesgray codes


When we When we plot a functionplot a function, we put a , we put a 11 in each square correspondin in each square corresponding to a g to a minterm that is included in the functionminterm that is included in the function, and put a , and put a 00 in in or leave or leave blank those squares not included in the functionblank those squares not included in the function. For functions with . For functions with don’t caresdon’t cares, an , an ×× or or φφ goes in the square for which the minterm is a d goes in the square for which the minterm is a d

on’t care (on’t care (We can see that as 0 or 1We can see that as 0 or 1).).

Examples:Examples:

f(a,b)=∑m(0,3)f(a,b)=∑m(0,3) f(a,b)=∑m(0,3)+f(a,b)=∑m(0,3)+∑d(2)∑d(2)

11

10

10ba

11

φφ10

10ba

Assume: the order is abAssume: the order is ab

In adjacent In opposite

10

11

1101

00

10110100ABCD

1110

11

01

00

10110100ABCD

CD

11

11

10

11

01

00

10110100ABCD

11

11

10

11

01

00

10110100AB

adjacent squaresadjacent squares can always be combined can always be combined

AABBC’D+AC’D+AB’B’C’D=A(C’D=A(B+B’B+B’)C’D=AC’D)C’D=AC’D A’A’B’CD+B’CD+AAB’CD=(B’CD=(A’+AA’+A)B’CD=B’CD)B’CD=B’CD

∑∑m(0,2,8,10)=B’D’m(0,2,8,10)=B’D’ ∑∑m(5,7,13,15)=BDm(5,7,13,15)=BD

2211

2222

adjacent squaresadjacent squares can always be combined can always be combined

1

1

1

1

10

11

01

00

10110100ABCD

11

11

10

11

01

00

10110100ABCD

11

11

11

11

10

11

01

00

10110100ABCD

1111

1111

10

11

01

00

10110100ABCD

∑∑m(12,13,14,15)=ABm(12,13,14,15)=AB ∑∑m(1,3,9,11)=B’Dm(1,3,9,11)=B’D

∑∑m(0,1,2,3,8,9,10,11)=B’m(0,1,2,3,8,9,10,11)=B’ ∑∑m(1,3,5,7,9,11,13,15)=Dm(1,3,5,7,9,11,13,15)=D

2222

2233


6

7

112

3

01

1

4

5

0

10

1000abc

In reading the map, it is useful to label the pairs of In reading the map, it is useful to label the pairs of the columnsthe columns BB

AA

CC

m10m14m6m210

m11m15m7m311

m9m13m5m101

m8m12m4m000

10110100ABCD

BB

DDCC

AA


The easiest way to identify the term from the map is by determining in which row and column all of the 1’s are located.

110

11111

11101

100

10110100ABCD

A’B’A’B’

DD

AA

F(A,B,C,D)=A’B’+ADF(A,B,C,D)=A’B’+AD


P9aa. P9aa. a’b’+a’b+ab+ab’=1a’b’+a’b+ab+ab’=1

P9bb. (a’+b’)(a’+b)(a+b)(a+b’)=0P9bb. (a’+b’)(a’+b)(a+b)(a+b’)=0

1

11

1

01

1110

1000abc

A’B’C+A’BC+ABC+AB’C=C(A’B+A’B+AB+AB’)A’B’C+A’BC+ABC+AB’C=C(A’B+A’B+AB+AB’)

f=b’c’+a’bf=b’c’+a’b

f=b’c’+a’b+f=b’c’+a’b+a’c’a’c’

ExamplePlot the K-Map of Plot the K-Map of ff

11

1

1

01

1

110

1000abc

f=a’b’c’+a’bc’+a’bc+ab’c’f=a’b’c’+a’bc’+a’bc+ab’c’

a minimum sum of product a minimum sum of product solutions, how to find a solutions, how to find a minimum term solutions in minimum term solutions in Chap 3Chap 3

Example

Write the function of Write the function of ff

1

11

1

1

01

11

10

1000abc

f=a’b+ab’+acf=a’b+ab’+ac

1

11

1

1

01

11

10

1000abc

f=a’b+ab’+bcf=a’b+ab’+bc

ExampleExample

Plot the following functions on a karnaugh

F= BD’+ABC+AD+A’B’C

11110

11111

1101

1100

10110100ABCD

Example Example

1.p’q’r +p’qr’+p’qr+pqr’+pq’r’1.p’q’r +p’qr’+p’qr+pqr’+pq’r’

1

0

r

11

1

1

01

1 1

1000pq

11f=p’r+p’q+pr’f=p’r+p’q+pr’

11

1

1

01

1 1

1000pq

11

r

f=p’r+qr’+pr’f=p’r+qr’+pr’0

1

2. x’y’z’+x’y’z+x’yz+xy’z+xyz+xyz’2. x’y’z’+x’y’z+x’yz+xy’z+xyz+xyz’

11

1

1

01

1

1

1000xy

11

z0

1 11

F=z+x’y’+xyF=z+x’y’+xy

2.7 the complement and product of sums2.7 the complement and product of sums

DeMorgan’sDeMorgan’s theorem theorem ( 迪摩根定律 ): P11a (a+b)’=a’b’ P11b (ab)’=a’+b’ P11aa (a+b+c…)’=a’b’c’… P11bb (abc…)’=a’+b’+c’…

Caution Caution (( 注意注意 ):):

(ab)’ ≠a’b’ rather (ab)’=a’+b’

(a+b)’ ≠a’+b’ rather (a+b)’ =a’b’

(0·1)’=0’+1’=0’=1 0’ ·1’=1 ·0=0

a ba b

0 00 00 10 111 001 11 1

a+b a+b (a+b)’(a+b)’ a’ b’ a’ b’ a’b’a’b’

0 0 11 1 1 1 1 111 1 00 1 0 1 0 001 1 00 0 1 0 1 001 1 00 0 0 0 0 00

ab ab (ab)’ (a’+(ab)’ (a’+b’)b’)0 0 1 11 1

0 0 1 11 10 0 1 11 11 1 0 00 0

The simplest proof of these propertyThe simplest proof of these property

Thus, when we are given a function, f(w,x,y,z),Thus, when we are given a function, f(w,x,y,z), and need to find its complement, f ’(w,x,y,z). The and need to find its complement, f ’(w,x,y,z). The straightforward approachstraightforward approach is to use is to use DeMorgan’s DeMorgan’s ththeorem repeatedly.eorem repeatedly.

Example 2.12

f = wx’y+xy’+wxzf = wx’y+xy’+wxz

f ’= wx’y+xy’+wxzf ’= wx’y+xy’+wxz= (wx’y)(xy’)(wxz)= (wx’y)(xy’)(wxz)

= (w’+x+y’)(x’+y)(w’+x’+z’)= (w’+x+y’)(x’+y)(w’+x’+z’)

Assume that:Assume that: a=wx’ya=wx’y b=x’yb=x’y c=wxzc=wxzthus,thus,

a+b+c=a’b’c’a+b+c=a’b’c’

Note that if the function is in Note that if the function is in sum of products formsum of products form, , the the complement is in product of sums formcomplement is in product of sums form (and the (and the

complement of a product of sums expressioncomplement of a product of sums expression is a is a sum sum of products oneof products one).).

How to find the complement of more general expressions?

To find the complement of more general expressions, we can repeatedly apply DeMorgan’s theorem or we

can follow this set of rules:

1. Complement each variable (that is, a to a’, a’ to a).

2. Replace 0 by 1 and 1 by 0.

3. Replace AND by OR and OR by AND, being sure to p

reserve the order of operations. That sometimes requi

res additional parentheses ( 括号 ).

Example 2.11Example 2.11

f=ab’(c+d’e)+a’bc’f=ab’(c+d’e)+a’bc’

Note that in f, the Note that in f, the last operationlast operation to be performed is an to be performed is an OROR of the of the complex first termcomplex first term with the with the product termproduct term..

To To preserve the orderpreserve the order, , parentheses were neededparentheses were needed in f ’, making the in f ’, making the AND the last operation.AND the last operation.

f ’=ab’(c+d’e)+a’bc’f ’=ab’(c+d’e)+a’bc’ ==[[a’+b+c’(d+e’)a’+b+c’(d+e’)]]∙∙((a+b’+ca+b’+c))we can repeatedly apply DeMorgan’s theoremwe can repeatedly apply DeMorgan’s theorem

==[[ab’(c+d’e)ab’(c+d’e)]]++((a’bc’a’bc’))

==[[ab’(c+d’e)ab’(c+d’e)]]∙∙((a’bc’a’bc’))

==[[a’+b+c’(d+e’)a’+b+c’(d+e’)]]∙∙((a+b’+ca+b’+c))

==[[a’+b+(c+d’e)a’+b+(c+d’e)]]∙∙((a+b’+ca+b’+c))

M7

M6

M5

M4

M3

M2

M1

M0

marked

m7’

m6’

m5’

m4’

m3’

m2’

m1’

m0’

compared

7a’+b’+c’111

6a’+b’+c110

5a’+b+c’101

4a’+b+c100

3a+b’+c’011

2a+b’+c010

1a+b+c’001

0a+b+c000

numberMaxtermabc

Maxterms Maxterms (( 最大项最大项 ))Each Each sum termsum term has each variable included, with that variable has each variable included, with that variable complemcomplementedented when the entry in the input column for that variable contains a when the entry in the input column for that variable contains a 11

and and uncomplementeduncomplemented when it contains a when it contains a 00..

MM00=a+b+c=a+b+c

mm00=a’b’c’=a’b’c’

mm00’=(a’b’c’)’’=(a’b’c’)’

=a+b+c=a+b+c =M=M00

MMii=m=mii’’

10111

10110

01101

01100

01011

01010

01001

10000

f’fabc

Example :Example : Write the expression f(a,b,c)f(a,b,c)= ∑m(1,2,3,4,5)= ∑m(1,2,3,4,5)

=a’b’c+a’bc’+a’bc+ab’c’+ab’c=a’b’c+a’bc’+a’bc+ab’c’+ab’c

=a’b’c+a’b+ab’=a’b’c+a’b+ab’

=a’c+a’b+ab’=a’c+a’b+ab’

=b’c+a’b+ab’=b’c+a’b+ab’

f ’(a,b,c)f ’(a,b,c)= ∑m(0,6,7)= ∑m(0,6,7)

=m0+m6+m7=m0+m6+m7

f=(f ’)’=(m0+m6+m7)f=(f ’)’=(m0+m6+m7)

=m=m00’m’m66’m’m77’’

=M=M00MM66MM77

=(a+b+c)(a’+b’+c)(a’+b’+c’)=(a+b+c)(a’+b’+c)(a’+b’+c’)POS: MaxtermsPOS: Maxterms

2.8 2.8 NANDNAND, , NORNOR, , andand EXCLUSIVE-OREXCLUSIVE-OR gates gates

In this section, we will introduce three other commonly useIn this section, we will introduce three other commonly used types of gates,the d types of gates,the NANDNAND, , NORNOR and and Exclusive-ORExclusive-OR, and se, and se

e how to implement circuits using them.e how to implement circuits using them.

Why use Why use NANDNAND and and NORNOR gates, rather than gates, rather than ANDAND, , OROR

and and NOT NOT ??

Because these operators are said to be Because these operators are said to be functionally cofunctionally completemplete(( 功能完备的功能完备的 ). That is, we could implement AND, ). That is, we could implement AND,

OR, and NOT gates using OR, and NOT gates using onlyonly NANDs or NORs. NANDs or NORs.Thus, the Thus, the NANDNAND or or NORNOR is more is more convenientconvenient to imple to imple

ment than the AND or OR.ment than the AND or OR.

NAND gates:NAND gates:

a

b (ab)'wx (wxyz)'yz

(ab)’=a’+b’(ab)’=a’+b’ a

ba' +b' =(ab)' a

ba'+b’=(ab)’

a b f0 00 00 10 11 01 01 11 1

11111100


有有 0 0 出出 11 ，全，全 11 为零为零

(a+b)’=a’b’(a+b)’=a’b’

a

b (a+b)'

NOR gates:NOR gates:ab

(a+b+c)'

c

a

ba'b'=(a+b)'

a

ba'b’=(a+b)’

a b f0 00 00 10 11 01 01 11 1

11000000


有有 11 出出 00 ，全，全 00 为为 11

Because these operators are said to be Because these operators are said to be functionally cofunctionally completemplete(( 功能完备的功能完备的 ). That is, we could implement AND, ). That is, we could implement AND,

OR, and NOT gates using OR, and NOT gates using onlyonly NANDs or NORs. NANDs or NORs.

a

bf

a

b

f

x'y

xy'

xz

f

The function f=x’y+xy’+xz, we first implemented with AND and OR gates.

But note that the property oBut note that the property of (a’)’=a, we havef (a’)’=a, we have

f=(f ’)’=(x’y+xy’+xz)f=(f ’)’=(x’y+xy’+xz)

=(x’y)(xy’)(xz)=(x’y)(xy’)(xz)

x'y

xy'

xz

f

That is, all of the That is, all of the ANDAND and and OROR gates gates of the original circuit become of the original circuit become NANDsNANDs, ,

Nothing elseNothing else was changed. was changed.

How to implement circHow to implement circuits using uits using NANDsNANDs??

How to implement circuits using How to implement circuits using NANDsNANDsThis process can be greatly simplified when we have a ciThis process can be greatly simplified when we have a ci

rcuit rcuit consisting of AND and ORconsisting of AND and OR gates such gates such that that

1. The 1. The output of the circuitoutput of the circuit comes from an comes from an OROR;;

2. The 2. The inputs to all OR gatesinputs to all OR gates come either from a come either from a system inputsystem input or from the or from the output of an ANDoutput of an AND;;

3. The 3. The inputs to all AND gatesinputs to all AND gates come either from a come either from a system inputsystem input or from or from the output of an ORthe output of an OR..

All gates are All gates are replaced by NAND gatesreplaced by NAND gates, and any , and any input coming input coming directly into an ORdirectly into an OR is is

complementedcomplemented..

x'y

xy'

xz

f

x'y

xy'

xz

f

A’+B’+C’=(ABC)’A’+B’+C’=(ABC)’x'y

xy'

xz

f

AA

BB

CC

How to implement circuits using How to implement circuits using NANDs NANDs (Con.)(Con.)

h=z’+wx’y+v(xz+w’)h=z’+wx’y+v(xz+w’)xzw'vwx'yz'

h

h=(h’)’=z’+wx’y+v(xz+w’)h=(h’)’=z’+wx’y+v(xz+w’) =z(wx’y)(vxz)(vw’)=z(wx’y)(vxz)(vw’)wx'yvxzvw'z

h

Example 2.13: Example 2.13: f=wx(y+z)+x’yf=wx(y+z)+x’yyz wx

x'y

f

f=(f ’)’=wx(y+z)+x’yf=(f ’)’=wx(y+z)+x’y =wxy+wxz+x’y=wxy+wxz+x’y

=(wxy)(wxz)(x’y)=(wxy)(wxz)(x’y)

xywxzx'y

f

The function of The function of sum of product form sum of product form (SOP)(SOP) can be easily implemented with can be easily implemented with NAND gates.NAND gates.

The dual approach works for implementing circuits with NOR gates.The dual approach works for implementing circuits with NOR gates.

When we have a circuit When we have a circuit consisting of AND and ORconsisting of AND and OR gates s gates suchuch that that

1. The 1. The output of the circuitoutput of the circuit comes from an comes from an ANDAND;;

2. The 2. The inputs to OR gatesinputs to OR gates come either from a come either from a system inputsystem input or from the or from the output of an ANDoutput of an AND;;

3. The 3. The inputs to AND gatesinputs to AND gates come either from a come either from a system inputsystem input or from or from the output of an ORthe output of an OR..

Then all gates can be Then all gates can be converted to NORconverted to NOR gates, gates, and, if an input comes and, if an input comes directly into an AND gate, directly into an AND gate,

that input must be complementedthat input must be complemented..

How to implement circuits using How to implement circuits using NORs?NORs?

xy'x'yx'z'

g


Example 2.14: g=(x+y’)(x’+y)(x’+z’)

xy'x'yx'z'

g

A’B’C’=(A+B+C)’A’B’C’=(A+B+C)’

AA

BB

CC

xy’

x'yx'z'

g


Example 2.14: Example 2.14: g=(x+y’)(x’+y)(x’+z’)g=(x+y’)(x’+y)(x’+z’)

g=(g’)’=(x+y’)(x’+y)(x’+z’)g=(g’)’=(x+y’)(x’+y)(x’+z’)

=(x+y’)+(x’+y)+(x’+z’)=(x+y’)+(x’+y)+(x’+z’)

xy’

x'yx'z'

g

Exclusive-OR gate implements the expressionExclusive-OR gate implements the expression

f=a’b+ab’f=a’b+ab’

ab

a b ⊕a b ⊕

Written asWritten as aa⊕⊕b b

Exclusive-OR (Exclusive-OR (XOR: XOR: 异或异或 ) gate) gate

a b f0 00 00 10 11 01 01 11 1

00111100

a b is 1 if a=1 and b=0 or⊕a b is 1 if a=1 and b=0 or⊕ if b=1 and a=0 , if b=1 and a=0 ,

but not bothbut not both a=1 and b=1.a=1 and b=1.

Symbol asSymbol as

Definition thatDefinition that

Truth Table:Truth Table:

相异为相异为 11 ，相同为，相同为 00

Since, a(a’+b’)+b(a’+b’)=aa’+ab’+ba’+bb’=ab’+a’bSince, a(a’+b’)+b(a’+b’)=aa’+ab’+ba’+bb’=ab’+a’b

thusthus, ab’+a’b=a(a’+b’)+(a’+b’)b=, ab’+a’b=a(a’+b’)+(a’+b’)b=((a(a’+b’)a(a’+b’))()((a’+b’)b(a’+b’)b))

Use NAND to implement Exclusive-OR gatesUse NAND to implement Exclusive-OR gates

=(a=(a(ab)’(ab)’) ) (((ab)’(ab)’b)b)

a

b

b

aAll input, a and b, are All input, a and b, are uncomplemented.uncomplemented.

Some useful properties of the Exclusive-OR:Some useful properties of the Exclusive-OR:

(a⊕b)’ = (a’b+ab’)’=(a+b’)(a’+b)=a’b’+aba’b’+ab (XNOR: XNOR: 同或同或 )

(a’⊕b)=(a’)’b+(a’)b’=ab+a’b’=(a⊕b)’

(a⊕b’)=(a⊕b)’

a⊕0=a=(a’·0+a ·1)

a⊕1=a’=(a’·1+a ·0)

The Exclusive-OR has both The Exclusive-OR has both

the the commutativecommutative(( 交换律交换律 ) and ) and

associativeassociative(( 结合律结合律 ) properties) properties ：： aa⊕⊕b=bb=b⊕⊕a a

(a(a⊕⊕b)b)⊕⊕c= ac= a⊕⊕(b(b⊕⊕c)c)

Exclusive-OR (Exclusive-OR (XOR: XOR: 异或异或 ) gate) gate

ab+a’b’=(aab+a’b’=(a⊕⊕b)’b)’ =a =a b⊙ b⊙

a b f0 00 00 10 11 01 01 11 1

11000011

Truth Table:Truth Table:

相同为相同为 11 ，相异为，相异为 00

written as aa⊙⊙b=a’b’+abb=a’b’+ab=(a’b+ab’)’ (( 异或非异或非 ))

Properties:

(a⊙ b)’ = (a’b’+ab)’=(a+b)(a’+b’)

=ab’+a’b= a⊕b

(a’⊙b)=(a’)’b’+a’b=ab’+a’b=a b= (a⊕ ⊙ b)’

(a⊙b’)=(a⊙b)’= a⊕b

a⊙0=a’=(a·0+a’ ·1)

a⊙1=a =(a’·0+a ·1)

The commutative(The commutative( 交换律交换律 ) and associative() and associative( 结合律结合律 ) properties) properties ：： a⊙b=b⊙a

(a⊙b)⊙c= a⊙(b⊙c)

Additional:Additional: XNOR XNOR (( 同或逻辑同或逻辑 ))

Symbol asSymbol asab

a⊙ b

SUMMARYSUMMARY

1A F &A

BF 1

A

BF

A=A’A=A’ F=ABF=AB F=A+BF=A+B

SummarySummary

AB F& A

B F≥ 1≥ 1

FABCD

& AB F A

B F=1 =

F=(AB)’F=(AB)’ F=(A+B)’F=(A+B)’ F=(AB+CD)’F=(AB+CD)’ F=AB’+A’BF=AB’+A’B F=AB+A’B’F=AB+A’B’

AB F A

B F FABCD

AB FA

B F

A list of some of the more common NAND,NOR, and A list of some of the more common NAND,NOR, and Exclusive-OR integrated circuit packages that we may Exclusive-OR integrated circuit packages that we may encounter in the laboratory is as follows:encounter in the laboratory is as follows:

7400 4(quadruple) two-input NAND gates

7410 3(triple) three-input NAND gates

7420 2(dual) four-input NAND gates

7430 1 eight-input NAND gate

7402 4(quadruple) two-input NOR gates

7427 3 (triple) three-input NOR gates

7486 4 (quadruple) two-input Exclusive-OR gates

2.9 Simplification of Algebraic Expressions2.9 Simplification of Algebraic Expressions Some useful properties in simplifyingSome useful properties in simplifying

P6a a+a=a P6b a•a=a

P8a a(b+c)=ab+ac P8bP8b (a+bc)=(a+b)(a+c) (a+bc)=(a+b)(a+c)

P9a ab+ab’=a P9b (a+b)(a+b’)=a

P10aP10a a+a’b=a+b a+a’b=a+b P10b a(a’+b)=ab

P12aP12a a+ab=a a+ab=a P12b a(a+b)=aP13aP13a at at11+a’t+a’t22+t+t11tt22=at=at11+a’t+a’t22

P13b (a+t1)(a’+t2)(t1+t2)=(a+t1)(a’+t2)P13aa at1+a’t2+t1t2 t3t4…=at1+a’t2

P13bb (a+t1)(a’+t2)(t1+t2 +t2 +t2+…)=(a+t1)(a’+t2)

P75: P75: Consensus (Consensus ( 合意合意，， redundancy term: redundancy term: 冗余项冗余项 )) For any For any two product termstwo product terms where where exactlyexactly one variableone variable appear appears s uncomplemented in one and complemented in the otheruncomplemented in one and complemented in the other, the , the coconsensusnsensus is defined as the is defined as the product of the remaining literalsproduct of the remaining literals..

For example: atFor example: at11+a’t+a’t22=at=at11+a’t+a’t22++tt11tt22

The method of Simplification of Algebraic ExpressionsThe method of Simplification of Algebraic Expressions

一：并项法（一：并项法（ ab+ab’=a)ab+ab’=a)

Example1: Example1: f=ab’+acd+a’b’+a’cdf=ab’+acd+a’b’+a’cd

=a(b’+cd)+a’(b’+cd)=a(b’+cd)+a’(b’+cd)

=(b’+cd)(a+a’)=(b’+cd)(a+a’)

=b’+cd=b’+cd

Example2: Example2: f=a’bc’+ac’+b’cf=a’bc’+ac’+b’c’’

=a’bc’+(a+b’)c’=a’bc’+(a+b’)c’

=a’bc’+(a’b)’c’=a’bc’+(a’b)’c’

=c’=c’

Ex3: f = ab’c’+abc’+abc+ab’c = a(b’c’+bc)+a(bc’+b’c)

= a(b⊙c)+a(b⊕c) = a(b⊙c+b⊕c) =a

二：吸收法（二：吸收法（ a+ab)=aa+ab)=a

Ex1. f=ab+abc’+abd+ab(c’+d’)Ex1. f=ab+abc’+abd+ab(c’+d’)

=ab=ab

Ex2. f=a+(a’(bc)’)’[a’+(b’c’+d)’]+bcEx2. f=a+(a’(bc)’)’[a’+(b’c’+d)’]+bc

=a+(a+bc)[a’+(b’c’+d)’]+bc=a+(a+bc)[a’+(b’c’+d)’]+bc

=(a+bc)+ (a+bc)[a’+(b’c’+d)’]=(a+bc)+ (a+bc)[a’+(b’c’+d)’]

=a+bc=a+bc

三：合意法（消项法）三：合意法（消项法） ab+a’c+bc=ab+ac’ ab+a’c+bcd=ab+a’cab+a’c+bc=ab+ac’ ab+a’c+bcd=ab+a’c

Ex1. f=ac+ab’+(b+c)’Ex1. f=ac+ab’+(b+c)’

=ac+ab’+b’c’=ac+ab’+b’c’

=ac+b’c’=ac+b’c’

合意项为合意项为 ab’ab’

Ex2. f=ab’cd’+(ab’)’e+a’cd’eEx2. f=ab’cd’+(ab’)’e+a’cd’e

=(ab’)cd’+(ab’)’e+cd’ea’=(ab’)cd’+(ab’)’e+cd’ea’

=ab’cd’+(ab’)’e=ab’cd’+(ab’)’e

Ex3. f= a’b’c+abc+a’bd’+ab’d’+a’bcd’+bcd’e’Ex3. f= a’b’c+abc+a’bd’+ab’d’+a’bcd’+bcd’e’

=(a’b’+ab)c+(a’b+ab’)d’+bcd’(a’+e’)=(a’b’+ab)c+(a’b+ab’)d’+bcd’(a’+e’)

=(a=(a⊕b)’c+(a b)d’+bcd’(a’+e’)⊕ =(a=(a⊕b)’c+(a b)d’⊕

四消因子法：四消因子法： a+a’b=a+ba+a’b=a+b

Ex. f= b’+abcEx. f= b’+abc

= b’+ac= b’+ac

Ex. f= ab’+b+a’bEx. f= ab’+b+a’b

＝＝ a+b+a’ba+b+a’b

=a+b=a+b

Ex. f=ac+a’d+c’dEx. f=ac+a’d+c’d

=ac+(a’+c’)d=ac+(a’+c’)d

=ac+(ac)’d=ac+(ac)’d

=ac+d=ac+d

五配项法：五配项法： a+a=aa+a=a

Ex. f=a’bc’+a’bc+abcEx. f=a’bc’+a’bc+abc

=a’b(c+c’)+bc(a+a’)=a’b(c+c’)+bc(a+a’)

=a’b+bc =a’b+bc

加入加入 a’bca’bc

Ex1. f = wx+wxy+w’yz+w’y’z+w’xyz’

1110

11111

11101

100

10110100wxyz

Using Using KarnaughKarnaugh map to simplify map to simplify the algebraic expressionsthe algebraic expressions

Map the functionMap the function

f = f = wx++w’z+ + xyxywx w’z xyxy

f = ab’c’+abc’+abc+ab’c

01

1

1

11 1000

11

10

ABC

f = af = a

= a(b’c’+bc)+a(bc’+b’c) = a(b⊙c)+a(b⊕c) = a(b⊙c+b⊕c) =a

1

110

1111

1101

100

10110100wxyz

1

1

f = f = wx++w’z+ + xyxyy’z w’x wz

Ex. K-mapEx. K-map

2.10 Manipulation of algebraic functions 2.10 Manipulation of algebraic functions and NAND gate implementationsand NAND gate implementations

Several expression forms of algebraic function: SOP—Sum of productsSOP—Sum of products （与或式） Including Sum of Minterms （最小项之和式） POS—Product of sumsPOS—Product of sums （或与式） Including Product of Maxterms （最大项之积式） NAND formNAND form （与非与非式） NOR formNOR form （或非或非式） AND-OR-NOT formAND-OR-NOT form （与或非式）

Ex. f = ab+a’c [SOP]ab+a’c [SOP]

= (a’+b)(a+c) [POS]

= (ab)(a’c) [ 与非与非式 ]

= (a’+b)+(a+c) [ 或非或非式 ]

= ab’+a’c’ [ 与或非式 ]

How to put an expression in a certain format?How to put an expression in a certain format? Two method of putting an expression in sum of minter

ms or in product of maxterms:

(a) from truth table to produce a sum of minterms or product of maxterms;

(b) Use P9a and P9b to add variables to a term.

P9a P9a ab+ab’=a ab+ab’=a P9b P9b (a+b)(a+b’)=a(a+b)(a+b’)=a

ex2.26 f = bc+ac+ab

f = bca+bca’+acb+acb’+abc+abc’

= abc+a’bc+ab’c+abc’

ex2.27 g = x’+xyz

= x’y+x’y’+xyz

= x’yz’+xyz+x’y’z’+x’y’z+xyz

ex2.28 f = (a+b+c)(a’+b’)

= (a+b+c)(a’+b’+c’)(a’+b’+c)

P14aP14a ab+a’c=(a+c)(a’+b) ab+a’c=(a+c)(a’+b)

Put a POS in SOP:

ex2.29 f = (a+b+c)(a’+b’)

= ab’+a’(b+c)

= ab’+a’b+a’c

P9a P9a ab+ab’=a ab+ab’=a P9b P9b (a+b)(a+b’)=a(a+b)(a+b’)=a

Ex2.31 f = (a+b’+c)(a+b+d)(a’+c’+d’)

= (a+(b’+c)(b+d))(a’+c’+d’) [P8b]

= (a+b’d+bc)(a’+c’+d’) [P14a]

= a(c’+d’)+a’(b’d+bc)

= ac’+ad’+a’b’d+a’bc

SummarizeSummarizeEx. f = ab+a’c [SOP]ab+a’c [SOP]

= (a’+b)(a+c) [POS]

= (ab)(a’c) [ 与非与非式 ]

= (a’+b)+(a+c) [ 或非或非式 ]

= ab’+a’c’ [ 与或非式 ]

SOPSOP POSPOS

NANDNAND Form Form与非与非式与非与非式

NORNOR Form Form或非或非式或非或非式

AND-OR-NOTAND-OR-NOT Form Form与或非式与或非式

Truth Table orTruth Table orKarnaughKarnaugh Map Map

ab+a’c=(a+c)(a’+b)ab+a’c=(a+c)(a’+b) =ab+a’c+=ab+a’c+bcbc

2.11 A More General Boolean Algebra2.11 A More General Boolean Algebra The basis for switching algebra is Boolean algebra, it works fo

r a two-valued system. There are two binary operators ( 二元操作符 ), +(OR)+(OR) and •(AN•(AN

D)D), and one unary operator(一元操作符 ), ’(NOT)’(NOT). The algebra is closed, that is, if a and b are members of the set,

then a+b, a•b, a’ are also members of the set.

a+b = b+a, a •b = b •a （交换律） a+(b+c)=(a+b)+c a•(b •c)=(a •b) •c （结合律） a+b •c=(a+b) •(a+c) a •(b+c)=a •b+a •c （分配律） a+0=a a •1=a （恒等律） a+a’=1 a •a’=0 （互补） a+a=a a •a=a (幂等性 )

chapter 2 switching algebra and logic circuits. switching algebra ( 开关代数 ) boolean algebra (...

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