chapter #2: two-level combinational logic
DESCRIPTION
Chapter #2: Two-Level Combinational Logic. Motivation. Further Amplification on the Concepts of Chapter #1:. • Multiple Design Representations Truth Tables Static gate descriptions Dynamic waveform descriptions • Rapid prototyping technology - PowerPoint PPT PresentationTRANSCRIPT
2-1
Introduction
Chapter #2: Two-Level Combinational Logic
2-2
IntroductionMotivation
• Multiple Design Representations
Truth Tables
Static gate descriptions
Dynamic waveform descriptions
• Rapid prototyping technology
Use of computer aided design tools: espresso
• Design Techniques that Spanning Multiple Technologies
Transistor-Transistor Logic (TTL)
Complementary Metal on Oxide Silicon (CMOS)
Further Amplification on the Concepts of Chapter #1:
2-3
IntroductionChapter Overview
• Logic Functions and Switches
Not, AND, OR, NAND, NOR, XOR, XNOR
• Gate Logic
Laws and Theorems of Boolean Algebra
Two Level Canonical Forms
Incompletely Specified Functions
• Two Level Simplification
Boolean Cubes
Karnaugh Maps
Quine-McClusky Method
Espresso Methos
2-4
IntroductionLogic Functions: Boolean Algebra
Algebraic structure consisting of:
set of elements B
binary operations {+, -}
unary operation {'}
such that the following axioms hold:
1. B contains at least two elements, a, b, such that a = b
2. Closure a,b in B, (i) a + b in B (ii) a • b in B
3. Commutative Laws: a,b in B, (i) a + b = b + a (ii) a • b = b • a
4. Identities: 0, 1 in B (i) a + 0 = a (ii) a • 1 = a
5. Distributive Laws: (i) a + (b • c) = (a + b) • (a + c) (ii) a • (b + c) = a • b + a • c
6. Complement: (i) a + a' = 1 (ii) a • a' = 0
2-5
IntroductionLogic Functions: Boolean AlgebraB = {0,1}, + = OR, • = AND, ' = NOT is a Boolean Algebra
must verify that the axioms hold:E.g., Commutative Law:
0 + 1 = 1 + 0?1 = 1
0 • 1 = 1 • 0?0 = 0
Theorem: any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using ', +, •
Reviewfrom
Chapter 1
NOT
Description Z = 1 if X and Y are both 1
Gates Truth Table Switches
XY
ZY 0 1 0 1
X 0 0 1 1
Z 0 0 0 1
X • Y
false
true
OR
Description If X = 0 then X ' = 1 If X = 1 then X ' = 0
Switches Gates
X
X X 0 1
X 1 0
T ruth T able
X T rue
False X
Description Z = 1 if X or Y (or both) are 1
Gates T ruth T able Switches X Y Z X
0 0 1 1
Y 0 1 0 1
Z 0 1 1 1
X Y
X + Y
False
T rue
AND
2-6
IntroductionLogic Functions: From Expressions to GatesMore than one way to map an expression to gates
E.g., Z = A' • B' • (C + D) = (A' • (B' • (C + D)))
T1
T2
Literal: each appearance of a variable or its complement in an expression
E.g., Z = A B' C + A' B + A' B C' + B' C
use of 3-input gate
3 variables, 10 literals
A
B
C
D T
2
T 1
Z
Z
A
B
C
D
2-7
IntroductionLogic Functions: NAND, NOR, XOR, XNOR16 functions of two variables:
X, X', Y, Y', X • Y, X+Y, 0, 1 only half of the possible functions
NOR
0 X • Y X Y X + Y X Y
1
F15 1 1 1 1
F0 0 0 0 0
F1 0 0 0 1
F2 0 0 1 0
F3 0 0 1 1
F4 0 1 0 0
F5 0 1 0 1
F6 0 1 1 0
F7 0 1 1 1
F8 1 0 0 0
F9 1 0 0 1
F10 1 0 1 0
F1 1 1 0 1 1
F12 1 1 0 0
F13 1 1 0 1
F14 1 1 1 0
X 0 0 1 1
Y 0 1 0 1
NANDDescription Z = 1 if X is 0 or Y is 0
Gates T ruth T able
X 0 0 1 1
Y 0 1 0 1
Z 1 1 1 0
X Y
Z
Description Z = 1 if both X and Y are 0
Gates T ruth T able Switches X
Y Z X
0 0 1 1
Y 0 1 0 1
Z 1 0 0 0
X Y
X + Y False
T rue
Switches
X Y
False
T rue
X • Y
2-8
IntroductionLogic Functions: NAND, NOR Implementation
NAND, NOR gates far outnumber AND, OR in typical designs
easier to construct in the underlying transistor technologies
Any Boolean expression can be implemented by NAND, NOR, NOT gates
In fact, NOT is superfluous (NOT = NAND or NOR with both inputs tied together)
X0
1
Y0
1
X NOR Y1
0
X0
1
Y0
1
X NAND Y1
0
2-9
IntroductionLogic Functions: XOR, XNORXOR: X or Y but not both ("inequality", "difference")XNOR: X and Y are the same ("equality", "coincidence")
X Y = X Y' + X' Y X Y = X Y + X' Y'
(a) XOR (b) XNOR
Description Z = 1 if X has a different value than Y
Gates
T ruth T able
X
Y Z
X 0 0 1 1
Y 0 1 0 1
Z 0 1 1 0
Description Z = 1 if X has the same value as Y
Gates
T ruth T able
X
Y Z
X 0 0 1 1
Y 0 1 0 1
Z 1 0 0 1
2-10
IntroductionLogic Functions: Waveform View
2-11
IntroductionLogic Functions: Rationale for SimplificationLogic Minimization: reduce complexity of the gate level implementation
• reduce number of literals (gate inputs)
• reduce number of gates
• reduce number of levels of gates
fewer inputs implies faster gates in some technologies
fan-ins (number of gate inputs) are limited in some technologies
fewer levels of gates implies reduced signal propagation delays
minimum delay configuration typically requires more gates
number of gates (or gate packages) influences manufacturing costs
Traditional methods: reduce delay at expense of adding gates
New methods: trade off between increased circuit delay and reduced gate count
Traditional methods: reduce delay at expense of adding gates
New methods: trade off between increased circuit delay and reduced gate count
2-12
IntroductionLogic Functions: Alternative Gate Realizations
Two-Level Realization(inverters don't count)
Multi-Level RealizationAdvantage: Reduced Gate
Fan-ins
Complex Gate: XORAdvantage: Fewest Gates
TTL Package Counts: Z1 - three packages (1x 6-inverters, 1x 3-input AND, 1x 3-input OR) Z2 - three packages (1x 6-inverters, 1x 2-input AND, 1x 2-input OR) Z3 - two packages (1x 2-input AND, 1x 2-input XOR)
0 1 0 1 0 1
A B C
0
0
Z 1
Z 2
Z 3
0
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Z 0 1 0 1 0 1 1 0
2-13
IntroductionLogic Functions: Waveform Verification
Under the same input stimuli, the three alternative implementations have essentially the same waveform behavior.
Slight variations due to differences in number of gate levels
The three implementations are equivalent
2-14
IntroductionGate Logic: Laws of Boolean AlgebraDuality: a dual of a Boolean expression is derived by replacing AND operations by ORs, OR operations by ANDs, constant 0s by 1s, and 1s by 0s (literals are left unchanged).
Any statement that is true for an expression is also true for its dual!
Useful Laws/Theorems of Boolean Algebra:
Operations with 0 and 1:
Idempotent Law:
Involution Law:
Laws of Complementarity:
Commutative Law:
1. X + 0 = X2. X + 1 = 1
1D. X • 1 = X2D. X • 0 = 0
3. X + X = X 3D. X • X = X
4. (X')' = X
5. X + X' = 1 5D. X • X' = 0
6. X + Y = Y + X 6D. X • Y = Y • X
2-15
IntroductionGate Logic: Laws of Boolean Algebra (cont)
Distributive Laws:
Simplification Theorems:
DeMorgan's Law:
Duality:
Theorems for Multiplying and Factoring:
Consensus Theorem:
8. X • (Y+ Z) = (X • Y) + (X • Z) 8D. X + (Y • Z) = (X + Y) • (X + Z)
9. X •Y + X • Y' = X10. X + X • Y = X11. (X + Y') • Y = X • Y
9D. (X + Y) • (X + Y') = X10D. X • (X + Y) = X11D. (X • Y') + Y = X + Y
12. (X + Y + Z + ...)' = X' • Y' • Z' • ...13. {F(X1,X2,...,Xn,0,1,+,•)}' = {F(X1',X2',...,Xn',1,0,•,+)}
12D. (X • Y • Z • ...)' = X' + Y' + Z' + ...
14. (X + Y + Z + ...) = X • Y • Z • ...
15. {F(X1,X2,...,Xn,0,1,+,•)} = {F(X1,X2,...,Xn,1,0,•,+)}
D
D
14D. (X • Y • Z • ...) = X + Y + Z + ...D
16. XZ + X'Y + YZ =XZ+X’Y 16D. X • Y + X' • Z = (X + Z) • (X' + Y)
17. (X • Y) + (Y • Z) + (X' • Z) = X • Y + X' • Z
17D. (X + Y) • (Y + Z) • (X' + Z) = (X + Y) • (X' + Z)
Associative Laws:7. (X + Y) + Z = X + (Y + Z) = X + Y + Z
7D. (X • Y) • Z = X • (Y • Z) = X • Y • Z
2-16
IntroductionGate Logic: Laws of Boolean AlgebraProving theorems via axioms of Boolean Algebra:
E.g., prove the theorem: X • Y + X • Y' = X
E.g., prove the theorem: X + X • Y = X
2-17
IntroductionGate Logic: Laws of Boolean AlgebraProving theorems via axioms of Boolean Algebra:
E.g., prove the theorem: X • Y + X • Y' = X
X • Y + X • Y' = X • (Y + Y')
X • (Y + Y') = X • (1)
X • (1) = X
distributive law (8)
complementary law (5)
identity (1D)
E.g., prove the theorem: X + X • Y = X
X + X • Y = X • 1 + X • Y
X • 1 + X • Y = X • (1 + Y)
X • (1 + Y) = X • (1)
X • (1) = X
identity (1D)
distributive law (8)
identity (2)
identity (1)
2-18
IntroductionGate Logic: Laws of Boolean Algebra
E.g., prove the theorem: (X + Z) • (X' + Y) = X • Z + X' • Y
(X + Z) • (X' + Y)
= XZ + X'Y + YZ
= XZ + X'Y + YZX + YZX'
= XZ(Y+1) + X'Y(Z+1)
= X • Z + X' • Y
2-19
IntroductionGate Logic: Laws of Boolean Algebra
DeMorgan's Law
(X + Y)' = X' • Y'
(X • Y)' = X' + Y'
NOR is equivalent to ANDwith inputs complemented
NAND is equivalent to ORwith inputs complemented
Example:Z = A' B' C + A' B C + A B' C + A B C'
Z' = (A + B + C') • (A + B' + C') • (A' + B + C') • (A' + B' + C)
DeMorgan's Law can be used to convert AND/OR expressionsto OR/AND expressions
DeMorgan's Law can be used to convert AND/OR expressionsto OR/AND expressions
X 0 0 1 1
Y 0 1 0 1
X 1 1 0 0
Y 1 0 1 0
X + Y 1 0 0 0
X•Y 1 0 0 0
X 0 0 1 1
Y 0 1 0 1
X 1 1 0 0
Y 1 0 1 0
X + Y 1 1 1 0
X•Y 1 1 1 0
2-20
IntroductionGate Logic: Laws of Boolean AlgebraApply the laws and theorems to simplify Boolean equations
Example: full adder's carry out function
Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin
2-21
IntroductionGate Logic: Laws of Boolean AlgebraApply the laws and theorems to simplify Boolean equations
Example: full adder's carry out function
Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin
= A' B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin
= A' B Cin + A B Cin + A B' Cin + A B Cin' + A B Cin
= (A' + A) B Cin + A B' Cin + A B Cin' + A B Cin
= (1) B Cin + A B' Cin + A B Cin' + A B Cin
= B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin
= B Cin + A B' Cin + A B Cin + A B Cin' + A B Cin
= B Cin + A (B' + B) Cin + A B Cin' + A B Cin
= B Cin + A (1) Cin + A B Cin' + A B Cin
= B Cin + A Cin + A B (Cin' + Cin)
= B Cin + A Cin + A B (1)
= B Cin + A Cin + A B
identity
associative
2-22
Introduction
A + 0 = A A + 1 = 1
A A
0
=
A 1
=
1
Gate Logic: Switching Equivalents
Idempotent Laws Identity Laws
Complementarity Laws Simplification Theorems
A • A = A
A A
A
A
A
A + A = A
= =
A
A + A = 1 A • A = 0
A
A
=
1
A A
=
0
X Y + X Y = X X + X Y = X
X Y
X Y
X Y
X
= =
X X
2-23
IntroductionGate Logic: 2-Level Canonical FormsTruth table is the unique signature of a Boolean function
Many alternative expressions (and gate realizations) may have the same truth table
Canonical form: standard form for a Boolean expression provides a unique algebraic signature
Sum of Products Formalso known as disjunctive normal form, minterm expansion
F = A' B C + A B' C' + A B' C + A B C' + A B C0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
F' = A' B' C' + A' B' C + A' B C'
F 0 0 0 1 1 1 1 1
F 1 1 1 0 0 0 0 0
C 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 1 1
A 0 0 0 0 1 1 1 1
2-24
IntroductionGate Logic: Two Level Canonical Forms
Sum of Products
Shorthand Notation forMinterms of 3 Variables
product term / minterm:
ANDed product of literals in which eachvariable appears exactly once, in true orcomplemented form (but not both!)
F in canonical form:
F(A,B,C) = m(3,4,5,6,7)= m3 + m4 + m5 + m6 + m7= A' B C + A B' C' + A B' C + A B C' + A B C
canonical form/minimal form
F = A B' (C + C') + A' B C + A B (C' + C)
= A B' + A' B C + A B
= A (B' + B) + A' B C
= A + A' B C
= A + B C2-Level AND/OR
Realization F = (A + B C)' = A' (B' + C') = A' B' + A' C'
B
C
A
F
A B C = m 1 A B C = m 2 A B C = m 3 A B C = m 4 A B C = m 5 A B C = m 6 A B C = m 7
A
0 0 0 0 1 1 1 1
B
0 0 1 1 0 0 1 1
C
0 1 0 1 0 1 0 1
Minterms
A B C = m 0
2-25
IntroductionGate Logic: 2 Level Canonical FormsProduct of Sums / Conjunctive Normal Form / Maxterm Expansion
Maxterm Shorthand Notationfor a Function of Three Variables
Maxterm:ORed sum of literals in which eachvariable appears exactly once in eithertrue or complemented form, but not both!
Maxterm form:Find truth table rows where F is 00 in input column implies true literal1 in input column implies complemented literal
F(A,B,C) = M(0,1,2)
= (A + B + C) (A + B + C') (A + B' + C)
F(A,B,C) = M(3,4,5,6,7)
= (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Maxterms A + B + C = M 0 A + B + C = M 1 A + B + C = M 2 A + B + C = M 3 A + B + C = M 4 A + B + C = M 5 A + B + C = M 6 A + B + C = M 7
2-26
IntroductionGate Logic: Two Level Canonical FormsSum of Products, Products of Sums, and DeMorgan's Law
F' = A' B' C' + A' B' C + A' B C'
Apply DeMorgan's Law to obtain F:
(F')' = (A' B' C' + A' B' C + A' B C')'
F = (A + B + C) (A + B + C') (A + B' + C)
F' = (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')
(F')' = {(A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')}'
F = A' B C + A B' C' + A B' C + A B C' + A B C
Apply DeMorgan's Law to obtain F:
2-27
IntroductionGate Logic: Two-Level Canonical FormsFour Alternative Implementations of F:
Canonical Sum of Products
Minimized Sum of Products
Canonical Products of Sums
Minimized Products of Sums
A
B
F 2
F 3
F 4
F 1 C
2-28
IntroductionGate Logic: Two-Level Canonical FormsWaveform Verification of the Three Alternatives
Eight Unique Combinationsof Three Inputs
Except for timing glitches,output waveforms of the
three implementations areessentially identical
100 200
A
B
C
F 1
F 2
F 3
2-29
IntroductionGate Logic: Two-Level Canonical FormsMapping Between Forms
1. Minterm to Maxterm conversion: rewrite minterm shorthand using maxterm shorthand replace minterm indices with the indices not already used
E.g., F(A,B,C) = m(3,4,5,6,7) = M(0,1,2)
2. Maxterm to Minterm conversion:rewrite maxterm shorthand using minterm shorthandreplace maxterm indices with the indices not already used
E.g., F(A,B,C) = M(0,1,2) = m(3,4,5,6,7)
3. Minterm expansion of F to Minterm expansion of F':in minterm shorthand form, list the indices not already used in F
E.g., F(A,B,C) = m(3,4,5,6,7) F'(A,B,C) = m(0,1,2) = M(0,1,2) = M(3,4,5,6,7)
4. Minterm expansion of F to Maxterm expansion of F':rewrite in Maxterm form, using the same indices as F
E.g., F(A,B,C) = m(3,4,5,6,7) F'(A,B,C) = M(3,4,5,6,7) = M(0,1,2) = m(0,1,2)
2-30
IntroductionGate Logic: Positive vs. Negative LogicNormal Convention: Postive Logic/Active High
Low Voltage = 0; High Voltage = 1
Alternative Convention sometimes used: Negative Logic/Active Low
Behavior in termsof Electrical Levels
Two Alternative InterpretationsPositive Logic ANDNegative Logic OR
Dual Operations
Negative Logic Positive Logic V oltage T ruth T able
F low low low high
F 0 0 0 1
F 1 1 1 0
A low low high high
B low high low high
B 0 1 0 1
A 0 0 1 1
A 1 1 0 0
B 1 0 1 0
F
2-31
IntroductionGate Logic: Positive vs. Negative LogicConversion from Positive to Negative Logic
Positive Logic NOR: A + B = A • B
Negative Logic NAND: A • B = A + B
Dual operations: AND becomes OR, OR becomes AND Complements remain unchanged
V oltage T ruth T able
F high low low low
F 1 0 0 0
F 0 1 1 1
A low low high high
B low high low high
B 0 1 0 1
A 0 0 1 1
A 1 1 0 0
B 1 0 1 0
F
Negative Logic Positive Logic
2-32
Introduction
(c)
Change Request
(active low)
T imer Expired
(active low)
Change Lights
(active low)
Bubble Mismatch
(d)
(a)
Change Request
(active high)
T imer Expired
(active high)
Change Lights
(active high)
Active High
(b)
Change Request
(active low)
T imer Expired
(active low)
Change Lights
(active low)
Active Low
Change Request
(active low)
T imer Expired
(active low)
Change Lights
(active low)
Bubble Match
Gate Logic: Positive vs. Negative LogicPractical Example
Mismatch betweeninput and outputlogic polarities
Use NAND w/ invertedinputs if negative logic
Use OR gate if inputpolarities are neg. logic
Use AND gateif active high
2-33
Introduction
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
W 0 0 0 0 0 0 0 1 1 0 X X X X X X
X 0 0 0 1 1 1 1 0 0 0 X X X X X X
Y 0 1 1 0 0 1 1 0 0 0 X X X X X X
Z 1 0 1 0 1 0 1 0 1 0 X X X X X X
Gate Logic: Incompletely Specified Functionsn input functions have 2 possible input configurations
for a given function, not all input configurations may be possible
this fact can be exploited during circuit minimization!
E.g., Binary Coded Decimal Digit Increment by 1BCD digits encode the decimal digits 0 - 9 in the bit patterns 0000 - 1001
n
2 2
These input patterns shouldnever be encountered in practise
associated output values are"Don't Cares"
Off-set of W
On-set of W
Don't care (DC) set of W
2-34
IntroductionGate Logic: Incompletely Specified FunctionsDon't Cares and Canonical Forms
Z = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 + d15
Z = m(0, 2, 4, 6, 8) + d(10, 11, 12 ,13, 14, 15)
Z = M1 • M3 • M5 • M7 • M9 • D10 • D11 • D12 • D13 • D14 • D15
Z= M(1, 3, 5, 7, 9) • D(10, 11, 12, 13, 14 ,15)
On set : contains all input combinations for which the function is 1
Off set : contains all input combinations for which the function is 0
Don’t care set : contains all input combinations for which the function is X
Canonical Representations of the BCD Increment by 1 Function:
2-35
IntroductionGate Logic: Two-Level SimplificationAlgebraic Simplification:
not an algorithm/systematic procedure
how do you know when the minimum realization has been found?
Computer-Aided Tools:
precise solutions require very long computation times, especially for functions with many inputs (>10)
heuristic methods employed "educated guesses" to reduce the amount of computation good solutions not best solutions
Still Relevant to Learn Hand Methods:
insights into how the CAD programs work, and their strengths and weaknesses
ability to check the results, at least on small examples
don't have computer terminals during exams
2-36
Introduction
A 0 0 1 1
B 0 1 0 1
G 1 0 1 0
A 0 0 1 1
B 0 1 0 1
F 0 0 1 1
Gate Logic: Two-Level Simplification
Key Tool: The Uniting Theorem A (B' + B) = AKey Tool: The Uniting Theorem A (B' + B) = A
F = A B' + A B = A (B' + B) = A
A's values don't change within the on-set rows
B's values change within the on-set rows
G = A' B' + A B' = (A' + A) B' = B'
B's values stay the same within the on-set rows
A's values change within the on-set rows
B is eliminated, A remains
A is eliminated, B remains
Essence of Simplification:find two element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!
2-37
IntroductionGate Logic: Two-Level SimplificationBoolean Cubes
Visual technique for identifying when the Uniting Theorem can be applied
Just another way torepresent the truth table
n input variables =n dimensional "cube"
2-cube 3-cube
4-cube
XYZ
X
011
010
000
001
111
110
100
101 Y Z
WXYZ
0111 0011
0010
0000
0001
0110
1010
0101
0100 1000
1011
1001
1110
1111
1101
1100
Y Z
W
X
XY
1-cube
X
X
01
00
11
10
Y
0 1
2-38
IntroductionGate Logic: Two-Level Simplification
Mapping Truth Tables onto Boolean Cubes
ON-set = filled-in nodes
OFF-set = empty nodes
DC-set = X'd nodes
F
G
A asserted and unchanged
B varies within loop
A varies within loop
B complemented and unchanged
Cube of n-1 dimensions
Reduced expression contains n-1 variables
01 11
10 00
B
A
01 11
10 00
A
B
adjacency plane
2-39
Introduction
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
A
B
Cin 0 1 0 1 0 1 0 1
Cout 0 0 0 1 0 1 1 1
011 111
010 110
001
000 100
101 Cin
Gate Logic: Two-Level SimplificationThree variable example: Full Adder Carry Out
(A' + A) B Cin
A B (Cin' + Cin)
A (B + B') Cin
Cout = B Cin + A B + A Cin
The ON-set is coveredby the OR of the subcubes
of lower dimensionality
2-40
Introduction
011 111
101
100
110 010
001
000
B
C
A
Gate Logic: Two-Level Simplification
Subcubes of Higher Dimensions than 2
F(A,B,C) = m(4,5,6,7)
On-set forms a rectangle, i.e., a cube of two dimensions
represents an expression in one variable i.e., 3 dimensions - 2 dimensions
A is asserted and unchangedB and C vary
This subcube represents theliteral A
2-41
IntroductionGate Logic: Two-Level SimplificationIn a 3-cube:
a 0-cube, i.e., a single node, yields a term in three literals
a 1-cube, i.e., a line of two nodes, yields a term in two literals
a 2-cube, i.e., a plane of four nodes, yields a term in one literal
a 3-cube, i.e., a cube of eight nodes, yields a constant term "1"
In general,
an m-subcube within an n-cube (m < n) yields a term with n - m literals
2-42
Introduction
A B 0 1
0
1
0
1
2
3
0
1
2
3
6
7
4
5
AB C
0
1
3
2
4
5
7
6
12
13
15
14
8
9
11
10
A
B
AB
CD
A
00 01 11 10
0
1
00 01 11 00
00
01
11
10 C
B
D
Gate Logic: Two-Level SimplificationKarnaugh Map Method
hard to draw cubes of more than 4 dimensions
K-map is an alternative method of representing the truth table that helps visualize adjacencies in up to 6 dimensions
Beyond that, computer-based methods are needed
2-variableK-map
3-variableK-map
4-variableK-map
Numbering Scheme: 00, 01, 11, 10Gray Code : only a single bit changes from code word to next code word
2-43
IntroductionGate Logic: Two-Level SimplificationKarnaugh Map Method
Adjacencies in the K-Map
Wrap from first to last column
Top row to bottom row
000
001
010
01 1
1 10
1 1 1
100
101
00 01 11 10
0
1
AB C
A
B
011
010
000
001
100
110
101
111
B
C
A
2-44
IntroductionGate Logic: Two-Level SimplificationK-Map Method Examples
F =
A asserted, unchangedB varies
G =
B complemented, unchangedA varies
Cout = F(A,B,C) =
A
B 0 1
0 1
0 1
0
1
A
B 0 1
1 1
0 0
0
1
A B A
B
Cin 00 01 11 10
0
1
0
0
0
1
1
1
0
1
AB C
A
00 01 11 10
0
1
0
0
0
0
1
1
1
1
B
2-45
IntroductionGate Logic: Two-Level SimplificationK-Map Method Examples
F = A
A asserted, unchangedB varies
G = B'
B complemented, unchangedA varies
Cout = A B + B Cin + A Cin F(A,B,C) = A
A
B 0 1
0 1
0 1
0
1
A
B 0 1
1 1
0 0
0
1
A B A
B
Cin 00 01 11 10
0
1
0
0
0
1
1
1
0
1
AB C
A
00 01 11 10
0
1
0
0
0
0
1
1
1
1
B
2-46
IntroductionGate Logic: Two-Level Simplification
More K-Map Method Examples, 3 Variables
F(A,B,C) = m(0,4,5,7)
F =
F'(A,B,C) = m(1,2,3,6)
F' =
F' simply replace 1's with 0's and vice versa
00 C
AB 01 11 10
1 0 0 1
1 1 0 0
A
B
0
1
00 C
AB
01 11 10
0 1 1 0
0 0 1 1
A
B
0
1
2-47
IntroductionGate Logic: Two-Level Simplification
More K-Map Method Examples, 3 Variables
F(A,B,C) = m(0,4,5,7)
F = B' C' + A C
In the K-map, adjacency wraps from left to rightand from top to bottom
F'(A,B,C) = m(1,2,3,6)
F' = B C' + A' C
Compare with the method of using DeMorgan's Theorem and Boolean Algebra to reduce the complement!
F' simply replace 1's with 0's and vice versa
00 C
AB 01 11 10
1 0 0 1
1 1 0 0
A
B
0
1
00 C
AB
01 11 10
0 1 1 0
0 0 1 1
A
B
0
1
2-48
IntroductionGate Logic: Two-Level Simplification
K-map Method Examples: 4 variables
F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15)
F =
AB 00 01 11 10
1 0 0 1
0 1 0 0
1 1 1 1
1 1 1 1
00
01
11
10 C
CD
A
D
B
2-49
IntroductionGate Logic: Two-Level Simplification
K-map Method Examples: 4 variables
F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15)
F = C + A' B D + B' D'
K-map Corner AdjacencyIllustrated in the 4-Cube
Find the smallest numberof the largest possible
subcubes that cover theON-set
AB 00 01 11 10
1 0 0 1
0 1 0 0
1 1 1 1
1 1 1 1
00
01
11
10 C
CD
A
D
B
0011
D
0010
0000
0111
0110
0001 C
A
B 0100 1000
1100
1101
1111
1110
1001
1011
1010
0101
2-50
IntroductionGate Logic: Two-Level Simplification
K-map Method: Circling Zeros
AB 00 01 11 10
1 0 0 1
0 1 0 0
1 1 1 1
1 1 1 1
00
01
11
10 C
CD
A
D
B
F = (B + C + D) (A + C + D) (B + C + D)
F = B C D + A C D + B C D
F = B C D + A C D + B C D
F = (B + C + D) (A + C + D) (B + C + D)
Replace F by F, 0 become 1 and vice versa
2-51
IntroductionGate Logic: Two-Level Simplification
K-map Example: Don't Cares
F(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)
F = w/o don't cares
F = w/ don't cares
Don't Cares can be treated as 1's or 0's if it is advantageous to do soDon't Cares can be treated as 1's or 0's if it is advantageous to do so
AB 00 01 11 10
0 0 X 0
1 1 X 1
1 1 0 0
0 X 0 0
00
01
11
10 C
CD
A
D
B
2-52
IntroductionGate Logic: Two-Level Simplification
K-map Example: Don't Cares
F(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)
F = A'D + B' C' D w/o don't cares
F = C' D + A' D w/ don't cares
Don't Cares can be treated as 1's or 0's if it is advantageous to do soDon't Cares can be treated as 1's or 0's if it is advantageous to do so
By treating this DC as a "1", a 2-cubecan be formed rather than one 0-cube
AB 00 01 11 10
0 0 X 0
1 1 X 1
1 1 0 0
0 X 0 0
00
01
11
10 C
CD
A
D
B AB
00 01 11 10
0 0 X 0
1 1 X 1
1 1 0 0
0 X 0 0
00
01
11
10 C
CD
A
D
B
In PoS form: F = D (A' + C')
Same answer as above, but fewer literals