chapter 3 gate-level minimization 授課教師 : 張傳育博士 (chuan-yu chang ph.d.) e-mail:...

Chapter 3

Gate-Level Minimization

授課教師 : 張傳育博士 (Chuan-Yu Chang Ph.D.)E-mail: [email protected]: (05)5342601 ext. 4337Office: EB212

3-2Digital Circuits

3-1 Introduction

Gate-level minimization refers to the design task of finding an optimal gate-level implementation of Boolean functions describing a digital circuit.

3-3Digital Circuits

3-2 The Map Method

The complexity of the digital logic gates the complexity of the algebraic expression

Logic minimization algebraic approaches: lack specific rules the Karnaugh map

a simple straight forward procedure a pictorial form of a truth table applicable if the # of variables < 7

A diagram made up of squares each square represents one minterm

3-4Digital Circuits

3-2 The Map Method (cont.)

Boolean function sum of minterms sum of products (or product of sum) in the simplest

form The simplest algebraic expression is an algebraic

expression with a minimum number of terms a minimum number of literals

The expression produces a circuit diagram with A minimum number of gates and the minimum number of

inputs to each gates The simplified expression may not be unique

3-5Digital Circuits

Two-Variable Map

A two-variable map four minterms x' = row 0; x = row 1 y' = column 0;

y = column 1 a truth table in square

diagram xy x+y =

Fig. 3.2 Representation of functions in the map

3-6Digital Circuits

A three-variable map Eight minterms The Gray-code-like sequence Any two adjacent squares in the map differ by only

one variable primed in one square and unprimed in the other e.g., m5 and m7 can be simplified

m5+ m7 = xy'z + xyz = xz (y'+y) = xz

3-7Digital Circuits

A three-variable map (cont.)

Example 3-1 F(x,y,z) = (2,3,4,5) F = x'y + xy'

3-8Digital Circuits


m0 and m2 (m4 and m6) are adjacent

m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'

m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'

3-9Digital Circuits


Example 3-2 F(x,y,z) = (3,4,6,7) = yz+ xz'

3-10Digital Circuits

Four adjacent squares 2, 4, 8 and 16 squares m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz'

= x'z'(y'+y) +xz'(y'+y)= x'z' + xz‘ = z'

m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz=x'z(y'+y) + xz(y'+y)

=x'z + xz = z


Example 3-3 F(x,y,z) = (0,2,4,5,6) F = z'+ xy'


Example 3-4 F = A'C + A'B + AB'C + BC express it in sum of minterms find the minimal sum of products expression


3-3 Four-Variable Map The map

16 minterms combinations of 2, 4, 8, and 16 adjacent squares


Example 3-5 F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14)

F = y'+w'z'+xz'


Example 3-6Simplify the Boolean function

F = ABC + BCD + ABCD + ABC


卡諾圖化簡的規則輸入端有 N 個變數時，則繪出 2N個空格與其對應。將真值表內輸入所對應的輸出依次填入空格內。如果為布林代數式時：

當布林代數式為 SOP 型時，將 1 填入對應的方格內，其餘的部分則填 0 。

當布林代數式為 POS 型時，將 0 填入對應的方格內，其餘的部分則填 1 。

若沒有明確的輸出則填入 × 或 (don’t care) 。圈選的相鄰項越大越好，其中，相鄰項的個數須符合 2n。

n=0 ， 20=1 ，當圈一格時無法消去任何變數。 n=1 ， 21=2 ，當圈二格時可以消去 1 個變數。 n=2 ， 22=4 ，當圈四格時可以消去 2 個變數。 n=3 ， 23=8 ，當圈八格時可以消去 3 個變數。 n=4 ， 24=16 ，當圈十六格時可以消去 4 個變數。

圈在一起的 0 或 1 必須滿足相鄰間僅有一個位元不同。用最少的圈圈，把所有 1 的項圈起來。圈過還可再圈。


Prime Implicants

意含項 (implicant) ：任一個乘積項即為該函數的一個意含項 (implicant) ，

i.e ，在卡諾圖內，由含有“ 1” 之方格所組合的所有矩形均是 implicant 。

質含項 (prime implicant) ：某一 implicant 不再為另一個 implicant 的子集

(subset) 此種 implicant 稱為 prime implicant 。必要項 (essential prime implicant) ：

若函數的某個最小項 (min term) 僅包含在其中一個prime implicant 時，則該 prime implicant 稱為必要項 (essential prime implicant)


求下列卡諾圖之 prime implicant, essential prime implicant 。

由卡諾圖中可看出， prime implicants= essential prime implicants=

YXZYZXZX ,,,

ZXZX ,

X

YZ

1111

110

10110100


求 F(A, B, C, D)=(0, 1, 2, 4, 5, 10, 11, 13, 15) 之必要項及最簡的 SOP 。

由卡諾圖中可看出共有 7 個 prime implicant ，其中essential prime implicant 只有 1 項

因此，化簡後CA

DCBorDBACBAABDCAF

ABCD

1110

1111

1101

11100

10110100


the simplified expression may not be unique F = BD+B'D'+CD+AD = BD+B'D'+CD+AB = BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'

( , , , ) (0,2,3,5,7,8,9,10,11,13,15)F A B C D Consider


3-4 Five-Variable Map Map for more than four variables becomes

complicated five-variable map: two four-variable map (one on

the top of the other)


Table 3.1 shows the relationship between the number of adjacent squares and the number of literals in the term.


Example 3-7 F = (0,2,4,6,9,13,21,23,25,29,31)

F = A'B'E'+BD'E+ACE


Another Map for Example 3-7

ABC

DE000 001 011 010 110 111 101 100

00 1 1

01 1 1 1 1 1

11 1 1

10 1 1

F = (0,2,4,6,9,13,21,23,25,29,31)


Another Map for Example 3-7


3-5 Product of Sums Simplification

Approach #1 Simplified F' in the form of sum of products Apply DeMorgan's theorem F = (F')' F': sum of products => F: product of sums

Approach #2: duality 將基本定理之 OR 與 AND 運算互換 , 把 0 變成 1 , 1 變成 0 ，

即可得出對偶式 (dual) 。 combinations of maxterms (it was minterms) M0M1 = (A+B+C+D)(A+B+C+D')

= (A+B+C)+(DD')= A+B+C

CDAB 00 01 11 1000 M0 M1 M3 M2

01 M4 M5 M7 M6

11 M12 M13 M15 M14

10 M8 M9 M11 M10


Example 3-8 F = (0,1,2,5,8,9,10)

F' = AB+CD+BD' Apply DeMorgan's theorem; F=(A'+B')(C'+D')(B'+D) Or think in terms of maxterms


Gate implementation of the function of Example 3-8


Consider the function defined in Table 3.2.

( , , ) (1,3,4,6)F x y z In sum-of-minterm:

( , , ) (0,2,5,7)F x y z

In sum-of-maxterm:

Taking the complement of F

( , , ) ( )( )F x y z x z x z


Consider the function defined in Table 3.2.

( , , )F x y z x z xz

Combine the 1’s:

( , , )F x y z xz x z

Combine the 0’s :


3-6 Don't-Care Conditions

The value of a function is not specified for certain combinations of variables BCD; 1010-1111: don't care

The don't care conditions can be utilized in logic minimization can be implemented as 0 or 1

Example 3-9 F (w,x,y,z) = (1,3,7,11,15) d(w,x,y,z) = (0,2,5)


F = yz + w'x'; F = yz + w'z F = (0,1,2,3,7,11,15) ; F = (1,3,5,7,11,15) either expression is acceptable

Also apply to products of sum


3-7 NAND and NOR Implementation

NAND gate is a universal gate can implement any digital system


NAND and NOR Implementation

Two graphic symbols for a NAND gate 對等邏輯

對等邏輯在邏輯電路的分析化簡上相當好用，它可以用來消去許多的迪莫根運算，


Two-level Implementation The implementation of Boolean function with

NAND gates requires that the functions be in sum of products

Example: F = AB+CD F = ((AB)' (CD)' )' =AB+CDFig. 3-20 Three ways to implement F = AB + CD


Two-level Implementation (cont.) Example 3-10

( , , ) (1,2,3,4,5,7)F x y z ( , , )F x y z xy x y z


Two-level Implementation (cont.)

The procedure Simplify the function and express it in sum of

products form. Draw a NAND gate for each product term; the

inputs to each NAND gate are the literals of the term

Draw a single NAND gate / invert-OR gate for the second sum term.

A term with a single literal requires an inverter in the first level. If the single literal is complemented, it can be connected directly to an input of the second-level NAND gate.


Multilevel NAND Circuits

AND-OR logic => NAND-NAND logic The general procedure for converting a multilevel

AND-OR diagram into an all-NAND diagram Convert all AND gates to NAND gates with AND-inverter

graphic symbols. Convert all OR gates to NAND gates with inverter-OR

graphic symbols. Check all the bubbles in the diagram. For every bubble

that is not compensated by another small circle along the same line, insert an invert or complement the input literal.

(1) 將邏輯函數化成積之和 (SOP) 最簡函數。 (2) 將此 SOP 取兩次補數，再以迪莫根定理化簡，使其 OR 運算全部變成以” ∙” (AND) 為連接的運算。


Multilevel NAND Circuits Example: F = A(CD + B) + BC

Fig. 3.22Implementing F = A(CD + B) + BC



Fig. 3.23 Implementing F = (AB +AB)(C+ D)


Example

Problem 3.16 Simplify the following functions, and implement

them with two-level NAND gate circuits:(a) F(A,B,C,D)=A’B’C+AC’+ACD+ACD’+A’B’D’(b) F(A,B,C)=(A’+B’+C’)(A’+B’)(A’+C’)



Simply the Multilevel NAND Circuits


NOR Implementation NOR function is the dual of NAND function The NOR gate is also universal

The function be simplified into product-of-sum form. The simplified POS express is obtained from the map by combing

the 0’s and complementing. The transformation from the OR-AND diagram to a NOR

diagram Changing the OR gates to NOR gates with OR-invert graphic

symbols Changing the AND gate to a NOR gate with an invert-AND graphic

symbol. A single literal term going into the second-level gate must be

complemented. 方法： (1) 將邏輯函數化成和之積 (POS) 最簡函數。 (2) 將此 POS 取兩次補數，再以迪莫根定理化簡，使其 AND 運

算全部變成以”＋” (OR) 為連接的運算。


NOR Implementation

Logic operations with NOR gates


Two graphic symbols for a NOR gate

Example: F = (A + B)(C + D)E

Fig. 3.26ImplementingF = (A + B)(C + D)E


NOR Implementation

F=(AB+E)(C+D)


Example: F = (AB +AB)(C + D)

Fig. 3.27Implementing F = (AB +AB)(C + D) with NOR gates

NOR Implementation


Example

Problems 3.19 Simply the following functions, and implement

them with two-level NOR gate circuit:(a) F=wx’+y’z’+w’yz’(b) F(x,y,z)=[(x+y)(x’+z)]’


3-8 Other Two-level Implementations Wired logic

a wire connection between the outputs of two gates open-collector TTL NAND gates: wired-AND logic the NOR output of ECL gates: wired-OR logic

( ) ( ) ( ) ( )( )

( ) ( ) [( )( )]

F AB CD AB CD A B C D

F A B C D A B C D

AND-OR-INVERT function

OR-AND-INVERT function


Nondegenerate Forms

Consider four types of gates: AND, OR, NAND, and NOR.

16 possible combinations of two-level forms eight of them: degenerate forms = a single operation The eight nondegenerate forms

AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND, OR-AND, AND-OR

AND-OR and NAND-NAND = sum of products OR-AND and NOR-NOR = product of sums NOR-OR, NAND-AND, OR-AND, AND-OR = ?


AND-OR-Invert Implementation

AND-OR-INVERT (AOI) Implementation NAND-AND = AND-NOR = AOI F = (AB+CD+E)' F' = AB+CD+E (sum of products)

simplify F' in sum of products


Other Two-level Implementations (cont.)

OR-AND-INVERT (OAI) Implementation OR-NAND = NOR-OR = OAI F = ((A+B)(C+D)E)' F' = (A+B)(C+D)E (product of sums)

simplified F' in products of sum


Tabular Summary and Examples

Example 3-11 F' = x'y+xy'+z (F': sum of products) F = (x'y+xy'+z)' (F: AOI implementation)

F = x'y'z' + xyz‘ (F: sum of products) F' = (x+y+z)(x'+y'+z) (F': product of sums) F = ((x+y+z)(x'+y'+z))' (F: OAI)


Tabular Summary and Examples


3-9 Exclusive-OR Function Exclusive-OR (XOR): XOR is equal to 1 if only x and

y differ in value. xy = xy'+x'y

Exclusive-NOR (XNOR): XNOR is equal to 1 if both x and y are equal.

(xy)' = xy + x'y' Some identities

x0 = x x1 = x' xx = 0 xx' = 1 xy' = (xy)' x'y = (xy)'

Commutative and associative AB = BA (AB) C = A (BC) = ABC


Implementations (x'+y')x + (x'+y')y = xy'+x'y = xy

Exclusive-OR Function (cont.)



Odd function ABC = (AB'+A'B)C' +(AB+A'B')C

= AB'C'+A'BC'+ABC+A'B'C = (1,2,4,7)

The three-variable exclusive-OR function is equal to 1 if only one variable is equal to 1, or if all three variables are equal to 1.

For more variables, an odd number of variables be equal to 1.



The four minterms of the function are a unit distance apart from each other.

The odd function is identified from the four minterms whose binary values have an odd number of 1’s.

The complement of an odd function is an even function.

The three-variable even function is equal to 1 when an even number of its variables is equal to 1.

Logic diagram of odd and even functions


Four-variable Exclusive-OR function ABCD = (AB’+A’B)(CD’+C’D)

= (AB’+A’B)(CD+C’D’)+(AB+A’B’)(CD’+C’D)



Parity Generation and Checking XOR functions are very useful in error detection

and correction codes. Parity generator

A circuit that generates the parity bit in the transmitter. a parity bit: P = xyz

Parity checker A circuit that checks the parity bit in the receiver. parity check: C = xyzP C=1: an odd number of data bit error C=0: correct or an ever # of data bit error



3.10 Hardware Description Language (HDL)

Hardware Description Language (HDL) HDL is a computer-based language that describe

the design of digital systems in a textual form. Used for describing hardware structure and the

function/behavior of logic circuits. HDL are used in several major steps in the

design flow of an integrated circuit Design entry Functional simulation or verification Logic synthesis Timing verification Fault simulation


Hardware Description Language (HDL) (cont.)

Design entry Creates an HDL-based description of the functionality that is to be

implemented in hardware. The description can be in a variety of forms:

Boolean logic equation, truth tables, a netlist of interconnected gates, an abstract behavioroal model.

Logic simulation Displays the behavior of a digital system through the use of a

computer. A simulator interprets the HDL description and produces readable

output. Logic synthesis

The process of deriving a list of physical components and their interconnections from the model of a digital system described in an HDL.

Logic synthesis is similar to compiling a program in a conventional high-level language.

Logic synthesis produces a database describing the elements and structure of a circuit.


Hardware Description Language (HDL) (cont.)

Timing verification Confirms that the fabricated integrated circuit will operate at

a specified speed. Propagation delays ultimately limit the speed at which a

circuit can operate. Timing verification checks each signal path to verify that it is

not compromised by propagation delay. Fault simulation

Compares the behavior of an ideal circuit with the behavior of a circuit that contains a process-induced flaw.

Fault simulation is used to identify input stimuli that can be used to reveal the difference between the faulty circuit and the fault-free circuit.


A Top-Down Design Flow

Specification

RTL design andSimulation

Logic Synthesis

Gate Level Simulation

ASIC Layout FPGA Implementation

第三版內容，參考用 !


Module Declaration

Examples of keywords:module, end-module, input, output, wire, and, or, and not.

Any text between two forward slashes (//) and the end of the line is interpreted as a comment.

Verilog is case sensitive. A module is the fundamental descriptive unit in the Verilog language

Fig. 3-37 Circuit to demonstrate an HDL


HDL Example 3.1

HDL description for circuit shown in Fig. 3.37


Gate Displays

Example: timescale directive

‘timescale 1 ns/100ps

30ns

10ns

20ns


HDL Example 3.2

Gate-level description with propagation delays for circuit shown in Fig. 3.37


HDL Example 3.3

Test bench for simulating the circuit with delay


Simulation output for HDL Example 3.3


Boolean Expression

Boolean expression for the circuit of Fig. 3.37

Boolean expression:

HDL Example 3.4


HDL Example 3.4


User-Defined Primitives

General rules:

Declaration:

Implementing the hardware in Fig. 3.39


HDL Example 3.5


HDL Example 3.5 (Continued)


Fig. 3.39Schematic for circuit with_UDP_02467

chapter 3 gate-level minimization 授課教師 : 張傳育 博士 (chuan-yu chang ph.d.) e-mail:...

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chapter 3 gate-level minimization 授課教師 : 張傳育博士 (chuan-yu chang ph.d.) e-mail:...