32

Chapter 3

IMPLEMENTATION OF QALU BASED SPWM CONTROLLER

THROUGH FPGA

3.1. Introduction

This Chapter presents an implementation of area efficient SPWM

control through single FPGA using Q-Format. The SPWM and controller

is simulated using ModelSim 5.7 and implemented using Xilinx 9.2i.

Through the simulation, the area utilization in FPGA for the SPWM

controller is obtained and verified with the existing FPGA

implementations. Then, the experiments are conducted to verify the

possibility of single chip FPGA implementation using QALU for SPWM for

VSI with induction motor load.

In addition to the basic concepts that are discussed in Chapter 1 and

2, the implementation of FPGA based SPWM controller requires the

following concepts:

i. Voltage Source Inverter (VSI) [119]

ii. Principle and Algorithm of SPWM [120]

The following section describes the basics of VSI and SPWM. After the

short revision of basics required, implementation of QALU based SPWM

is presented [28-32, 95, 107].

3.2. Three Phase Voltage Source Inverter

The function of an inverter is to convert DC voltage to a symmetric AC

output voltage of desired magnitude and frequency. The output voltage

33

can be varied either by varying DC input voltage or by controlling the

gain of the inverter with PWM. The output voltage waveforms of ideal

inverters should be sinusoidal. However, the practical inverters will have

non-sinusoidal waveforms due to harmonics. For low and medium power

applications, square-wave or quasi-square wave voltages may be

acceptable and for high power applications, low distorted sinusoidal

waveforms are required. The VSI topology and the operating principles

are described in [119-120]. In order to have a maximum fundamental of

50 Hz and fs of 20 kHz , the value of filter inductance is 0.2 mH and the

filter capacitance is 10 µF are chosen [4]. The value of DC link capacitor

is 500 µF /1000V [3].

3.3. Sinusoidal Pulse Width Modulation (SPWM)

This section deals with the development of SPWM control for inverter

fed induction motor as a load. The basic principles and algorithm for

SPWM is presented.

3.3.1. Principle of SPWM

The most widely used method of PWM is carrier based. Sinusoidal

modulation is based on triangular carrier signal and level comparison

between them produces the PWM gating signal. The time for vertex

sampling point and the nadir sampling is t1 and t2 respectively [2, 56].

)7,5,3,1,k(when2

)6,4,2,0,k(when2

2

1

kTt

kTt

t

t

(3.1)

tpu is the width of SPWM pulses, which can be expressed as

34

2121 sin42

sin4

sinsin2

12

tMTT

tMT

ttMTt ttttpu

(3.2)

where Ma= Uc/Ur is the modulation index, Uc is the maximum value of

the sine wave, Tt represents the period of the triangular carrier, and ω is

the angular frequency of the sine wave.

3.3.2. Voltage Control of Three Phase Inverters through SPWM

A three-phase inverter may be considered as three single phase

inverters and the output of each single phase inverter is shifted by 1200.

There are three sinusoidal reference waves (ura, urb and urc) each shifted

by 1200. A carrier wave is compared with the reference signal

corresponding to a phase to generate the gating signals for that phase.

Comparing the carrier signal vcr with the reference phases vra, vrb and vrc

produces the three PWM gating signals P1, P3 and P5 respectively. The

instantaneous line-to-line output voltage is vab = Udc (P1-P3). The

normalized carrier frequency mf should be odd multiple of three. Thus,

all phase-voltage (uaN, ubN, and ucN) are identical, but 1200 out of phase

[2, 119-120].

3.3.3. Algorithm of SPWM

Step 1: The Three phase sinusoidal reference signal with 120°

displacement can be generated using following relations:

)3

2sin(

)sin(

tAV

tAV

rbref

raref(3.3)

35

The frequency that the sine wave will be modulated can be calculated

from the following formula,

nsXTstepstepf

2)( (3.4)

where, f(step) = desired frequency, TS = the time period between each

update i.e. the PWM period, n = the number of bits in the counter

register and, step = the step size used.

Step 2: Generation of triangular carrier wave with desired fs.

Step 3: Comparator function of the sinusoidal and triangular waves,

i.e. the intersections between the reference voltage and the carrying wave

gives the time of opening and closing instants of the switches.

3.4. Implementation of QALU based SPWM controller through FPGA

Sinusoidal PWM is practically used in three phase power conversion

applications due to its simplicity in implementation. From the

literatures, a comparison between DSP and FPGA based control

capabilities for PWM power converters has been demonstrated and given

that the FPGA based digital control is better than the DSP in [53]. A

digital ASIC is used to replace a microprocessor in SPWM control

implementation [54]. In [56], the three phase SPWM VVVF controller is

implemented using FPGA. The above PWM controller can be used for

high performance VVVF AC drives. The design takes more FPGA area and

it has to be optimised.

36

A high precision programmable digital three phase SPWM chip based

on variable sampling frequency method is designed. The chip can be

programmed by Microcontroller Unit [58]. The concept of slope PWM

generated by comparing a trapezoidal modulator wave with a

discontinuous triangular carrier wave is implemented using a Xilinx

XC3S200 FPGA with external Digilent S3 processor. The integer fixed

point arithmetic is used in the signal processing used. The total resource

for above implementation is around 30% of the available resources [61].

In [63], an implementation of SPWM in a multi phase inverter using DSP-

TMS320C28335 and Altera Cyclone FPGA is presented. FPGA serves as a

coprocessor, producing 30 independent PWM pulses based on timing

signals from DSP.

Most of the SPWM controllers are implemented with a host processor

to perform arithmetic computations and an FPGA to generate PWM

gating signals [53-54, 58-63]. The signal processing is a key issue in the

performance of a digital system to achieve a single chip solution with

reduced FPGA resource utilisation.

To overcome the above limitations such as utilization of host

processor and more resource utilization in FPGA, QALU based SPWM

controller is developed and implemented.

37

3.4.1. Implementation VLSI Architecture for QALU based SPWM

Controller through FPGA

The schematic diagram of SPWM is shown in Fig. 3. 1 and the VLSI

architecture for implementation of SPWM controller through QALU based

on FPGA is developed and shown in Fig 3. 2. The SPWM controller is

developed using VHDL. The functional flow diagram is shown in Fig. 3. 3.

The designed VLSI Architecture for SPWM controller is implemented in a

reprogrammable FPGA chip single XC3S400PQ208 FPGA. The internal

modules of the architecture are Q –Format Arithmetic Logic Unit (QALU),

clock divider, frequency selector, sin generator, PWM controller and dead

time module. The QALU performs all arithmetic and logic functions in

Q-Format representation [28,95].

Fig. 3. 1. Schematic diagram of carrier based Sinusoidal PWM

Carrier

+

+

+

38

P5

DeadTimeinsert

ClockDivider

PWMControllerQALU

Fc

Foclk

Fig. 3. 2. VLSI Architecture for QALU based SPWM

Frequencyselector Sin

generator

PWM A

PWM B

PWM C

P1P3

P4P6

Td

P2

PWM

Out

put

Fig. 3. 3. Functional flow diagram of QALU based SPWM control

Start

Generating sin wave and triangular waves

Insert the desired delay time

PWM output at the Configured pin as per UCF

Stop

Initialize the QALU

Compare Sin and Triangular wave values in comparatorto generate the pulses.

39

The implementation of QALU is constructed as generic library function,

and each module is described with VHDL, compiled, simulated, and

implemented [28, 125]. The pseudo code for SPWM is shown in Fig. 3. 4.

3.4.1.1. Q –Format Arithmetic Logic Unit (QALU)

The QALU designed performs the data representation, arithmetic and

logic operations in the SPWM algorithm using Q-Format. The QALU in

FPGA is implemented as generic library function. This ALU can be used

as core for designing FPGA based dedicated processors for inverter and

motor control applications [28].

3.4.1.2. Clock Divider

In the FPGA development board, a common clock of 10 MHz is

provided by the oscillator. But, the operation speed or clock for each

module in the design is varying. Therefore, a clock divider is used to

generate the clock for sine wave generator, triangular wave generator

Pseudo code:

Functional unit name: QALU based SPWM

Input: sine wave, triangular wave, M, Fz and Td

Output: SPWM waves

Steps:1. Read the set values.

2. Convert the data corresponding to the sampling instant in Qm.n format

by QALU in the design as library function.

3. Initialize the Comparator function.

4. PWM output is inserted with delay time.

End

Fig. 3. 4. Pseudo code for QALU based SPWM

40

comparator and PWM modules. Foclk is the oscillator clock. To get

different frequency ratios the clock divider is needed to generate 50%

duty cycle of carrier from the base clock. Fc is control clock. The output

voltage control is employed for controlling the fundamental.

3.4.1.3. Sine Generator

The three phase sin waves with the 120° displacement from each

other are the reference waves. This reference waves are generated by the

sin generator module. The sine table is designed as a look up table which

contains the sine values for 180° of the sin wave for each phase. The

frequency of the sin wave can be varied.

3.4.1.4. PWM Generator

The PWM pulses are generated by comparing the sinusoidal referece

and triangular carrier signal. The relation for the vertex sampling point t1

and the nadir sampling point t2 are evaluated using the relations (3.1).

The frequency relation between the reference and carrier should satisfy

the Nyquist theorm. Three comparators and a counter is used to generate

the PWM pulses. One compare unit with two PWM outputs is used for

each leg in the inverter. The fo can be varied by changing the Foclk and by

adjusting the clock divider.

3.4.1.5. Dead time Insertion

The phase legs of the inverter have to be protected from short circuit.

Therefore, a programmable delay-time controller is introduced in the

designed SPWM architecture. The turn-off time of power devices is

usually longer than its turn-on time, and, therefore, an appropriate delay

41

time must be inserted between these two gating signals. The length of

this delay time is usually about 1.5 to 2 times the maximum turn-off

time. The output signals ta, tb , tc and td decides the switching pattern for

positive, negative legs respectively as shown in Fig. 3. 5. The relationship

of the gating signal is given in (3.7) [64, 91-92].

2

TonTst 1

2

TonTst 2

2ΔT)(TonTst 3

2ΔT)(TonTst 4 (3.7)

3.4.2. Implementation of SPWM Controller

In order to evaluate the performance of QALU based SPWM controller,

the VSI fed induction motor load is considered. SPWM controller is

simulated, implemented and its effectiveness is verified experimentally

using Xilinx SPARTAN XC3S400PQ208 FPGA.

Fig. 3. 5. PWM waveforms with delay time

Ton Toff

Ts

TonT

Ts

t

t

tatb

tc

td T

Ts Ts

P1

P4

42

3.4.2.1. Simulation Results of QALU based SPWM Controller

The SPWM controller has been simulated using ModelSim 5.7 and

implemented using Xilinx 9.2i. The QALU implementation has been

validated with the simulation and implementation of an arithmetic

operation (multiplication) and the corresponding implementation report

and results are discussed in Chapter 2. The implementation report of the

designed SPWM modulator is shown in Table 3. 1. The simulation results

for SPWM output waveforms for different fo, fs and M are shown in Fig. 3.

6 to Fig. 3. 10. The PWM waveform with delay time is shown in Fig. 3. 11.

The simulation is carried out with the frequencies from low to high

frequency up to 100 kHz.

Table 3. 1. Implementation report of QALU based SPWM

Logic Utilization Used Available Utilization

Number of Slice Flip Flops 341 7,168 4%Number of 4 input LUTs 1,102 7,168 15%Number of occupied Slices 737 3,584 20%

No.of Slices containing related logic 737 737 100%

Number of bonded IOBs 13 141 9%

Number of MULT18X18s 1 16 6%

Total equ. gate count for design 15,587

43

Fig. 3. 7. Three Phase SPWM waveforms: fs = 40 kHz, fo = 50 Hz, and M=0.75

Fig. 3. 6. Three Phase SPWM waveforms: fs = 20 kHz, fo = 50 Hz, and M=0.65

Analog Sine signal

Fig. 3. 8. Three Phase SPWM waveforms: fs = 20 kHz, fo = 50 Hz, and M=0.65 (in analog form)

44

Fig. 3. 10. Three Phase SPWM waveforms: fs = 10 kHz, fo = 30 Hz, and M=0.75

Fig. 3. 9. Three Phase SPWM waveforms: fs = 20 kHz, fo = 50 Hz, and M=0.65( Expanded scale)

Fig. 3. 11. Three Phase SPWM waveforms: fs = 20 kHz, fo = 50 Hz, and M=0.65showing the dead time

Dead time

45

3.4.2.2. Experimental verification of QALU based SPWM Controller

The experimentation has been carried out with the FPGA hardware

SPARTAN XC3S400PQ208 from Xilinx. Inc. The hardware setup shown in

Fig. 3. 12, consists of FPGA, three phase VSI, bridge rectifier to supply

DC voltage, opto isolator, pulse driver and induction motor. The power

module is 3- phase VSI Bridge with 6 power IRFP460MOSFETs. The opto

isolator IL260 provides the electrical isolation between the FPGA

controller and power circuit. The MOSFET amplifier provides the

amplified PWM signals to drive the gate of the power devices. The FPGA

in the system can operate with a maximum clock of 50 MHz, but the

power devices will not respond to such high switching frequencies.

Induction motor

Current sensor

Speed sensor

Fig. 3. 12. Experimental setup of SPWM controller fed threeinduction motor

FPGA

Pulse driverAmp OPTO

isolation

PowerModule

46

A. Power Converter

The low cost converter with 3 leg VSI power module, Opto isolator,

and snubber is fabricated. The first step in designing the power converter

is to select the power semiconductor devices. The input to the Inverter is

variable form 0 – 300 V DC and system is designed for an average load

current of 16A.

B. MOSFETs and Driver Circuit

The three phase VSI consists of six MOSFETs (IRFP460) which are

sequentially controlled by the PWM pulses. The PWM pulses from the

FPGA are having magnitude of 3.2 V. This is amplified to a level of 12 V

using the amplifier. The drive circuit requires isolated DC power

supplies. The output of the gate driver is connected across the gate and

source of the power MOSFET. The source terminal of the upper MOSFET

is floating and it can either be at 0V or at 500. As this is connected to the

gate driver ground, this floating ground would generate lot of common

mode noise. This would interfere with the normal operation of the circuit

and it might malfunction. To avoid this situation, the ground of each gate

driver output is isolated from the grounds of the other gate driver and

also from the input stage ground. The input-output isolation is achieved

by an opto-coupler IL260.

C. Current sensing circuit

In order to measure, current sensing circuit is designed. The current

sensing circuit is shown in Fig. 3. 13.

47

D. Speed sensing circuit

The speed measurement system has a proximity sensor and a pulley

with 12 steel tips which produces 12 pulses per revolution of the motor.

The pulses are counted for a minute to have speed in revolutions per

minute (rpm).

E. SPARTAN 3 FPGA board

The Spartan FPGA development board has XC3S400PQ208 FPGA

from Xilinx. The FPGA kit provides a complete development environment,

and includes power supply for the board, JTAG connector and on board

PROM. The features of this FPGA are 400 K gate density, 896 CLBs, 16

multipliers, and 264 user I/Os. The maximum clock is 50 MHz [126].

3.4.2.3. Experimental Results

In the experiments, the fo has been varied from 0.3 Hz to 60 Hz and

the fs is varied from 1 kHz to 20 kHz and the PWM switching patterns are

achieved. The results for PWM output in the different channels are

obtained and the PWM patterns in the channels P1and P5 are shown in

Fig. 3. 13. Circuit diagram of current sensing circuit

To measurement

ILTS 100 P

M

G

48

Fig. 3. 14. to Fig. 3. 16 respectively. The result for the line to line voltage

(R-Y) for three phase motor load is shown in Fig. 3. 17. The Voltage THD

when fo =50 Hz with fs = 10 kHz and 2 kHz are shown in Fig. 3. 18 and

Fig. 3. 19 respectively.V

olta

ge5

V/d

iv

100 ms /div

Fig. 3. 15. SPWM waveform in P1: fs=2.63 kHz and f0 = 50 Hz (Expanded scale)

Vol

tage

5 V

/div

1s/div

Fig. 3. 14. SPWM waveform in P1: fs =2.63 kHz and f0 = 50 Hz

49

Fig. 3. 17. The Line to Line voltage (R-Y) for three phase starconnected R load: fs=10 kHz, f0 = 50 Hz, and M=0.65

Vol

tage

25

V/d

iv

Time 5 ms/div

Fig. 3. 18. Voltage THD: fs=10 kHz, f0 = 50 Hz, and M=0.65

% T

HD

(50

%/

div)

500 ms /div

Fig. 3. 16. SPWM wave form in P5: fs=10 kHz and f0 = 50 Hz

Vol

tage

5 V

/div

50

The experimental results of the PWM gating signal generation from

FPGA and the AC output waveform of the three phase inverter shows the

feasibility of the practical implementation of QALU based SPWM in single

FPGA in real time. The speed of the induction motor at various fo with fs

of10 kHz is given in Table 3. 2.

Table 3. 2. Speed of Induction motor drive (0.25 hp/0.18 kW, 4 pole,

3phase, 415 V, 50 Hz) for different f0

S.No FundamentalFrequency, fo (Hz)

Calculated speed for 4pole (RPM)

Measuredspeed (RPM)

1 0.15 4.5 3.52 0.3 9 7.03 1.0 30 264 3.0 90 845 10.0 300 2916 15.0 450 4397 30.0 900 8788 50.0 1500 1489

Fig. 3. 19. Voltage THD: fs=2 kHz, f0 = 50 Hz, and M=0.65

% T

HD

(50

%/

div)

51

3.5. Discussions

The results show that the Q-Format implementation takes total gate

count of 348 and integer fixed format implementation takes 975. The Q-

Format takes less chip resources and also the results are accurate when

compared to integer fixed format [28-32, 95, 107]. The implementation

report of QALU SPWM modulator architecture is shown in Table 3.1. The

design occupies 15587 gates, 1102 LUTs and 13 IOBs.

In order to compare the performance of the developed SPWM

controllers some of the reported examples are considered. A digital ASIC

is used to replace a microprocessor in a SPWM system as developed in

[54]. In high performance multilevel/multiphase drives and power filter

applications, the controller is implemented with the SPWM controllers, in

which the host processor is used. In DSP-FPGA based implementations,

it requires additional controller and the data representation is integer

fixed-point [54-58]. The SPWM reported in [56], the logic utilization is

more and it is to be optimized. The developed QALU based SPWM

controller overcomes the limitations in the existing SPWM controllers

such as more FPGA resource usage and the host processor for

computations. The Performance comparison of SPWM controller with

existing FPGA implementations is presented in Table 3. 3.

52

Table 3. 3. Performance comparison of SPWM controller with existingFPGA implementations

S.N0

Performance Details Developed 8 bitSPWM

Conventional SPWM

1 Use DSP processors for arithmeticcomputations in PWM control

QALU can do thearithmetic

computations in FPGA

DSPs used for arithmeticcomputations [53-54, 58-63]

2 Device utilization : No. of slicestaken by the design

341 Given that resource utilizationto be optimized [85]

3 Possibility of single chipimplementation

Possible using QALU Not Possible by conventionaldesign

3.6. Conclusion

The single chip FPGA implementation for SPWM using has been

developed using QALU. The SPWM IP core is designed using VHDL and a

single FPGA, SPARTAN XC3S400PQ208 from Xilinx Inc. The simulations

are carried out using ModelSim 5.7 and the implementation is carried

out using Xilinx foundation series 9.2i. The area efficient SPWM core is

implemented in a single FPGA and the experimentation is carried out

with a 3- phase VSI for different operating frequencies. The QALU can be

used as IP core for any FPGA based application. The developed SPWM

core can be used as modulator for high performance AC drives, UPS

system and power conditioning systems. Also these SPWM controller can

be used provide a single FPGA implementation for multilevel and multi

phase drives. Moreover, the developed SPWM with QALU is more suitable

for single chip FPGA and SOC implementations of power electronic

converter control algorithms and motor control systems.