chapter 4 :jfet
DESCRIPTION
CHAPTER 4 :JFET. Junction Field Effect Transistor. Introduction (FET). Field-effect transistor (FET) are important devices such as BJTs Also used as amplifier and logic switches Types of FET: MOSFET (metal-oxide-semiconductor field-effect transistor) Depletion-mode MOSFET - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/1.jpg)
CHAPTER 4 :JFET
Junction Field Effect Transistor
![Page 2: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/2.jpg)
Introduction (FET) Field-effect transistor (FET) are important
devices such as BJTs Also used as amplifier and logic switches Types of FET:
MOSFET (metal-oxide-semiconductor field-effect transistor)
Depletion-mode MOSFET JFET (junction field-effect transistor)
What is the difference between JFET and MOSFET?
![Page 3: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/3.jpg)
Current-controlled amplifiers
![Page 4: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/4.jpg)
Voltage-controlled amplifiers
![Page 5: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/5.jpg)
High input impedance (M) (Linear AC amplifier system)
Temperature stable than BJT Smaller than BJT Can be fabricated with fewer processing BJT is bipolar – conduction both hole and
electron FET is unipolar – uses only one type of current
carrier Less noise compare to BJT Usually use as logic switch
Introduction.. (Advantages of FET)
![Page 6: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/6.jpg)
Disadvantages of FET
Easy to damage compare to BJT ???
![Page 7: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/7.jpg)
Junction field-effect transistor (JFET)
![Page 8: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/8.jpg)
There are 2 types of JFET n-channel JFET p-channel JFET
Three Terminal Drain – D (Saliran) Gate -G (Get) Source – S (Punca)
Junction field-effect transistor..
![Page 9: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/9.jpg)
N channel JFET: Major structure is n-type material (channel)
between embedded p-type material to form 2 p-n junction.
In the normal operation of an n-channel device, the Drain (D) is positive with respect to the Source (S). Current flows into the Drain (D), through the channel, and out of the Source (S)
Because the resistance of the channel depends on the gate-to-source voltage (VGS), the drain current (ID) is controlled by that voltage
N-channel JFET
![Page 10: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/10.jpg)
N-channel JFET..
![Page 11: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/11.jpg)
P channel JFET: Major structure is p-type material
(channel) between embedded n-type material to form 2 p-n junction.
Current flow : from Source (S) to Drain (D)
Holes injected to Source (S) through p-type channel and flowed to Drain (D)
P-channel JFET
![Page 12: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/12.jpg)
P-channel JFET..
![Page 13: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/13.jpg)
Water analogy for the JFET control mechanism
![Page 14: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/14.jpg)
JFET Characteristic Curve
To start, suppose VGS=0 Then, when VDS is increased, ID increases. Therefore,
ID is proportional to VDS for small values of VDS
For larger value of VDS, as VDS increases, the depletion layer become wider, causing the resistance of channel increases.
After the pinch-off voltage (Vp) is reached, the ID becomes nearly constant (called as ID maximum, IDSS-Drain to Source current with Gate Shorted)
![Page 15: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/15.jpg)
ID versus VDS for VGS = 0 V.
JFET Characteristic Curve
![Page 16: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/16.jpg)
JFET for VGS = 0 V and 0<VDS<|Vp|
Channel becomes narrower as VDS is increased
![Page 17: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/17.jpg)
Pinch-off (VGS = 0 V, VDS = VP).
![Page 18: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/18.jpg)
Application of a negative voltage to the gate of a JFET.
![Page 19: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/19.jpg)
JFET Characteristic Curve..
For negative values of VGS, the gate-to-channel junction is reverse biased even with VDS=0
Thus, the initial channel resistance is higher (in which the initial slope of the curves is smaller for values of VGS closer to the pinch-off voltage (VP)
The resistance value is under the control of VGS
If VGS is less than pinch-off voltage, the resistance becomes an open-circuit ;therefore the device is in cutoff (VGS=VGS(off) )
The region where ID constant – The saturation/pinch-off region
The region where ID depends on VDS is called the linear/triode/ohmic region
![Page 20: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/20.jpg)
n-Channel JFET characteristics curve with IDSS = 8 mA and VP = -4 V.
JFET Characteristic Curve
![Page 21: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/21.jpg)
p-Channel JFET
![Page 22: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/22.jpg)
p-Channel JFET characteristics with IDSS = 6 mA and VP = +6 V.
![Page 23: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/23.jpg)
Characteristics for n-channel JFET
![Page 24: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/24.jpg)
P
+
+
+
Characteristics for p-channel JFET
![Page 25: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/25.jpg)
Operation of n-channel JFET JFET is biased with two voltage sources:
VDD
VGG
VDD generate voltage bias between Drain (D) and Source (S) – VDS
VDD causes drain current, ID flows from Drain (D) to Source (S)
VGG generate voltage bias between Gate (G) and Source (S) with negative polarity source is connected to the Gate Junction (G) – reverse-biases the gate; therefore gate current, IG = 0.
VGG is to produce depletion region in N channel so that it can control the amount of drain current, ID that flows through the channel
![Page 26: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/26.jpg)
Transfer Characteristics
The input-output transfer characteristic of the JFET is not as straight forward as it is for the BJT. In BJT:
IC= IB
which is defined as the relationship between IB (input current) and IC (output current).
![Page 27: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/27.jpg)
Transfer Characteristics..
In JFET, the relationship between VGS (input voltage) and ID (output current) is used to define the transfer characteristics. It is called as Shockley’s Equation:
The relationship is more complicated (and not linear)As a result, FET’s are often referred to a square law devices
2GS
D DSSP
V I = I 1 -
VVP=VGS (OFF)
![Page 28: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/28.jpg)
Defined by Shockley’s equation:
Relationship between ID and VGS. Obtaining transfer characteristic curve axis
point from Shockley: When VGS = 0 V, ID = IDSS
When VGS = VGS(off) or Vp, ID = 0 mA
)(
2
)(
1 offGSP
offGS
GSDSSD VV
V
VII
Transfer Characteristics…
![Page 29: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/29.jpg)
Transfer Characteristics
JFET Transfer Characteristic Curve JFET Characteristic Curve
![Page 30: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/30.jpg)
Exercise 1
DGS P
DSS
I V = V 1 -
I
2GS
D DSSP
V I = I 1 -
V
VGS ID0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
Sketch the transfer defined byIDSS = 12 mA dan VGS(off) = - 6
![Page 31: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/31.jpg)
Exercise 1
DGS P
DSS
I V = V 1 -
I
Sketch the transfer defined by IDSS = 12 mA dan VGS(off) = Vp= - 6
IDSS
IDSS/2
IDSS/4
2GS
D DSSP
V I = I 1 -
VVGS =0.3VP
VGS =0.5VP
![Page 32: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/32.jpg)
Answer 1
![Page 33: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/33.jpg)
Exercise 2
DGS P
DSS
I V = V 1 -
I
2GS
D DSSP
V I = I 1 -
V
VGS ID0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
Sketch the transfer defined byIDSS = 4 mA dan VGS(off) = 3 V
![Page 34: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/34.jpg)
Exercise 2
DGS P
DSS
I V = V 1 -
I
Sketch the transfer defined by IDSS = 4 mA dan VGS(off) = 3V
2GS
D DSSP
V I = I 1 -
V
VGS =0.5VP
VGS =0.3VP
VP
IDSS
IDSS/2
IDSS/4
![Page 35: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/35.jpg)
Answer 2Answer 2
![Page 36: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/36.jpg)
DC JFET Biasing
Just as we learned that the BJT must be biased for proper operation, the JFET also must be biased for operation point (ID, VGS, VDS)
In most cases the ideal Q-point will be at the middle of the transfer characteristic curve, which is about half of the IDSS.
3 types of DC JFET biasing configurations : Fixed-bias Self-bias Voltage-Divider Bias
![Page 37: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/37.jpg)
Fixed-bias
VDS
+_
VGG
VGS_
RD
VDD
RG
+C1
C2
Fixed-bias
+
Vin
_
+
Vout
_
+ Use two voltage sources: VGG, VDD
VGG is reverse-biased at the Gate – Source (G-S) terminal, thus no current flows through RG (IG = 0).
![Page 38: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/38.jpg)
Fixed-bias.. DC analysis
All capacitors replaced with open-circuit
VDS
+_
VGG
VGS_
RD
VDD
RG
+
Loop 1
![Page 39: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/39.jpg)
Fixed-bias…
1. Input Loop By using KVL at loop 1:
VGG + VGS = 0 VGS = - VGG
For graphical solution, use VGS = - VGG to draw the load line
For mathematical solution, replace VGS = -VGG in Shockley’s Eq. ,therefore:
2. Output loop- VDD + IDRD + VDS = 0
VDS = VDD – IDRD
3. Then, plot transfer characteristic curve by using Shockley’s Equation
2
)(
2
)(
11
offGS
GGDSS
offGS
GSDSSD V
VI
V
VII
![Page 40: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/40.jpg)
Example : Fixed-bias
2GS
D DSSP
V I = I 1 -
V
Determine the following network:
1. VGSQ
2. IDQ
3. VD
4. VG
5. VS
![Page 41: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/41.jpg)
Mathematical Solutions
GSQ GGV = - V = - 2
2 2GS
DQ DSSP
2
V - 2 I = I 1 - = 10mA 1 -
V -8
= 10mA 0 5.6.75 25mA
DS DD D DV = V - I R = 16 - 5.625mA 2k
= 16V -11.25V = 4.75V
![Page 42: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/42.jpg)
Graphical solution for the network
GSQ GGV = - V = - 2
DS 4V = .75V
D
G
S
V =
V =
4.75V
- 2V
V = 0V
Draw load line for:
![Page 43: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/43.jpg)
Self-bias
Using only one voltage source
![Page 44: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/44.jpg)
DC analysis of the self-bias configuration.
G G GRG
RG
Since I 0A, V I R
thus V 0A,
Q point for VGS
![Page 45: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/45.jpg)
Graphical Solutions:Defining a point on the self-bias line.
VGS ID0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
![Page 46: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/46.jpg)
Graphical Solutions: Sketching the self-bias line.
D DSS
GS D S
DSS S
I = I 2
V = -I R
I R = -
2 DS DD D S DV = V - I R + R
S D SV = I R
![Page 47: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/47.jpg)
Mathematical Solutions:
Replace in the Shockley’s Equation:
By using, quadratic equation and formula, choose value of ID that relevant within the range (0 to IDSS): nearly to IDSS/2
Find VGS by using ;also choose VGS that within the range (0 to VP)
2
)(
2
)(1
;
1
P
SDDSSD
offGSPP
GSDSSD
V
RIII
therefore
VVV
VII
![Page 48: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/48.jpg)
Example : Self-bias configuration
GSQ
DQ
D
G
1. V
2. I
Det
3. V
e
rmine the following for
4. V
the network
5. Vs
![Page 49: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/49.jpg)
Graphical Solutions:
![Page 50: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/50.jpg)
Sketching the transfer characteristics curve
Vgs ID
0 IDSS
0.3Vp IDSS/2
0.5Vp IDSS/4
Vp 0 mA
![Page 51: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/51.jpg)
Sketching the self-bias line
D GS
D GS
When I = 4mA, V =
When I = 8mA, V
- 4V
= - 8V
![Page 52: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/52.jpg)
Graphical Solutions: Determining the Q-point
Q-point
IDQ=2.6mAVGSQ=-2.6mV
![Page 53: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/53.jpg)
Mathematical Solutions
VVandmAIchoosetherefore
VV
kmAkmA
RIVRIV
mAImAI
IkI
kIII
MIkIkIm
kIm
kImI
V
RII
RIVrecallV
VII
GSD
SDGSSDGS
DD
DD
DDD
DDD
DDD
P
SDDSS
SDGSP
GSDSSD
6.2588.2;
6.29.13
)1(588.2)1(9.13
588.29.13
0288.01328
896288.036
1663636
8
6
)1(68
6
)1(18
)(1
1
211
2
2
2
22
2
2
![Page 54: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/54.jpg)
SolutionsGSQV = - 2.6V
DS DD D D SV = V - I R + R
= 20V - 2.6mA 4.3kΩ
= 8.82V
IDQ = 2.6mA
ID=I
S
![Page 55: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/55.jpg)
Voltage-divider bias
A
IG=0A
![Page 56: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/56.jpg)
Redrawn network
2G DD
1 2
RV = V
R + R
![Page 57: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/57.jpg)
Sketching the network equation for the voltage-divider configuration.
D
GS
GS G I =0mA
GD
S V =0V
V = V
VI
R
G GS RS
GS G RS
GS G D SV
V - V - V = 0
V = V
= V - I
V
R
-
![Page 58: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/58.jpg)
Effect of RS on the resulting Q-point.
![Page 59: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/59.jpg)
Example : Voltage-divider bias
DQ GSQ
D
S
DS
DG
1. I andV
2. V
3. V
Determine the following for th
4. V
e netw k
5. V
or
![Page 60: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/60.jpg)
Solutions
2G DD
1 2
DD2
RV = V
R + R
270kΩ 16V = V
2.1MΩ + 0.27MΩ
= 1.82V
D GSWhen I = 0mA, V = +1.82V
GS G D S
D
V = V - I R
= 1.82V - I 1.5kΩ
GS D
+1.82VWhen V = 0V, I = = 1.21mA
1.5kΩ
![Page 61: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/61.jpg)
Determining the Q-point for the network
GS DV = 1.82V - I 1.5kΩ
IDQ=2.4mAVGSQ=-1.8V
DS DD SS D S D
DS S
V = V + V - I R R
= V + V = 8.82V + 2 11.6V = .42V
![Page 62: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/62.jpg)
Mathematical solutions
How to get IDS, VGS and VDS for voltage-divider bias configuration by using mathematical solutions?
![Page 63: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/63.jpg)
Exercise 3:
DQ GSQ
DS
D
S
1. I andV
2. V
Determine the
followi
3. V
ng for the
networ
4. V
k
![Page 64: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/64.jpg)
Drawing the self bias line
GS D S
GS D
V + I R -10V = 0
V = 10V - I 1.5k
D GSWhen I = 0mA, V = 10V
GS D
10VWhen V = 0V, I = = 6.67mA
1.5kΩ
![Page 65: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/65.jpg)
Determining the Q-point IDQ=6.9mAVGSQ=-0.35V DS DD SS D S DV = V - V - I R + R
= 20 +10 - (6.9mA)(1.8kΩ +1.5kΩ)
= 7.23V
D DD D DV = V - I R = 7.58V
S D DSV = V - V
= 7.58V - 7.23V = 0.35V
![Page 66: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/66.jpg)
Exercise 4
D S
Determine the required
values of R and R
![Page 67: CHAPTER 4 :JFET](https://reader033.vdocuments.net/reader033/viewer/2022061308/5681400e550346895dab4a00/html5/thumbnails/67.jpg)
Determining VGSQ for the network.
DD DQRDD
DQ DQ
V VV 20V 12VR = =
I I 2.5mA
= 3.2k
GSQ
SDQ
V -1R = = 0.4k
I 2.5mA